1 /*
2 * @file op_model_amd.c
3 * athlon / K7 / K8 / Family 10h model-specific MSR operations
4 *
5 * @remark Copyright 2002-2009 OProfile authors
6 * @remark Read the file COPYING
7 *
8 * @author John Levon
9 * @author Philippe Elie
10 * @author Graydon Hoare
11 * @author Robert Richter <robert.richter@amd.com>
12 * @author Barry Kasindorf
13 */
14
15 #include <linux/oprofile.h>
16 #include <linux/device.h>
17 #include <linux/pci.h>
18
19 #include <asm/ptrace.h>
20 #include <asm/msr.h>
21 #include <asm/nmi.h>
22
23 #include "op_x86_model.h"
24 #include "op_counter.h"
25
26 #define NUM_COUNTERS 4
27 #define NUM_CONTROLS 4
28
29 #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
30 #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
31 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
32 #define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
33
34 #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
35 #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
36 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
37 #define CTRL_SET_ACTIVE(n) (n |= (1<<22))
38 #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
39 #define CTRL_CLEAR_LO(x) (x &= (1<<21))
40 #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
41 #define CTRL_SET_ENABLE(val) (val |= 1<<20)
42 #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
43 #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
44 #define CTRL_SET_UM(val, m) (val |= (m << 8))
45 #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
46 #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
47 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
48 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
49
50 static unsigned long reset_value[NUM_COUNTERS];
51
52 #ifdef CONFIG_OPROFILE_IBS
53
54 /* IbsFetchCtl bits/masks */
55 #define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */
56 #define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */
57 #define IBS_FETCH_LOW_MAX_CNT_MASK 0x0000FFFFUL /* MaxCnt mask */
58
59 /*IbsOpCtl bits */
60 #define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */
61 #define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */
62
63 #define IBS_FETCH_SIZE 6
64 #define IBS_OP_SIZE 12
65
66 static int has_ibs; /* AMD Family10h and later */
67
68 struct op_ibs_config {
69 unsigned long op_enabled;
70 unsigned long fetch_enabled;
71 unsigned long max_cnt_fetch;
72 unsigned long max_cnt_op;
73 unsigned long rand_en;
74 unsigned long dispatched_ops;
75 };
76
77 static struct op_ibs_config ibs_config;
78
79 #endif
80
81 /* functions for op_amd_spec */
82
op_amd_fill_in_addresses(struct op_msrs * const msrs)83 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
84 {
85 int i;
86
87 for (i = 0; i < NUM_COUNTERS; i++) {
88 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
89 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
90 else
91 msrs->counters[i].addr = 0;
92 }
93
94 for (i = 0; i < NUM_CONTROLS; i++) {
95 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
96 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
97 else
98 msrs->controls[i].addr = 0;
99 }
100 }
101
102
op_amd_setup_ctrs(struct op_msrs const * const msrs)103 static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
104 {
105 unsigned int low, high;
106 int i;
107
108 /* clear all counters */
109 for (i = 0 ; i < NUM_CONTROLS; ++i) {
110 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
111 continue;
112 CTRL_READ(low, high, msrs, i);
113 CTRL_CLEAR_LO(low);
114 CTRL_CLEAR_HI(high);
115 CTRL_WRITE(low, high, msrs, i);
116 }
117
118 /* avoid a false detection of ctr overflows in NMI handler */
119 for (i = 0; i < NUM_COUNTERS; ++i) {
120 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
121 continue;
122 CTR_WRITE(1, msrs, i);
123 }
124
125 /* enable active counters */
126 for (i = 0; i < NUM_COUNTERS; ++i) {
127 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
128 reset_value[i] = counter_config[i].count;
129
130 CTR_WRITE(counter_config[i].count, msrs, i);
131
132 CTRL_READ(low, high, msrs, i);
133 CTRL_CLEAR_LO(low);
134 CTRL_CLEAR_HI(high);
135 CTRL_SET_ENABLE(low);
136 CTRL_SET_USR(low, counter_config[i].user);
137 CTRL_SET_KERN(low, counter_config[i].kernel);
138 CTRL_SET_UM(low, counter_config[i].unit_mask);
139 CTRL_SET_EVENT_LOW(low, counter_config[i].event);
140 CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
141 CTRL_SET_HOST_ONLY(high, 0);
142 CTRL_SET_GUEST_ONLY(high, 0);
143
144 CTRL_WRITE(low, high, msrs, i);
145 } else {
146 reset_value[i] = 0;
147 }
148 }
149 }
150
151 #ifdef CONFIG_OPROFILE_IBS
152
153 static inline int
op_amd_handle_ibs(struct pt_regs * const regs,struct op_msrs const * const msrs)154 op_amd_handle_ibs(struct pt_regs * const regs,
155 struct op_msrs const * const msrs)
156 {
157 u32 low, high;
158 u64 msr;
159 struct op_entry entry;
160
161 if (!has_ibs)
162 return 1;
163
164 if (ibs_config.fetch_enabled) {
165 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
166 if (high & IBS_FETCH_HIGH_VALID_BIT) {
167 rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr);
168 oprofile_write_reserve(&entry, regs, msr,
169 IBS_FETCH_CODE, IBS_FETCH_SIZE);
170 oprofile_add_data(&entry, (u32)msr);
171 oprofile_add_data(&entry, (u32)(msr >> 32));
172 oprofile_add_data(&entry, low);
173 oprofile_add_data(&entry, high);
174 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr);
175 oprofile_add_data(&entry, (u32)msr);
176 oprofile_add_data(&entry, (u32)(msr >> 32));
177 oprofile_write_commit(&entry);
178
179 /* reenable the IRQ */
180 high &= ~IBS_FETCH_HIGH_VALID_BIT;
181 high |= IBS_FETCH_HIGH_ENABLE;
182 low &= IBS_FETCH_LOW_MAX_CNT_MASK;
183 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
184 }
185 }
186
187 if (ibs_config.op_enabled) {
188 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
189 if (low & IBS_OP_LOW_VALID_BIT) {
190 rdmsrl(MSR_AMD64_IBSOPRIP, msr);
191 oprofile_write_reserve(&entry, regs, msr,
192 IBS_OP_CODE, IBS_OP_SIZE);
193 oprofile_add_data(&entry, (u32)msr);
194 oprofile_add_data(&entry, (u32)(msr >> 32));
195 rdmsrl(MSR_AMD64_IBSOPDATA, msr);
196 oprofile_add_data(&entry, (u32)msr);
197 oprofile_add_data(&entry, (u32)(msr >> 32));
198 rdmsrl(MSR_AMD64_IBSOPDATA2, msr);
199 oprofile_add_data(&entry, (u32)msr);
200 oprofile_add_data(&entry, (u32)(msr >> 32));
201 rdmsrl(MSR_AMD64_IBSOPDATA3, msr);
202 oprofile_add_data(&entry, (u32)msr);
203 oprofile_add_data(&entry, (u32)(msr >> 32));
204 rdmsrl(MSR_AMD64_IBSDCLINAD, msr);
205 oprofile_add_data(&entry, (u32)msr);
206 oprofile_add_data(&entry, (u32)(msr >> 32));
207 rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr);
208 oprofile_add_data(&entry, (u32)msr);
209 oprofile_add_data(&entry, (u32)(msr >> 32));
210 oprofile_write_commit(&entry);
211
212 /* reenable the IRQ */
213 high = 0;
214 low &= ~IBS_OP_LOW_VALID_BIT;
215 low |= IBS_OP_LOW_ENABLE;
216 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
217 }
218 }
219
220 return 1;
221 }
222
223 #endif
224
op_amd_check_ctrs(struct pt_regs * const regs,struct op_msrs const * const msrs)225 static int op_amd_check_ctrs(struct pt_regs * const regs,
226 struct op_msrs const * const msrs)
227 {
228 unsigned int low, high;
229 int i;
230
231 for (i = 0 ; i < NUM_COUNTERS; ++i) {
232 if (!reset_value[i])
233 continue;
234 CTR_READ(low, high, msrs, i);
235 if (CTR_OVERFLOWED(low)) {
236 oprofile_add_sample(regs, i);
237 CTR_WRITE(reset_value[i], msrs, i);
238 }
239 }
240
241 #ifdef CONFIG_OPROFILE_IBS
242 op_amd_handle_ibs(regs, msrs);
243 #endif
244
245 /* See op_model_ppro.c */
246 return 1;
247 }
248
op_amd_start(struct op_msrs const * const msrs)249 static void op_amd_start(struct op_msrs const * const msrs)
250 {
251 unsigned int low, high;
252 int i;
253 for (i = 0 ; i < NUM_COUNTERS ; ++i) {
254 if (reset_value[i]) {
255 CTRL_READ(low, high, msrs, i);
256 CTRL_SET_ACTIVE(low);
257 CTRL_WRITE(low, high, msrs, i);
258 }
259 }
260
261 #ifdef CONFIG_OPROFILE_IBS
262 if (has_ibs && ibs_config.fetch_enabled) {
263 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
264 high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
265 + IBS_FETCH_HIGH_ENABLE;
266 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
267 }
268
269 if (has_ibs && ibs_config.op_enabled) {
270 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
271 + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
272 + IBS_OP_LOW_ENABLE;
273 high = 0;
274 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
275 }
276 #endif
277 }
278
279
op_amd_stop(struct op_msrs const * const msrs)280 static void op_amd_stop(struct op_msrs const * const msrs)
281 {
282 unsigned int low, high;
283 int i;
284
285 /*
286 * Subtle: stop on all counters to avoid race with setting our
287 * pm callback
288 */
289 for (i = 0 ; i < NUM_COUNTERS ; ++i) {
290 if (!reset_value[i])
291 continue;
292 CTRL_READ(low, high, msrs, i);
293 CTRL_SET_INACTIVE(low);
294 CTRL_WRITE(low, high, msrs, i);
295 }
296
297 #ifdef CONFIG_OPROFILE_IBS
298 if (has_ibs && ibs_config.fetch_enabled) {
299 /* clear max count and enable */
300 low = 0;
301 high = 0;
302 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
303 }
304
305 if (has_ibs && ibs_config.op_enabled) {
306 /* clear max count and enable */
307 low = 0;
308 high = 0;
309 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
310 }
311 #endif
312 }
313
op_amd_shutdown(struct op_msrs const * const msrs)314 static void op_amd_shutdown(struct op_msrs const * const msrs)
315 {
316 int i;
317
318 for (i = 0 ; i < NUM_COUNTERS ; ++i) {
319 if (CTR_IS_RESERVED(msrs, i))
320 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
321 }
322 for (i = 0 ; i < NUM_CONTROLS ; ++i) {
323 if (CTRL_IS_RESERVED(msrs, i))
324 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
325 }
326 }
327
328 #ifdef CONFIG_OPROFILE_IBS
329
330 static u8 ibs_eilvt_off;
331
apic_init_ibs_nmi_per_cpu(void * arg)332 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
333 {
334 ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
335 }
336
apic_clear_ibs_nmi_per_cpu(void * arg)337 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
338 {
339 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
340 }
341
init_ibs_nmi(void)342 static int init_ibs_nmi(void)
343 {
344 #define IBSCTL_LVTOFFSETVAL (1 << 8)
345 #define IBSCTL 0x1cc
346 struct pci_dev *cpu_cfg;
347 int nodes;
348 u32 value = 0;
349
350 /* per CPU setup */
351 on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
352
353 nodes = 0;
354 cpu_cfg = NULL;
355 do {
356 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
357 PCI_DEVICE_ID_AMD_10H_NB_MISC,
358 cpu_cfg);
359 if (!cpu_cfg)
360 break;
361 ++nodes;
362 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
363 | IBSCTL_LVTOFFSETVAL);
364 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
365 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
366 pci_dev_put(cpu_cfg);
367 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
368 "IBSCTL = 0x%08x", value);
369 return 1;
370 }
371 } while (1);
372
373 if (!nodes) {
374 printk(KERN_DEBUG "No CPU node configured for IBS");
375 return 1;
376 }
377
378 #ifdef CONFIG_NUMA
379 /* Sanity check */
380 /* Works only for 64bit with proper numa implementation. */
381 if (nodes != num_possible_nodes()) {
382 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
383 "found: %d, expected %d",
384 nodes, num_possible_nodes());
385 return 1;
386 }
387 #endif
388 return 0;
389 }
390
391 /* uninitialize the APIC for the IBS interrupts if needed */
clear_ibs_nmi(void)392 static void clear_ibs_nmi(void)
393 {
394 if (has_ibs)
395 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
396 }
397
398 /* initialize the APIC for the IBS interrupts if available */
ibs_init(void)399 static void ibs_init(void)
400 {
401 has_ibs = boot_cpu_has(X86_FEATURE_IBS);
402
403 if (!has_ibs)
404 return;
405
406 if (init_ibs_nmi()) {
407 has_ibs = 0;
408 return;
409 }
410
411 printk(KERN_INFO "oprofile: AMD IBS detected\n");
412 }
413
ibs_exit(void)414 static void ibs_exit(void)
415 {
416 if (!has_ibs)
417 return;
418
419 clear_ibs_nmi();
420 }
421
422 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
423
setup_ibs_files(struct super_block * sb,struct dentry * root)424 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
425 {
426 struct dentry *dir;
427 int ret = 0;
428
429 /* architecture specific files */
430 if (create_arch_files)
431 ret = create_arch_files(sb, root);
432
433 if (ret)
434 return ret;
435
436 if (!has_ibs)
437 return ret;
438
439 /* model specific files */
440
441 /* setup some reasonable defaults */
442 ibs_config.max_cnt_fetch = 250000;
443 ibs_config.fetch_enabled = 0;
444 ibs_config.max_cnt_op = 250000;
445 ibs_config.op_enabled = 0;
446 ibs_config.dispatched_ops = 1;
447
448 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
449 oprofilefs_create_ulong(sb, dir, "enable",
450 &ibs_config.fetch_enabled);
451 oprofilefs_create_ulong(sb, dir, "max_count",
452 &ibs_config.max_cnt_fetch);
453 oprofilefs_create_ulong(sb, dir, "rand_enable",
454 &ibs_config.rand_en);
455
456 dir = oprofilefs_mkdir(sb, root, "ibs_op");
457 oprofilefs_create_ulong(sb, dir, "enable",
458 &ibs_config.op_enabled);
459 oprofilefs_create_ulong(sb, dir, "max_count",
460 &ibs_config.max_cnt_op);
461 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
462 &ibs_config.dispatched_ops);
463
464 return 0;
465 }
466
op_amd_init(struct oprofile_operations * ops)467 static int op_amd_init(struct oprofile_operations *ops)
468 {
469 ibs_init();
470 create_arch_files = ops->create_files;
471 ops->create_files = setup_ibs_files;
472 return 0;
473 }
474
op_amd_exit(void)475 static void op_amd_exit(void)
476 {
477 ibs_exit();
478 }
479
480 #else
481
482 /* no IBS support */
483
op_amd_init(struct oprofile_operations * ops)484 static int op_amd_init(struct oprofile_operations *ops)
485 {
486 return 0;
487 }
488
op_amd_exit(void)489 static void op_amd_exit(void) {}
490
491 #endif /* CONFIG_OPROFILE_IBS */
492
493 struct op_x86_model_spec const op_amd_spec = {
494 .init = op_amd_init,
495 .exit = op_amd_exit,
496 .num_counters = NUM_COUNTERS,
497 .num_controls = NUM_CONTROLS,
498 .fill_in_addresses = &op_amd_fill_in_addresses,
499 .setup_ctrs = &op_amd_setup_ctrs,
500 .check_ctrs = &op_amd_check_ctrs,
501 .start = &op_amd_start,
502 .stop = &op_amd_stop,
503 .shutdown = &op_amd_shutdown
504 };
505