1 /*
2 * @file op_model_ppro.h
3 * Family 6 perfmon and architectural perfmon MSR operations
4 *
5 * @remark Copyright 2002 OProfile authors
6 * @remark Copyright 2008 Intel Corporation
7 * @remark Read the file COPYING
8 *
9 * @author John Levon
10 * @author Philippe Elie
11 * @author Graydon Hoare
12 * @author Andi Kleen
13 */
14
15 #include <linux/oprofile.h>
16 #include <linux/slab.h>
17 #include <asm/ptrace.h>
18 #include <asm/msr.h>
19 #include <asm/apic.h>
20 #include <asm/nmi.h>
21 #include <asm/intel_arch_perfmon.h>
22
23 #include "op_x86_model.h"
24 #include "op_counter.h"
25
26 static int num_counters = 2;
27 static int counter_width = 32;
28
29 #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
30 #define CTR_OVERFLOWED(n) (!((n) & (1ULL<<(counter_width-1))))
31
32 #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
33 #define CTRL_READ(l, h, msrs, c) do {rdmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
34 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
35 #define CTRL_SET_ACTIVE(n) (n |= (1<<22))
36 #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
37 #define CTRL_CLEAR(x) (x &= (1<<21))
38 #define CTRL_SET_ENABLE(val) (val |= 1<<20)
39 #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
40 #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
41 #define CTRL_SET_UM(val, m) (val |= (m << 8))
42 #define CTRL_SET_EVENT(val, e) (val |= e)
43
44 static u64 *reset_value;
45
ppro_fill_in_addresses(struct op_msrs * const msrs)46 static void ppro_fill_in_addresses(struct op_msrs * const msrs)
47 {
48 int i;
49
50 for (i = 0; i < num_counters; i++) {
51 if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
52 msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
53 else
54 msrs->counters[i].addr = 0;
55 }
56
57 for (i = 0; i < num_counters; i++) {
58 if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
59 msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
60 else
61 msrs->controls[i].addr = 0;
62 }
63 }
64
65
ppro_setup_ctrs(struct op_msrs const * const msrs)66 static void ppro_setup_ctrs(struct op_msrs const * const msrs)
67 {
68 unsigned int low, high;
69 int i;
70
71 if (!reset_value) {
72 reset_value = kmalloc(sizeof(reset_value[0]) * num_counters,
73 GFP_ATOMIC);
74 if (!reset_value)
75 return;
76 }
77
78 if (cpu_has_arch_perfmon) {
79 union cpuid10_eax eax;
80 eax.full = cpuid_eax(0xa);
81
82 /*
83 * For Core2 (family 6, model 15), don't reset the
84 * counter width:
85 */
86 if (!(eax.split.version_id == 0 &&
87 current_cpu_data.x86 == 6 &&
88 current_cpu_data.x86_model == 15)) {
89
90 if (counter_width < eax.split.bit_width)
91 counter_width = eax.split.bit_width;
92 }
93 }
94
95 /* clear all counters */
96 for (i = 0 ; i < num_counters; ++i) {
97 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
98 continue;
99 CTRL_READ(low, high, msrs, i);
100 CTRL_CLEAR(low);
101 CTRL_WRITE(low, high, msrs, i);
102 }
103
104 /* avoid a false detection of ctr overflows in NMI handler */
105 for (i = 0; i < num_counters; ++i) {
106 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
107 continue;
108 wrmsrl(msrs->counters[i].addr, -1LL);
109 }
110
111 /* enable active counters */
112 for (i = 0; i < num_counters; ++i) {
113 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
114 reset_value[i] = counter_config[i].count;
115
116 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
117
118 CTRL_READ(low, high, msrs, i);
119 CTRL_CLEAR(low);
120 CTRL_SET_ENABLE(low);
121 CTRL_SET_USR(low, counter_config[i].user);
122 CTRL_SET_KERN(low, counter_config[i].kernel);
123 CTRL_SET_UM(low, counter_config[i].unit_mask);
124 CTRL_SET_EVENT(low, counter_config[i].event);
125 CTRL_WRITE(low, high, msrs, i);
126 } else {
127 reset_value[i] = 0;
128 }
129 }
130 }
131
132
ppro_check_ctrs(struct pt_regs * const regs,struct op_msrs const * const msrs)133 static int ppro_check_ctrs(struct pt_regs * const regs,
134 struct op_msrs const * const msrs)
135 {
136 u64 val;
137 int i;
138
139 for (i = 0 ; i < num_counters; ++i) {
140 if (!reset_value[i])
141 continue;
142 rdmsrl(msrs->counters[i].addr, val);
143 if (CTR_OVERFLOWED(val)) {
144 oprofile_add_sample(regs, i);
145 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
146 }
147 }
148
149 /* Only P6 based Pentium M need to re-unmask the apic vector but it
150 * doesn't hurt other P6 variant */
151 apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
152
153 /* We can't work out if we really handled an interrupt. We
154 * might have caught a *second* counter just after overflowing
155 * the interrupt for this counter then arrives
156 * and we don't find a counter that's overflowed, so we
157 * would return 0 and get dazed + confused. Instead we always
158 * assume we found an overflow. This sucks.
159 */
160 return 1;
161 }
162
163
ppro_start(struct op_msrs const * const msrs)164 static void ppro_start(struct op_msrs const * const msrs)
165 {
166 unsigned int low, high;
167 int i;
168
169 if (!reset_value)
170 return;
171 for (i = 0; i < num_counters; ++i) {
172 if (reset_value[i]) {
173 CTRL_READ(low, high, msrs, i);
174 CTRL_SET_ACTIVE(low);
175 CTRL_WRITE(low, high, msrs, i);
176 }
177 }
178 }
179
180
ppro_stop(struct op_msrs const * const msrs)181 static void ppro_stop(struct op_msrs const * const msrs)
182 {
183 unsigned int low, high;
184 int i;
185
186 if (!reset_value)
187 return;
188 for (i = 0; i < num_counters; ++i) {
189 if (!reset_value[i])
190 continue;
191 CTRL_READ(low, high, msrs, i);
192 CTRL_SET_INACTIVE(low);
193 CTRL_WRITE(low, high, msrs, i);
194 }
195 }
196
ppro_shutdown(struct op_msrs const * const msrs)197 static void ppro_shutdown(struct op_msrs const * const msrs)
198 {
199 int i;
200
201 for (i = 0 ; i < num_counters ; ++i) {
202 if (CTR_IS_RESERVED(msrs, i))
203 release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
204 }
205 for (i = 0 ; i < num_counters ; ++i) {
206 if (CTRL_IS_RESERVED(msrs, i))
207 release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
208 }
209 if (reset_value) {
210 kfree(reset_value);
211 reset_value = NULL;
212 }
213 }
214
215
216 struct op_x86_model_spec op_ppro_spec = {
217 .num_counters = 2, /* can be overriden */
218 .num_controls = 2, /* dito */
219 .fill_in_addresses = &ppro_fill_in_addresses,
220 .setup_ctrs = &ppro_setup_ctrs,
221 .check_ctrs = &ppro_check_ctrs,
222 .start = &ppro_start,
223 .stop = &ppro_stop,
224 .shutdown = &ppro_shutdown
225 };
226
227 /*
228 * Architectural performance monitoring.
229 *
230 * Newer Intel CPUs (Core1+) have support for architectural
231 * events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.
232 * The advantage of this is that it can be done without knowing about
233 * the specific CPU.
234 */
235
arch_perfmon_setup_counters(void)236 void arch_perfmon_setup_counters(void)
237 {
238 union cpuid10_eax eax;
239
240 eax.full = cpuid_eax(0xa);
241
242 /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
243 if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 &&
244 current_cpu_data.x86_model == 15) {
245 eax.split.version_id = 2;
246 eax.split.num_counters = 2;
247 eax.split.bit_width = 40;
248 }
249
250 num_counters = eax.split.num_counters;
251
252 op_arch_perfmon_spec.num_counters = num_counters;
253 op_arch_perfmon_spec.num_controls = num_counters;
254 op_ppro_spec.num_counters = num_counters;
255 op_ppro_spec.num_controls = num_counters;
256 }
257
258 struct op_x86_model_spec op_arch_perfmon_spec = {
259 /* num_counters/num_controls filled in at runtime */
260 .fill_in_addresses = &ppro_fill_in_addresses,
261 /* user space does the cpuid check for available events */
262 .setup_ctrs = &ppro_setup_ctrs,
263 .check_ctrs = &ppro_check_ctrs,
264 .start = &ppro_start,
265 .stop = &ppro_stop,
266 .shutdown = &ppro_shutdown
267 };
268