1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "2.12"
50
51 enum {
52 PDC_MAX_PORTS = 4,
53 PDC_MMIO_BAR = 3,
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55
56 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_FLASH_CTL = 0x44, /* Flash control register */
59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
60 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
61 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
63
64 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
65 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
66 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
67 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
68 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
69 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
70 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
71 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
72 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
73 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
74 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
75 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
76
77 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
78 PDC_PHYMODE4 = 0x14,
79
80 /* PDC_GLOBAL_CTL bit definitions */
81 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
82 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
83 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
84 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
85 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
86 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
87 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
88 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
89 PDC_DRIVE_ERR = (1 << 21), /* drive error */
90 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
91 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
92 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
93 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
94 PDC2_ATA_DMA_CNT_ERR,
95 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
96 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
97 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
98 PDC1_ERR_MASK | PDC2_ERR_MASK,
99
100 board_2037x = 0, /* FastTrak S150 TX2plus */
101 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
102 board_20319 = 2, /* FastTrak S150 TX4 */
103 board_20619 = 3, /* FastTrak TX4000 */
104 board_2057x = 4, /* SATAII150 Tx2plus */
105 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
106 board_40518 = 6, /* SATAII150 Tx4 */
107
108 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
109
110 /* Sequence counter control registers bit definitions */
111 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
112
113 /* Feature register values */
114 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
115 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
116
117 /* Device/Head register values */
118 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
119
120 /* PDC_CTLSTAT bit definitions */
121 PDC_DMA_ENABLE = (1 << 7),
122 PDC_IRQ_DISABLE = (1 << 10),
123 PDC_RESET = (1 << 11), /* HDMA reset */
124
125 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
126 ATA_FLAG_MMIO |
127 ATA_FLAG_PIO_POLLING,
128
129 /* ap->flags bits */
130 PDC_FLAG_GEN_II = (1 << 24),
131 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
132 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
133 };
134
135 struct pdc_port_priv {
136 u8 *pkt;
137 dma_addr_t pkt_dma;
138 };
139
140 static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
141 static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
142 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
143 static int pdc_common_port_start(struct ata_port *ap);
144 static int pdc_sata_port_start(struct ata_port *ap);
145 static void pdc_qc_prep(struct ata_queued_cmd *qc);
146 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
147 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
148 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
149 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
150 static void pdc_irq_clear(struct ata_port *ap);
151 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
152 static void pdc_freeze(struct ata_port *ap);
153 static void pdc_sata_freeze(struct ata_port *ap);
154 static void pdc_thaw(struct ata_port *ap);
155 static void pdc_sata_thaw(struct ata_port *ap);
156 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
157 unsigned long deadline);
158 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
159 unsigned long deadline);
160 static void pdc_error_handler(struct ata_port *ap);
161 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
162 static int pdc_pata_cable_detect(struct ata_port *ap);
163 static int pdc_sata_cable_detect(struct ata_port *ap);
164
165 static struct scsi_host_template pdc_ata_sht = {
166 ATA_BASE_SHT(DRV_NAME),
167 .sg_tablesize = PDC_MAX_PRD,
168 .dma_boundary = ATA_DMA_BOUNDARY,
169 };
170
171 static const struct ata_port_operations pdc_common_ops = {
172 .inherits = &ata_sff_port_ops,
173
174 .sff_tf_load = pdc_tf_load_mmio,
175 .sff_exec_command = pdc_exec_command_mmio,
176 .check_atapi_dma = pdc_check_atapi_dma,
177 .qc_prep = pdc_qc_prep,
178 .qc_issue = pdc_qc_issue,
179 .sff_irq_clear = pdc_irq_clear,
180
181 .post_internal_cmd = pdc_post_internal_cmd,
182 .error_handler = pdc_error_handler,
183 };
184
185 static struct ata_port_operations pdc_sata_ops = {
186 .inherits = &pdc_common_ops,
187 .cable_detect = pdc_sata_cable_detect,
188 .freeze = pdc_sata_freeze,
189 .thaw = pdc_sata_thaw,
190 .scr_read = pdc_sata_scr_read,
191 .scr_write = pdc_sata_scr_write,
192 .port_start = pdc_sata_port_start,
193 .hardreset = pdc_sata_hardreset,
194 };
195
196 /* First-generation chips need a more restrictive ->check_atapi_dma op */
197 static struct ata_port_operations pdc_old_sata_ops = {
198 .inherits = &pdc_sata_ops,
199 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
200 };
201
202 static struct ata_port_operations pdc_pata_ops = {
203 .inherits = &pdc_common_ops,
204 .cable_detect = pdc_pata_cable_detect,
205 .freeze = pdc_freeze,
206 .thaw = pdc_thaw,
207 .port_start = pdc_common_port_start,
208 .softreset = pdc_pata_softreset,
209 };
210
211 static const struct ata_port_info pdc_port_info[] = {
212 [board_2037x] =
213 {
214 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
215 PDC_FLAG_SATA_PATA,
216 .pio_mask = 0x1f, /* pio0-4 */
217 .mwdma_mask = 0x07, /* mwdma0-2 */
218 .udma_mask = ATA_UDMA6,
219 .port_ops = &pdc_old_sata_ops,
220 },
221
222 [board_2037x_pata] =
223 {
224 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
225 .pio_mask = 0x1f, /* pio0-4 */
226 .mwdma_mask = 0x07, /* mwdma0-2 */
227 .udma_mask = ATA_UDMA6,
228 .port_ops = &pdc_pata_ops,
229 },
230
231 [board_20319] =
232 {
233 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
234 PDC_FLAG_4_PORTS,
235 .pio_mask = 0x1f, /* pio0-4 */
236 .mwdma_mask = 0x07, /* mwdma0-2 */
237 .udma_mask = ATA_UDMA6,
238 .port_ops = &pdc_old_sata_ops,
239 },
240
241 [board_20619] =
242 {
243 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
244 PDC_FLAG_4_PORTS,
245 .pio_mask = 0x1f, /* pio0-4 */
246 .mwdma_mask = 0x07, /* mwdma0-2 */
247 .udma_mask = ATA_UDMA6,
248 .port_ops = &pdc_pata_ops,
249 },
250
251 [board_2057x] =
252 {
253 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
254 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
255 .pio_mask = 0x1f, /* pio0-4 */
256 .mwdma_mask = 0x07, /* mwdma0-2 */
257 .udma_mask = ATA_UDMA6,
258 .port_ops = &pdc_sata_ops,
259 },
260
261 [board_2057x_pata] =
262 {
263 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
264 PDC_FLAG_GEN_II,
265 .pio_mask = 0x1f, /* pio0-4 */
266 .mwdma_mask = 0x07, /* mwdma0-2 */
267 .udma_mask = ATA_UDMA6,
268 .port_ops = &pdc_pata_ops,
269 },
270
271 [board_40518] =
272 {
273 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
274 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
275 .pio_mask = 0x1f, /* pio0-4 */
276 .mwdma_mask = 0x07, /* mwdma0-2 */
277 .udma_mask = ATA_UDMA6,
278 .port_ops = &pdc_sata_ops,
279 },
280 };
281
282 static const struct pci_device_id pdc_ata_pci_tbl[] = {
283 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
284 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
285 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
286 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
287 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
288 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
289 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
290 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
291 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
292 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
293
294 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
295 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
296 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
297 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
298 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
299 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
300
301 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
302
303 { } /* terminate list */
304 };
305
306 static struct pci_driver pdc_ata_pci_driver = {
307 .name = DRV_NAME,
308 .id_table = pdc_ata_pci_tbl,
309 .probe = pdc_ata_init_one,
310 .remove = ata_pci_remove_one,
311 };
312
pdc_common_port_start(struct ata_port * ap)313 static int pdc_common_port_start(struct ata_port *ap)
314 {
315 struct device *dev = ap->host->dev;
316 struct pdc_port_priv *pp;
317 int rc;
318
319 rc = ata_port_start(ap);
320 if (rc)
321 return rc;
322
323 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
324 if (!pp)
325 return -ENOMEM;
326
327 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
328 if (!pp->pkt)
329 return -ENOMEM;
330
331 ap->private_data = pp;
332
333 return 0;
334 }
335
pdc_sata_port_start(struct ata_port * ap)336 static int pdc_sata_port_start(struct ata_port *ap)
337 {
338 int rc;
339
340 rc = pdc_common_port_start(ap);
341 if (rc)
342 return rc;
343
344 /* fix up PHYMODE4 align timing */
345 if (ap->flags & PDC_FLAG_GEN_II) {
346 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
347 unsigned int tmp;
348
349 tmp = readl(sata_mmio + PDC_PHYMODE4);
350 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
351 writel(tmp, sata_mmio + PDC_PHYMODE4);
352 }
353
354 return 0;
355 }
356
pdc_reset_port(struct ata_port * ap)357 static void pdc_reset_port(struct ata_port *ap)
358 {
359 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
360 unsigned int i;
361 u32 tmp;
362
363 for (i = 11; i > 0; i--) {
364 tmp = readl(ata_ctlstat_mmio);
365 if (tmp & PDC_RESET)
366 break;
367
368 udelay(100);
369
370 tmp |= PDC_RESET;
371 writel(tmp, ata_ctlstat_mmio);
372 }
373
374 tmp &= ~PDC_RESET;
375 writel(tmp, ata_ctlstat_mmio);
376 readl(ata_ctlstat_mmio); /* flush */
377 }
378
pdc_pata_cable_detect(struct ata_port * ap)379 static int pdc_pata_cable_detect(struct ata_port *ap)
380 {
381 u8 tmp;
382 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
383
384 tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
385 if (tmp & 0x01)
386 return ATA_CBL_PATA40;
387 return ATA_CBL_PATA80;
388 }
389
pdc_sata_cable_detect(struct ata_port * ap)390 static int pdc_sata_cable_detect(struct ata_port *ap)
391 {
392 return ATA_CBL_SATA;
393 }
394
pdc_sata_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)395 static int pdc_sata_scr_read(struct ata_link *link,
396 unsigned int sc_reg, u32 *val)
397 {
398 if (sc_reg > SCR_CONTROL)
399 return -EINVAL;
400 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
401 return 0;
402 }
403
pdc_sata_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)404 static int pdc_sata_scr_write(struct ata_link *link,
405 unsigned int sc_reg, u32 val)
406 {
407 if (sc_reg > SCR_CONTROL)
408 return -EINVAL;
409 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
410 return 0;
411 }
412
pdc_atapi_pkt(struct ata_queued_cmd * qc)413 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
414 {
415 struct ata_port *ap = qc->ap;
416 dma_addr_t sg_table = ap->prd_dma;
417 unsigned int cdb_len = qc->dev->cdb_len;
418 u8 *cdb = qc->cdb;
419 struct pdc_port_priv *pp = ap->private_data;
420 u8 *buf = pp->pkt;
421 __le32 *buf32 = (__le32 *) buf;
422 unsigned int dev_sel, feature;
423
424 /* set control bits (byte 0), zero delay seq id (byte 3),
425 * and seq id (byte 2)
426 */
427 switch (qc->tf.protocol) {
428 case ATAPI_PROT_DMA:
429 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
430 buf32[0] = cpu_to_le32(PDC_PKT_READ);
431 else
432 buf32[0] = 0;
433 break;
434 case ATAPI_PROT_NODATA:
435 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
436 break;
437 default:
438 BUG();
439 break;
440 }
441 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
442 buf32[2] = 0; /* no next-packet */
443
444 /* select drive */
445 if (sata_scr_valid(&ap->link))
446 dev_sel = PDC_DEVICE_SATA;
447 else
448 dev_sel = qc->tf.device;
449
450 buf[12] = (1 << 5) | ATA_REG_DEVICE;
451 buf[13] = dev_sel;
452 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
453 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
454
455 buf[16] = (1 << 5) | ATA_REG_NSECT;
456 buf[17] = qc->tf.nsect;
457 buf[18] = (1 << 5) | ATA_REG_LBAL;
458 buf[19] = qc->tf.lbal;
459
460 /* set feature and byte counter registers */
461 if (qc->tf.protocol != ATAPI_PROT_DMA)
462 feature = PDC_FEATURE_ATAPI_PIO;
463 else
464 feature = PDC_FEATURE_ATAPI_DMA;
465
466 buf[20] = (1 << 5) | ATA_REG_FEATURE;
467 buf[21] = feature;
468 buf[22] = (1 << 5) | ATA_REG_BYTEL;
469 buf[23] = qc->tf.lbam;
470 buf[24] = (1 << 5) | ATA_REG_BYTEH;
471 buf[25] = qc->tf.lbah;
472
473 /* send ATAPI packet command 0xA0 */
474 buf[26] = (1 << 5) | ATA_REG_CMD;
475 buf[27] = qc->tf.command;
476
477 /* select drive and check DRQ */
478 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
479 buf[29] = dev_sel;
480
481 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
482 BUG_ON(cdb_len & ~0x1E);
483
484 /* append the CDB as the final part */
485 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
486 memcpy(buf+31, cdb, cdb_len);
487 }
488
489 /**
490 * pdc_fill_sg - Fill PCI IDE PRD table
491 * @qc: Metadata associated with taskfile to be transferred
492 *
493 * Fill PCI IDE PRD (scatter-gather) table with segments
494 * associated with the current disk command.
495 * Make sure hardware does not choke on it.
496 *
497 * LOCKING:
498 * spin_lock_irqsave(host lock)
499 *
500 */
pdc_fill_sg(struct ata_queued_cmd * qc)501 static void pdc_fill_sg(struct ata_queued_cmd *qc)
502 {
503 struct ata_port *ap = qc->ap;
504 struct scatterlist *sg;
505 const u32 SG_COUNT_ASIC_BUG = 41*4;
506 unsigned int si, idx;
507 u32 len;
508
509 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
510 return;
511
512 idx = 0;
513 for_each_sg(qc->sg, sg, qc->n_elem, si) {
514 u32 addr, offset;
515 u32 sg_len;
516
517 /* determine if physical DMA addr spans 64K boundary.
518 * Note h/w doesn't support 64-bit, so we unconditionally
519 * truncate dma_addr_t to u32.
520 */
521 addr = (u32) sg_dma_address(sg);
522 sg_len = sg_dma_len(sg);
523
524 while (sg_len) {
525 offset = addr & 0xffff;
526 len = sg_len;
527 if ((offset + sg_len) > 0x10000)
528 len = 0x10000 - offset;
529
530 ap->prd[idx].addr = cpu_to_le32(addr);
531 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
532 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
533
534 idx++;
535 sg_len -= len;
536 addr += len;
537 }
538 }
539
540 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
541
542 if (len > SG_COUNT_ASIC_BUG) {
543 u32 addr;
544
545 VPRINTK("Splitting last PRD.\n");
546
547 addr = le32_to_cpu(ap->prd[idx - 1].addr);
548 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
549 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
550
551 addr = addr + len - SG_COUNT_ASIC_BUG;
552 len = SG_COUNT_ASIC_BUG;
553 ap->prd[idx].addr = cpu_to_le32(addr);
554 ap->prd[idx].flags_len = cpu_to_le32(len);
555 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
556
557 idx++;
558 }
559
560 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
561 }
562
pdc_qc_prep(struct ata_queued_cmd * qc)563 static void pdc_qc_prep(struct ata_queued_cmd *qc)
564 {
565 struct pdc_port_priv *pp = qc->ap->private_data;
566 unsigned int i;
567
568 VPRINTK("ENTER\n");
569
570 switch (qc->tf.protocol) {
571 case ATA_PROT_DMA:
572 pdc_fill_sg(qc);
573 /*FALLTHROUGH*/
574 case ATA_PROT_NODATA:
575 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
576 qc->dev->devno, pp->pkt);
577 if (qc->tf.flags & ATA_TFLAG_LBA48)
578 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
579 else
580 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
581 pdc_pkt_footer(&qc->tf, pp->pkt, i);
582 break;
583 case ATAPI_PROT_PIO:
584 pdc_fill_sg(qc);
585 break;
586 case ATAPI_PROT_DMA:
587 pdc_fill_sg(qc);
588 /*FALLTHROUGH*/
589 case ATAPI_PROT_NODATA:
590 pdc_atapi_pkt(qc);
591 break;
592 default:
593 break;
594 }
595 }
596
pdc_is_sataii_tx4(unsigned long flags)597 static int pdc_is_sataii_tx4(unsigned long flags)
598 {
599 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
600 return (flags & mask) == mask;
601 }
602
pdc_port_no_to_ata_no(unsigned int port_no,int is_sataii_tx4)603 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
604 int is_sataii_tx4)
605 {
606 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
607 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
608 }
609
pdc_sata_nr_ports(const struct ata_port * ap)610 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
611 {
612 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
613 }
614
pdc_sata_ata_port_to_ata_no(const struct ata_port * ap)615 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
616 {
617 const struct ata_host *host = ap->host;
618 unsigned int nr_ports = pdc_sata_nr_ports(ap);
619 unsigned int i;
620
621 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
622 ;
623 BUG_ON(i >= nr_ports);
624 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
625 }
626
pdc_sata_hotplug_offset(const struct ata_port * ap)627 static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap)
628 {
629 return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR;
630 }
631
pdc_freeze(struct ata_port * ap)632 static void pdc_freeze(struct ata_port *ap)
633 {
634 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
635 u32 tmp;
636
637 tmp = readl(ata_mmio + PDC_CTLSTAT);
638 tmp |= PDC_IRQ_DISABLE;
639 tmp &= ~PDC_DMA_ENABLE;
640 writel(tmp, ata_mmio + PDC_CTLSTAT);
641 readl(ata_mmio + PDC_CTLSTAT); /* flush */
642 }
643
pdc_sata_freeze(struct ata_port * ap)644 static void pdc_sata_freeze(struct ata_port *ap)
645 {
646 struct ata_host *host = ap->host;
647 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
648 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
649 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
650 u32 hotplug_status;
651
652 /* Disable hotplug events on this port.
653 *
654 * Locking:
655 * 1) hotplug register accesses must be serialised via host->lock
656 * 2) ap->lock == &ap->host->lock
657 * 3) ->freeze() and ->thaw() are called with ap->lock held
658 */
659 hotplug_status = readl(host_mmio + hotplug_offset);
660 hotplug_status |= 0x11 << (ata_no + 16);
661 writel(hotplug_status, host_mmio + hotplug_offset);
662 readl(host_mmio + hotplug_offset); /* flush */
663
664 pdc_freeze(ap);
665 }
666
pdc_thaw(struct ata_port * ap)667 static void pdc_thaw(struct ata_port *ap)
668 {
669 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
670 u32 tmp;
671
672 /* clear IRQ */
673 readl(ata_mmio + PDC_COMMAND);
674
675 /* turn IRQ back on */
676 tmp = readl(ata_mmio + PDC_CTLSTAT);
677 tmp &= ~PDC_IRQ_DISABLE;
678 writel(tmp, ata_mmio + PDC_CTLSTAT);
679 readl(ata_mmio + PDC_CTLSTAT); /* flush */
680 }
681
pdc_sata_thaw(struct ata_port * ap)682 static void pdc_sata_thaw(struct ata_port *ap)
683 {
684 struct ata_host *host = ap->host;
685 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
686 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
687 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
688 u32 hotplug_status;
689
690 pdc_thaw(ap);
691
692 /* Enable hotplug events on this port.
693 * Locking: see pdc_sata_freeze().
694 */
695 hotplug_status = readl(host_mmio + hotplug_offset);
696 hotplug_status |= 0x11 << ata_no;
697 hotplug_status &= ~(0x11 << (ata_no + 16));
698 writel(hotplug_status, host_mmio + hotplug_offset);
699 readl(host_mmio + hotplug_offset); /* flush */
700 }
701
pdc_pata_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)702 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
703 unsigned long deadline)
704 {
705 pdc_reset_port(link->ap);
706 return ata_sff_softreset(link, class, deadline);
707 }
708
pdc_sata_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)709 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
710 unsigned long deadline)
711 {
712 pdc_reset_port(link->ap);
713 return sata_sff_hardreset(link, class, deadline);
714 }
715
pdc_error_handler(struct ata_port * ap)716 static void pdc_error_handler(struct ata_port *ap)
717 {
718 if (!(ap->pflags & ATA_PFLAG_FROZEN))
719 pdc_reset_port(ap);
720
721 ata_std_error_handler(ap);
722 }
723
pdc_post_internal_cmd(struct ata_queued_cmd * qc)724 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
725 {
726 struct ata_port *ap = qc->ap;
727
728 /* make DMA engine forget about the failed command */
729 if (qc->flags & ATA_QCFLAG_FAILED)
730 pdc_reset_port(ap);
731 }
732
pdc_error_intr(struct ata_port * ap,struct ata_queued_cmd * qc,u32 port_status,u32 err_mask)733 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
734 u32 port_status, u32 err_mask)
735 {
736 struct ata_eh_info *ehi = &ap->link.eh_info;
737 unsigned int ac_err_mask = 0;
738
739 ata_ehi_clear_desc(ehi);
740 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
741 port_status &= err_mask;
742
743 if (port_status & PDC_DRIVE_ERR)
744 ac_err_mask |= AC_ERR_DEV;
745 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
746 ac_err_mask |= AC_ERR_HSM;
747 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
748 ac_err_mask |= AC_ERR_ATA_BUS;
749 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
750 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
751 ac_err_mask |= AC_ERR_HOST_BUS;
752
753 if (sata_scr_valid(&ap->link)) {
754 u32 serror;
755
756 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
757 ehi->serror |= serror;
758 }
759
760 qc->err_mask |= ac_err_mask;
761
762 pdc_reset_port(ap);
763
764 ata_port_abort(ap);
765 }
766
pdc_host_intr(struct ata_port * ap,struct ata_queued_cmd * qc)767 static unsigned int pdc_host_intr(struct ata_port *ap,
768 struct ata_queued_cmd *qc)
769 {
770 unsigned int handled = 0;
771 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
772 u32 port_status, err_mask;
773
774 err_mask = PDC_ERR_MASK;
775 if (ap->flags & PDC_FLAG_GEN_II)
776 err_mask &= ~PDC1_ERR_MASK;
777 else
778 err_mask &= ~PDC2_ERR_MASK;
779 port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
780 if (unlikely(port_status & err_mask)) {
781 pdc_error_intr(ap, qc, port_status, err_mask);
782 return 1;
783 }
784
785 switch (qc->tf.protocol) {
786 case ATA_PROT_DMA:
787 case ATA_PROT_NODATA:
788 case ATAPI_PROT_DMA:
789 case ATAPI_PROT_NODATA:
790 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
791 ata_qc_complete(qc);
792 handled = 1;
793 break;
794 default:
795 ap->stats.idle_irq++;
796 break;
797 }
798
799 return handled;
800 }
801
pdc_irq_clear(struct ata_port * ap)802 static void pdc_irq_clear(struct ata_port *ap)
803 {
804 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
805
806 readl(ata_mmio + PDC_COMMAND);
807 }
808
pdc_interrupt(int irq,void * dev_instance)809 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
810 {
811 struct ata_host *host = dev_instance;
812 struct ata_port *ap;
813 u32 mask = 0;
814 unsigned int i, tmp;
815 unsigned int handled = 0;
816 void __iomem *host_mmio;
817 unsigned int hotplug_offset, ata_no;
818 u32 hotplug_status;
819 int is_sataii_tx4;
820
821 VPRINTK("ENTER\n");
822
823 if (!host || !host->iomap[PDC_MMIO_BAR]) {
824 VPRINTK("QUICK EXIT\n");
825 return IRQ_NONE;
826 }
827
828 host_mmio = host->iomap[PDC_MMIO_BAR];
829
830 spin_lock(&host->lock);
831
832 /* read and clear hotplug flags for all ports */
833 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
834 hotplug_offset = PDC2_SATA_PLUG_CSR;
835 else
836 hotplug_offset = PDC_SATA_PLUG_CSR;
837 hotplug_status = readl(host_mmio + hotplug_offset);
838 if (hotplug_status & 0xff)
839 writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
840 hotplug_status &= 0xff; /* clear uninteresting bits */
841
842 /* reading should also clear interrupts */
843 mask = readl(host_mmio + PDC_INT_SEQMASK);
844
845 if (mask == 0xffffffff && hotplug_status == 0) {
846 VPRINTK("QUICK EXIT 2\n");
847 goto done_irq;
848 }
849
850 mask &= 0xffff; /* only 16 SEQIDs possible */
851 if (mask == 0 && hotplug_status == 0) {
852 VPRINTK("QUICK EXIT 3\n");
853 goto done_irq;
854 }
855
856 writel(mask, host_mmio + PDC_INT_SEQMASK);
857
858 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
859
860 for (i = 0; i < host->n_ports; i++) {
861 VPRINTK("port %u\n", i);
862 ap = host->ports[i];
863
864 /* check for a plug or unplug event */
865 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
866 tmp = hotplug_status & (0x11 << ata_no);
867 if (tmp && ap &&
868 !(ap->flags & ATA_FLAG_DISABLED)) {
869 struct ata_eh_info *ehi = &ap->link.eh_info;
870 ata_ehi_clear_desc(ehi);
871 ata_ehi_hotplugged(ehi);
872 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
873 ata_port_freeze(ap);
874 ++handled;
875 continue;
876 }
877
878 /* check for a packet interrupt */
879 tmp = mask & (1 << (i + 1));
880 if (tmp && ap &&
881 !(ap->flags & ATA_FLAG_DISABLED)) {
882 struct ata_queued_cmd *qc;
883
884 qc = ata_qc_from_tag(ap, ap->link.active_tag);
885 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
886 handled += pdc_host_intr(ap, qc);
887 }
888 }
889
890 VPRINTK("EXIT\n");
891
892 done_irq:
893 spin_unlock(&host->lock);
894 return IRQ_RETVAL(handled);
895 }
896
pdc_packet_start(struct ata_queued_cmd * qc)897 static void pdc_packet_start(struct ata_queued_cmd *qc)
898 {
899 struct ata_port *ap = qc->ap;
900 struct pdc_port_priv *pp = ap->private_data;
901 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
902 void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
903 unsigned int port_no = ap->port_no;
904 u8 seq = (u8) (port_no + 1);
905
906 VPRINTK("ENTER, ap %p\n", ap);
907
908 writel(0x00000001, host_mmio + (seq * 4));
909 readl(host_mmio + (seq * 4)); /* flush */
910
911 pp->pkt[2] = seq;
912 wmb(); /* flush PRD, pkt writes */
913 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
914 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
915 }
916
pdc_qc_issue(struct ata_queued_cmd * qc)917 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
918 {
919 switch (qc->tf.protocol) {
920 case ATAPI_PROT_NODATA:
921 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
922 break;
923 /*FALLTHROUGH*/
924 case ATA_PROT_NODATA:
925 if (qc->tf.flags & ATA_TFLAG_POLLING)
926 break;
927 /*FALLTHROUGH*/
928 case ATAPI_PROT_DMA:
929 case ATA_PROT_DMA:
930 pdc_packet_start(qc);
931 return 0;
932 default:
933 break;
934 }
935 return ata_sff_qc_issue(qc);
936 }
937
pdc_tf_load_mmio(struct ata_port * ap,const struct ata_taskfile * tf)938 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
939 {
940 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
941 ata_sff_tf_load(ap, tf);
942 }
943
pdc_exec_command_mmio(struct ata_port * ap,const struct ata_taskfile * tf)944 static void pdc_exec_command_mmio(struct ata_port *ap,
945 const struct ata_taskfile *tf)
946 {
947 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
948 ata_sff_exec_command(ap, tf);
949 }
950
pdc_check_atapi_dma(struct ata_queued_cmd * qc)951 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
952 {
953 u8 *scsicmd = qc->scsicmd->cmnd;
954 int pio = 1; /* atapi dma off by default */
955
956 /* Whitelist commands that may use DMA. */
957 switch (scsicmd[0]) {
958 case WRITE_12:
959 case WRITE_10:
960 case WRITE_6:
961 case READ_12:
962 case READ_10:
963 case READ_6:
964 case 0xad: /* READ_DVD_STRUCTURE */
965 case 0xbe: /* READ_CD */
966 pio = 0;
967 }
968 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
969 if (scsicmd[0] == WRITE_10) {
970 unsigned int lba =
971 (scsicmd[2] << 24) |
972 (scsicmd[3] << 16) |
973 (scsicmd[4] << 8) |
974 scsicmd[5];
975 if (lba >= 0xFFFF4FA2)
976 pio = 1;
977 }
978 return pio;
979 }
980
pdc_old_sata_check_atapi_dma(struct ata_queued_cmd * qc)981 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
982 {
983 /* First generation chips cannot use ATAPI DMA on SATA ports */
984 return 1;
985 }
986
pdc_ata_setup_port(struct ata_port * ap,void __iomem * base,void __iomem * scr_addr)987 static void pdc_ata_setup_port(struct ata_port *ap,
988 void __iomem *base, void __iomem *scr_addr)
989 {
990 ap->ioaddr.cmd_addr = base;
991 ap->ioaddr.data_addr = base;
992 ap->ioaddr.feature_addr =
993 ap->ioaddr.error_addr = base + 0x4;
994 ap->ioaddr.nsect_addr = base + 0x8;
995 ap->ioaddr.lbal_addr = base + 0xc;
996 ap->ioaddr.lbam_addr = base + 0x10;
997 ap->ioaddr.lbah_addr = base + 0x14;
998 ap->ioaddr.device_addr = base + 0x18;
999 ap->ioaddr.command_addr =
1000 ap->ioaddr.status_addr = base + 0x1c;
1001 ap->ioaddr.altstatus_addr =
1002 ap->ioaddr.ctl_addr = base + 0x38;
1003 ap->ioaddr.scr_addr = scr_addr;
1004 }
1005
pdc_host_init(struct ata_host * host)1006 static void pdc_host_init(struct ata_host *host)
1007 {
1008 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1009 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1010 int hotplug_offset;
1011 u32 tmp;
1012
1013 if (is_gen2)
1014 hotplug_offset = PDC2_SATA_PLUG_CSR;
1015 else
1016 hotplug_offset = PDC_SATA_PLUG_CSR;
1017
1018 /*
1019 * Except for the hotplug stuff, this is voodoo from the
1020 * Promise driver. Label this entire section
1021 * "TODO: figure out why we do this"
1022 */
1023
1024 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1025 tmp = readl(host_mmio + PDC_FLASH_CTL);
1026 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1027 if (!is_gen2)
1028 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1029 writel(tmp, host_mmio + PDC_FLASH_CTL);
1030
1031 /* clear plug/unplug flags for all ports */
1032 tmp = readl(host_mmio + hotplug_offset);
1033 writel(tmp | 0xff, host_mmio + hotplug_offset);
1034
1035 /* unmask plug/unplug ints */
1036 tmp = readl(host_mmio + hotplug_offset);
1037 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1038
1039 /* don't initialise TBG or SLEW on 2nd generation chips */
1040 if (is_gen2)
1041 return;
1042
1043 /* reduce TBG clock to 133 Mhz. */
1044 tmp = readl(host_mmio + PDC_TBG_MODE);
1045 tmp &= ~0x30000; /* clear bit 17, 16*/
1046 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1047 writel(tmp, host_mmio + PDC_TBG_MODE);
1048
1049 readl(host_mmio + PDC_TBG_MODE); /* flush */
1050 msleep(10);
1051
1052 /* adjust slew rate control register. */
1053 tmp = readl(host_mmio + PDC_SLEW_CTL);
1054 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1055 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1056 writel(tmp, host_mmio + PDC_SLEW_CTL);
1057 }
1058
pdc_ata_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1059 static int pdc_ata_init_one(struct pci_dev *pdev,
1060 const struct pci_device_id *ent)
1061 {
1062 static int printed_version;
1063 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1064 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1065 struct ata_host *host;
1066 void __iomem *host_mmio;
1067 int n_ports, i, rc;
1068 int is_sataii_tx4;
1069
1070 if (!printed_version++)
1071 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1072
1073 /* enable and acquire resources */
1074 rc = pcim_enable_device(pdev);
1075 if (rc)
1076 return rc;
1077
1078 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1079 if (rc == -EBUSY)
1080 pcim_pin_device(pdev);
1081 if (rc)
1082 return rc;
1083 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1084
1085 /* determine port configuration and setup host */
1086 n_ports = 2;
1087 if (pi->flags & PDC_FLAG_4_PORTS)
1088 n_ports = 4;
1089 for (i = 0; i < n_ports; i++)
1090 ppi[i] = pi;
1091
1092 if (pi->flags & PDC_FLAG_SATA_PATA) {
1093 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1094 if (!(tmp & 0x80))
1095 ppi[n_ports++] = pi + 1;
1096 }
1097
1098 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1099 if (!host) {
1100 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1101 return -ENOMEM;
1102 }
1103 host->iomap = pcim_iomap_table(pdev);
1104
1105 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1106 for (i = 0; i < host->n_ports; i++) {
1107 struct ata_port *ap = host->ports[i];
1108 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1109 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1110 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1111
1112 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1113
1114 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1115 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1116 }
1117
1118 /* initialize adapter */
1119 pdc_host_init(host);
1120
1121 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1122 if (rc)
1123 return rc;
1124 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1125 if (rc)
1126 return rc;
1127
1128 /* start host, request IRQ and attach */
1129 pci_set_master(pdev);
1130 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1131 &pdc_ata_sht);
1132 }
1133
pdc_ata_init(void)1134 static int __init pdc_ata_init(void)
1135 {
1136 return pci_register_driver(&pdc_ata_pci_driver);
1137 }
1138
pdc_ata_exit(void)1139 static void __exit pdc_ata_exit(void)
1140 {
1141 pci_unregister_driver(&pdc_ata_pci_driver);
1142 }
1143
1144 MODULE_AUTHOR("Jeff Garzik");
1145 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1146 MODULE_LICENSE("GPL");
1147 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1148 MODULE_VERSION(DRV_VERSION);
1149
1150 module_init(pdc_ata_init);
1151 module_exit(pdc_ata_exit);
1152