1 /*
2 * Xilinx SystemACE device driver
3 *
4 * Copyright 2007 Secret Lab Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 /*
12 * The SystemACE chip is designed to configure FPGAs by loading an FPGA
13 * bitstream from a file on a CF card and squirting it into FPGAs connected
14 * to the SystemACE JTAG chain. It also has the advantage of providing an
15 * MPU interface which can be used to control the FPGA configuration process
16 * and to use the attached CF card for general purpose storage.
17 *
18 * This driver is a block device driver for the SystemACE.
19 *
20 * Initialization:
21 * The driver registers itself as a platform_device driver at module
22 * load time. The platform bus will take care of calling the
23 * ace_probe() method for all SystemACE instances in the system. Any
24 * number of SystemACE instances are supported. ace_probe() calls
25 * ace_setup() which initialized all data structures, reads the CF
26 * id structure and registers the device.
27 *
28 * Processing:
29 * Just about all of the heavy lifting in this driver is performed by
30 * a Finite State Machine (FSM). The driver needs to wait on a number
31 * of events; some raised by interrupts, some which need to be polled
32 * for. Describing all of the behaviour in a FSM seems to be the
33 * easiest way to keep the complexity low and make it easy to
34 * understand what the driver is doing. If the block ops or the
35 * request function need to interact with the hardware, then they
36 * simply need to flag the request and kick of FSM processing.
37 *
38 * The FSM itself is atomic-safe code which can be run from any
39 * context. The general process flow is:
40 * 1. obtain the ace->lock spinlock.
41 * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is
42 * cleared.
43 * 3. release the lock.
44 *
45 * Individual states do not sleep in any way. If a condition needs to
46 * be waited for then the state much clear the fsm_continue flag and
47 * either schedule the FSM to be run again at a later time, or expect
48 * an interrupt to call the FSM when the desired condition is met.
49 *
50 * In normal operation, the FSM is processed at interrupt context
51 * either when the driver's tasklet is scheduled, or when an irq is
52 * raised by the hardware. The tasklet can be scheduled at any time.
53 * The request method in particular schedules the tasklet when a new
54 * request has been indicated by the block layer. Once started, the
55 * FSM proceeds as far as it can processing the request until it
56 * needs on a hardware event. At this point, it must yield execution.
57 *
58 * A state has two options when yielding execution:
59 * 1. ace_fsm_yield()
60 * - Call if need to poll for event.
61 * - clears the fsm_continue flag to exit the processing loop
62 * - reschedules the tasklet to run again as soon as possible
63 * 2. ace_fsm_yieldirq()
64 * - Call if an irq is expected from the HW
65 * - clears the fsm_continue flag to exit the processing loop
66 * - does not reschedule the tasklet so the FSM will not be processed
67 * again until an irq is received.
68 * After calling a yield function, the state must return control back
69 * to the FSM main loop.
70 *
71 * Additionally, the driver maintains a kernel timer which can process
72 * the FSM. If the FSM gets stalled, typically due to a missed
73 * interrupt, then the kernel timer will expire and the driver can
74 * continue where it left off.
75 *
76 * To Do:
77 * - Add FPGA configuration control interface.
78 * - Request major number from lanana
79 */
80
81 #undef DEBUG
82
83 #include <linux/module.h>
84 #include <linux/ctype.h>
85 #include <linux/init.h>
86 #include <linux/interrupt.h>
87 #include <linux/errno.h>
88 #include <linux/kernel.h>
89 #include <linux/delay.h>
90 #include <linux/slab.h>
91 #include <linux/blkdev.h>
92 #include <linux/hdreg.h>
93 #include <linux/platform_device.h>
94 #if defined(CONFIG_OF)
95 #include <linux/of_device.h>
96 #include <linux/of_platform.h>
97 #endif
98
99 MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
100 MODULE_DESCRIPTION("Xilinx SystemACE device driver");
101 MODULE_LICENSE("GPL");
102
103 /* SystemACE register definitions */
104 #define ACE_BUSMODE (0x00)
105
106 #define ACE_STATUS (0x04)
107 #define ACE_STATUS_CFGLOCK (0x00000001)
108 #define ACE_STATUS_MPULOCK (0x00000002)
109 #define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */
110 #define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */
111 #define ACE_STATUS_CFDETECT (0x00000010)
112 #define ACE_STATUS_DATABUFRDY (0x00000020)
113 #define ACE_STATUS_DATABUFMODE (0x00000040)
114 #define ACE_STATUS_CFGDONE (0x00000080)
115 #define ACE_STATUS_RDYFORCFCMD (0x00000100)
116 #define ACE_STATUS_CFGMODEPIN (0x00000200)
117 #define ACE_STATUS_CFGADDR_MASK (0x0000e000)
118 #define ACE_STATUS_CFBSY (0x00020000)
119 #define ACE_STATUS_CFRDY (0x00040000)
120 #define ACE_STATUS_CFDWF (0x00080000)
121 #define ACE_STATUS_CFDSC (0x00100000)
122 #define ACE_STATUS_CFDRQ (0x00200000)
123 #define ACE_STATUS_CFCORR (0x00400000)
124 #define ACE_STATUS_CFERR (0x00800000)
125
126 #define ACE_ERROR (0x08)
127 #define ACE_CFGLBA (0x0c)
128 #define ACE_MPULBA (0x10)
129
130 #define ACE_SECCNTCMD (0x14)
131 #define ACE_SECCNTCMD_RESET (0x0100)
132 #define ACE_SECCNTCMD_IDENTIFY (0x0200)
133 #define ACE_SECCNTCMD_READ_DATA (0x0300)
134 #define ACE_SECCNTCMD_WRITE_DATA (0x0400)
135 #define ACE_SECCNTCMD_ABORT (0x0600)
136
137 #define ACE_VERSION (0x16)
138 #define ACE_VERSION_REVISION_MASK (0x00FF)
139 #define ACE_VERSION_MINOR_MASK (0x0F00)
140 #define ACE_VERSION_MAJOR_MASK (0xF000)
141
142 #define ACE_CTRL (0x18)
143 #define ACE_CTRL_FORCELOCKREQ (0x0001)
144 #define ACE_CTRL_LOCKREQ (0x0002)
145 #define ACE_CTRL_FORCECFGADDR (0x0004)
146 #define ACE_CTRL_FORCECFGMODE (0x0008)
147 #define ACE_CTRL_CFGMODE (0x0010)
148 #define ACE_CTRL_CFGSTART (0x0020)
149 #define ACE_CTRL_CFGSEL (0x0040)
150 #define ACE_CTRL_CFGRESET (0x0080)
151 #define ACE_CTRL_DATABUFRDYIRQ (0x0100)
152 #define ACE_CTRL_ERRORIRQ (0x0200)
153 #define ACE_CTRL_CFGDONEIRQ (0x0400)
154 #define ACE_CTRL_RESETIRQ (0x0800)
155 #define ACE_CTRL_CFGPROG (0x1000)
156 #define ACE_CTRL_CFGADDR_MASK (0xe000)
157
158 #define ACE_FATSTAT (0x1c)
159
160 #define ACE_NUM_MINORS 16
161 #define ACE_SECTOR_SIZE (512)
162 #define ACE_FIFO_SIZE (32)
163 #define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE)
164
165 #define ACE_BUS_WIDTH_8 0
166 #define ACE_BUS_WIDTH_16 1
167
168 struct ace_reg_ops;
169
170 struct ace_device {
171 /* driver state data */
172 int id;
173 int media_change;
174 int users;
175 struct list_head list;
176
177 /* finite state machine data */
178 struct tasklet_struct fsm_tasklet;
179 uint fsm_task; /* Current activity (ACE_TASK_*) */
180 uint fsm_state; /* Current state (ACE_FSM_STATE_*) */
181 uint fsm_continue_flag; /* cleared to exit FSM mainloop */
182 uint fsm_iter_num;
183 struct timer_list stall_timer;
184
185 /* Transfer state/result, use for both id and block request */
186 struct request *req; /* request being processed */
187 void *data_ptr; /* pointer to I/O buffer */
188 int data_count; /* number of buffers remaining */
189 int data_result; /* Result of transfer; 0 := success */
190
191 int id_req_count; /* count of id requests */
192 int id_result;
193 struct completion id_completion; /* used when id req finishes */
194 int in_irq;
195
196 /* Details of hardware device */
197 resource_size_t physaddr;
198 void __iomem *baseaddr;
199 int irq;
200 int bus_width; /* 0 := 8 bit; 1 := 16 bit */
201 struct ace_reg_ops *reg_ops;
202 int lock_count;
203
204 /* Block device data structures */
205 spinlock_t lock;
206 struct device *dev;
207 struct request_queue *queue;
208 struct gendisk *gd;
209
210 /* Inserted CF card parameters */
211 struct hd_driveid cf_id;
212 };
213
214 static int ace_major;
215
216 /* ---------------------------------------------------------------------
217 * Low level register access
218 */
219
220 struct ace_reg_ops {
221 u16(*in) (struct ace_device * ace, int reg);
222 void (*out) (struct ace_device * ace, int reg, u16 val);
223 void (*datain) (struct ace_device * ace);
224 void (*dataout) (struct ace_device * ace);
225 };
226
227 /* 8 Bit bus width */
ace_in_8(struct ace_device * ace,int reg)228 static u16 ace_in_8(struct ace_device *ace, int reg)
229 {
230 void __iomem *r = ace->baseaddr + reg;
231 return in_8(r) | (in_8(r + 1) << 8);
232 }
233
ace_out_8(struct ace_device * ace,int reg,u16 val)234 static void ace_out_8(struct ace_device *ace, int reg, u16 val)
235 {
236 void __iomem *r = ace->baseaddr + reg;
237 out_8(r, val);
238 out_8(r + 1, val >> 8);
239 }
240
ace_datain_8(struct ace_device * ace)241 static void ace_datain_8(struct ace_device *ace)
242 {
243 void __iomem *r = ace->baseaddr + 0x40;
244 u8 *dst = ace->data_ptr;
245 int i = ACE_FIFO_SIZE;
246 while (i--)
247 *dst++ = in_8(r++);
248 ace->data_ptr = dst;
249 }
250
ace_dataout_8(struct ace_device * ace)251 static void ace_dataout_8(struct ace_device *ace)
252 {
253 void __iomem *r = ace->baseaddr + 0x40;
254 u8 *src = ace->data_ptr;
255 int i = ACE_FIFO_SIZE;
256 while (i--)
257 out_8(r++, *src++);
258 ace->data_ptr = src;
259 }
260
261 static struct ace_reg_ops ace_reg_8_ops = {
262 .in = ace_in_8,
263 .out = ace_out_8,
264 .datain = ace_datain_8,
265 .dataout = ace_dataout_8,
266 };
267
268 /* 16 bit big endian bus attachment */
ace_in_be16(struct ace_device * ace,int reg)269 static u16 ace_in_be16(struct ace_device *ace, int reg)
270 {
271 return in_be16(ace->baseaddr + reg);
272 }
273
ace_out_be16(struct ace_device * ace,int reg,u16 val)274 static void ace_out_be16(struct ace_device *ace, int reg, u16 val)
275 {
276 out_be16(ace->baseaddr + reg, val);
277 }
278
ace_datain_be16(struct ace_device * ace)279 static void ace_datain_be16(struct ace_device *ace)
280 {
281 int i = ACE_FIFO_SIZE / 2;
282 u16 *dst = ace->data_ptr;
283 while (i--)
284 *dst++ = in_le16(ace->baseaddr + 0x40);
285 ace->data_ptr = dst;
286 }
287
ace_dataout_be16(struct ace_device * ace)288 static void ace_dataout_be16(struct ace_device *ace)
289 {
290 int i = ACE_FIFO_SIZE / 2;
291 u16 *src = ace->data_ptr;
292 while (i--)
293 out_le16(ace->baseaddr + 0x40, *src++);
294 ace->data_ptr = src;
295 }
296
297 /* 16 bit little endian bus attachment */
ace_in_le16(struct ace_device * ace,int reg)298 static u16 ace_in_le16(struct ace_device *ace, int reg)
299 {
300 return in_le16(ace->baseaddr + reg);
301 }
302
ace_out_le16(struct ace_device * ace,int reg,u16 val)303 static void ace_out_le16(struct ace_device *ace, int reg, u16 val)
304 {
305 out_le16(ace->baseaddr + reg, val);
306 }
307
ace_datain_le16(struct ace_device * ace)308 static void ace_datain_le16(struct ace_device *ace)
309 {
310 int i = ACE_FIFO_SIZE / 2;
311 u16 *dst = ace->data_ptr;
312 while (i--)
313 *dst++ = in_be16(ace->baseaddr + 0x40);
314 ace->data_ptr = dst;
315 }
316
ace_dataout_le16(struct ace_device * ace)317 static void ace_dataout_le16(struct ace_device *ace)
318 {
319 int i = ACE_FIFO_SIZE / 2;
320 u16 *src = ace->data_ptr;
321 while (i--)
322 out_be16(ace->baseaddr + 0x40, *src++);
323 ace->data_ptr = src;
324 }
325
326 static struct ace_reg_ops ace_reg_be16_ops = {
327 .in = ace_in_be16,
328 .out = ace_out_be16,
329 .datain = ace_datain_be16,
330 .dataout = ace_dataout_be16,
331 };
332
333 static struct ace_reg_ops ace_reg_le16_ops = {
334 .in = ace_in_le16,
335 .out = ace_out_le16,
336 .datain = ace_datain_le16,
337 .dataout = ace_dataout_le16,
338 };
339
ace_in(struct ace_device * ace,int reg)340 static inline u16 ace_in(struct ace_device *ace, int reg)
341 {
342 return ace->reg_ops->in(ace, reg);
343 }
344
ace_in32(struct ace_device * ace,int reg)345 static inline u32 ace_in32(struct ace_device *ace, int reg)
346 {
347 return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16);
348 }
349
ace_out(struct ace_device * ace,int reg,u16 val)350 static inline void ace_out(struct ace_device *ace, int reg, u16 val)
351 {
352 ace->reg_ops->out(ace, reg, val);
353 }
354
ace_out32(struct ace_device * ace,int reg,u32 val)355 static inline void ace_out32(struct ace_device *ace, int reg, u32 val)
356 {
357 ace_out(ace, reg, val);
358 ace_out(ace, reg + 2, val >> 16);
359 }
360
361 /* ---------------------------------------------------------------------
362 * Debug support functions
363 */
364
365 #if defined(DEBUG)
ace_dump_mem(void * base,int len)366 static void ace_dump_mem(void *base, int len)
367 {
368 const char *ptr = base;
369 int i, j;
370
371 for (i = 0; i < len; i += 16) {
372 printk(KERN_INFO "%.8x:", i);
373 for (j = 0; j < 16; j++) {
374 if (!(j % 4))
375 printk(" ");
376 printk("%.2x", ptr[i + j]);
377 }
378 printk(" ");
379 for (j = 0; j < 16; j++)
380 printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.');
381 printk("\n");
382 }
383 }
384 #else
ace_dump_mem(void * base,int len)385 static inline void ace_dump_mem(void *base, int len)
386 {
387 }
388 #endif
389
ace_dump_regs(struct ace_device * ace)390 static void ace_dump_regs(struct ace_device *ace)
391 {
392 dev_info(ace->dev, " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n"
393 KERN_INFO " status:%.8x mpu_lba:%.8x busmode:%4x\n"
394 KERN_INFO " error: %.8x cfg_lba:%.8x fatstat:%.4x\n",
395 ace_in32(ace, ACE_CTRL),
396 ace_in(ace, ACE_SECCNTCMD),
397 ace_in(ace, ACE_VERSION),
398 ace_in32(ace, ACE_STATUS),
399 ace_in32(ace, ACE_MPULBA),
400 ace_in(ace, ACE_BUSMODE),
401 ace_in32(ace, ACE_ERROR),
402 ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT));
403 }
404
ace_fix_driveid(struct hd_driveid * id)405 void ace_fix_driveid(struct hd_driveid *id)
406 {
407 #if defined(__BIG_ENDIAN)
408 u16 *buf = (void *)id;
409 int i;
410
411 /* All half words have wrong byte order; swap the bytes */
412 for (i = 0; i < sizeof(struct hd_driveid); i += 2, buf++)
413 *buf = le16_to_cpu(*buf);
414
415 /* Some of the data values are 32bit; swap the half words */
416 id->lba_capacity = ((id->lba_capacity >> 16) & 0x0000FFFF) |
417 ((id->lba_capacity << 16) & 0xFFFF0000);
418 id->spg = ((id->spg >> 16) & 0x0000FFFF) |
419 ((id->spg << 16) & 0xFFFF0000);
420 #endif
421 }
422
423 /* ---------------------------------------------------------------------
424 * Finite State Machine (FSM) implementation
425 */
426
427 /* FSM tasks; used to direct state transitions */
428 #define ACE_TASK_IDLE 0
429 #define ACE_TASK_IDENTIFY 1
430 #define ACE_TASK_READ 2
431 #define ACE_TASK_WRITE 3
432 #define ACE_FSM_NUM_TASKS 4
433
434 /* FSM state definitions */
435 #define ACE_FSM_STATE_IDLE 0
436 #define ACE_FSM_STATE_REQ_LOCK 1
437 #define ACE_FSM_STATE_WAIT_LOCK 2
438 #define ACE_FSM_STATE_WAIT_CFREADY 3
439 #define ACE_FSM_STATE_IDENTIFY_PREPARE 4
440 #define ACE_FSM_STATE_IDENTIFY_TRANSFER 5
441 #define ACE_FSM_STATE_IDENTIFY_COMPLETE 6
442 #define ACE_FSM_STATE_REQ_PREPARE 7
443 #define ACE_FSM_STATE_REQ_TRANSFER 8
444 #define ACE_FSM_STATE_REQ_COMPLETE 9
445 #define ACE_FSM_STATE_ERROR 10
446 #define ACE_FSM_NUM_STATES 11
447
448 /* Set flag to exit FSM loop and reschedule tasklet */
ace_fsm_yield(struct ace_device * ace)449 static inline void ace_fsm_yield(struct ace_device *ace)
450 {
451 dev_dbg(ace->dev, "ace_fsm_yield()\n");
452 tasklet_schedule(&ace->fsm_tasklet);
453 ace->fsm_continue_flag = 0;
454 }
455
456 /* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */
ace_fsm_yieldirq(struct ace_device * ace)457 static inline void ace_fsm_yieldirq(struct ace_device *ace)
458 {
459 dev_dbg(ace->dev, "ace_fsm_yieldirq()\n");
460
461 if (ace->irq == NO_IRQ)
462 /* No IRQ assigned, so need to poll */
463 tasklet_schedule(&ace->fsm_tasklet);
464 ace->fsm_continue_flag = 0;
465 }
466
467 /* Get the next read/write request; ending requests that we don't handle */
ace_get_next_request(struct request_queue * q)468 struct request *ace_get_next_request(struct request_queue * q)
469 {
470 struct request *req;
471
472 while ((req = elv_next_request(q)) != NULL) {
473 if (blk_fs_request(req))
474 break;
475 end_request(req, 0);
476 }
477 return req;
478 }
479
ace_fsm_dostate(struct ace_device * ace)480 static void ace_fsm_dostate(struct ace_device *ace)
481 {
482 struct request *req;
483 u32 status;
484 u16 val;
485 int count;
486
487 #if defined(DEBUG)
488 dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n",
489 ace->fsm_state, ace->id_req_count);
490 #endif
491
492 /* Verify that there is actually a CF in the slot. If not, then
493 * bail out back to the idle state and wake up all the waiters */
494 status = ace_in32(ace, ACE_STATUS);
495 if ((status & ACE_STATUS_CFDETECT) == 0) {
496 ace->fsm_state = ACE_FSM_STATE_IDLE;
497 ace->media_change = 1;
498 set_capacity(ace->gd, 0);
499 dev_info(ace->dev, "No CF in slot\n");
500
501 /* Drop all pending requests */
502 while ((req = elv_next_request(ace->queue)) != NULL)
503 end_request(req, 0);
504
505 /* Drop back to IDLE state and notify waiters */
506 ace->fsm_state = ACE_FSM_STATE_IDLE;
507 ace->id_result = -EIO;
508 while (ace->id_req_count) {
509 complete(&ace->id_completion);
510 ace->id_req_count--;
511 }
512 }
513
514 switch (ace->fsm_state) {
515 case ACE_FSM_STATE_IDLE:
516 /* See if there is anything to do */
517 if (ace->id_req_count || ace_get_next_request(ace->queue)) {
518 ace->fsm_iter_num++;
519 ace->fsm_state = ACE_FSM_STATE_REQ_LOCK;
520 mod_timer(&ace->stall_timer, jiffies + HZ);
521 if (!timer_pending(&ace->stall_timer))
522 add_timer(&ace->stall_timer);
523 break;
524 }
525 del_timer(&ace->stall_timer);
526 ace->fsm_continue_flag = 0;
527 break;
528
529 case ACE_FSM_STATE_REQ_LOCK:
530 if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) {
531 /* Already have the lock, jump to next state */
532 ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY;
533 break;
534 }
535
536 /* Request the lock */
537 val = ace_in(ace, ACE_CTRL);
538 ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ);
539 ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK;
540 break;
541
542 case ACE_FSM_STATE_WAIT_LOCK:
543 if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) {
544 /* got the lock; move to next state */
545 ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY;
546 break;
547 }
548
549 /* wait a bit for the lock */
550 ace_fsm_yield(ace);
551 break;
552
553 case ACE_FSM_STATE_WAIT_CFREADY:
554 status = ace_in32(ace, ACE_STATUS);
555 if (!(status & ACE_STATUS_RDYFORCFCMD) ||
556 (status & ACE_STATUS_CFBSY)) {
557 /* CF card isn't ready; it needs to be polled */
558 ace_fsm_yield(ace);
559 break;
560 }
561
562 /* Device is ready for command; determine what to do next */
563 if (ace->id_req_count)
564 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE;
565 else
566 ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE;
567 break;
568
569 case ACE_FSM_STATE_IDENTIFY_PREPARE:
570 /* Send identify command */
571 ace->fsm_task = ACE_TASK_IDENTIFY;
572 ace->data_ptr = &ace->cf_id;
573 ace->data_count = ACE_BUF_PER_SECTOR;
574 ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY);
575
576 /* As per datasheet, put config controller in reset */
577 val = ace_in(ace, ACE_CTRL);
578 ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET);
579
580 /* irq handler takes over from this point; wait for the
581 * transfer to complete */
582 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER;
583 ace_fsm_yieldirq(ace);
584 break;
585
586 case ACE_FSM_STATE_IDENTIFY_TRANSFER:
587 /* Check that the sysace is ready to receive data */
588 status = ace_in32(ace, ACE_STATUS);
589 if (status & ACE_STATUS_CFBSY) {
590 dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n",
591 ace->fsm_task, ace->fsm_iter_num,
592 ace->data_count);
593 ace_fsm_yield(ace);
594 break;
595 }
596 if (!(status & ACE_STATUS_DATABUFRDY)) {
597 ace_fsm_yield(ace);
598 break;
599 }
600
601 /* Transfer the next buffer */
602 ace->reg_ops->datain(ace);
603 ace->data_count--;
604
605 /* If there are still buffers to be transfers; jump out here */
606 if (ace->data_count != 0) {
607 ace_fsm_yieldirq(ace);
608 break;
609 }
610
611 /* transfer finished; kick state machine */
612 dev_dbg(ace->dev, "identify finished\n");
613 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE;
614 break;
615
616 case ACE_FSM_STATE_IDENTIFY_COMPLETE:
617 ace_fix_driveid(&ace->cf_id);
618 ace_dump_mem(&ace->cf_id, 512); /* Debug: Dump out disk ID */
619
620 if (ace->data_result) {
621 /* Error occured, disable the disk */
622 ace->media_change = 1;
623 set_capacity(ace->gd, 0);
624 dev_err(ace->dev, "error fetching CF id (%i)\n",
625 ace->data_result);
626 } else {
627 ace->media_change = 0;
628
629 /* Record disk parameters */
630 set_capacity(ace->gd, ace->cf_id.lba_capacity);
631 dev_info(ace->dev, "capacity: %i sectors\n",
632 ace->cf_id.lba_capacity);
633 }
634
635 /* We're done, drop to IDLE state and notify waiters */
636 ace->fsm_state = ACE_FSM_STATE_IDLE;
637 ace->id_result = ace->data_result;
638 while (ace->id_req_count) {
639 complete(&ace->id_completion);
640 ace->id_req_count--;
641 }
642 break;
643
644 case ACE_FSM_STATE_REQ_PREPARE:
645 req = ace_get_next_request(ace->queue);
646 if (!req) {
647 ace->fsm_state = ACE_FSM_STATE_IDLE;
648 break;
649 }
650
651 /* Okay, it's a data request, set it up for transfer */
652 dev_dbg(ace->dev,
653 "request: sec=%llx hcnt=%lx, ccnt=%x, dir=%i\n",
654 (unsigned long long) req->sector, req->hard_nr_sectors,
655 req->current_nr_sectors, rq_data_dir(req));
656
657 ace->req = req;
658 ace->data_ptr = req->buffer;
659 ace->data_count = req->current_nr_sectors * ACE_BUF_PER_SECTOR;
660 ace_out32(ace, ACE_MPULBA, req->sector & 0x0FFFFFFF);
661
662 count = req->hard_nr_sectors;
663 if (rq_data_dir(req)) {
664 /* Kick off write request */
665 dev_dbg(ace->dev, "write data\n");
666 ace->fsm_task = ACE_TASK_WRITE;
667 ace_out(ace, ACE_SECCNTCMD,
668 count | ACE_SECCNTCMD_WRITE_DATA);
669 } else {
670 /* Kick off read request */
671 dev_dbg(ace->dev, "read data\n");
672 ace->fsm_task = ACE_TASK_READ;
673 ace_out(ace, ACE_SECCNTCMD,
674 count | ACE_SECCNTCMD_READ_DATA);
675 }
676
677 /* As per datasheet, put config controller in reset */
678 val = ace_in(ace, ACE_CTRL);
679 ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET);
680
681 /* Move to the transfer state. The systemace will raise
682 * an interrupt once there is something to do
683 */
684 ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER;
685 if (ace->fsm_task == ACE_TASK_READ)
686 ace_fsm_yieldirq(ace); /* wait for data ready */
687 break;
688
689 case ACE_FSM_STATE_REQ_TRANSFER:
690 /* Check that the sysace is ready to receive data */
691 status = ace_in32(ace, ACE_STATUS);
692 if (status & ACE_STATUS_CFBSY) {
693 dev_dbg(ace->dev,
694 "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n",
695 ace->fsm_task, ace->fsm_iter_num,
696 ace->req->current_nr_sectors * 16,
697 ace->data_count, ace->in_irq);
698 ace_fsm_yield(ace); /* need to poll CFBSY bit */
699 break;
700 }
701 if (!(status & ACE_STATUS_DATABUFRDY)) {
702 dev_dbg(ace->dev,
703 "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n",
704 ace->fsm_task, ace->fsm_iter_num,
705 ace->req->current_nr_sectors * 16,
706 ace->data_count, ace->in_irq);
707 ace_fsm_yieldirq(ace);
708 break;
709 }
710
711 /* Transfer the next buffer */
712 if (ace->fsm_task == ACE_TASK_WRITE)
713 ace->reg_ops->dataout(ace);
714 else
715 ace->reg_ops->datain(ace);
716 ace->data_count--;
717
718 /* If there are still buffers to be transfers; jump out here */
719 if (ace->data_count != 0) {
720 ace_fsm_yieldirq(ace);
721 break;
722 }
723
724 /* bio finished; is there another one? */
725 if (__blk_end_request(ace->req, 0,
726 blk_rq_cur_bytes(ace->req))) {
727 /* dev_dbg(ace->dev, "next block; h=%li c=%i\n",
728 * ace->req->hard_nr_sectors,
729 * ace->req->current_nr_sectors);
730 */
731 ace->data_ptr = ace->req->buffer;
732 ace->data_count = ace->req->current_nr_sectors * 16;
733 ace_fsm_yieldirq(ace);
734 break;
735 }
736
737 ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE;
738 break;
739
740 case ACE_FSM_STATE_REQ_COMPLETE:
741 ace->req = NULL;
742
743 /* Finished request; go to idle state */
744 ace->fsm_state = ACE_FSM_STATE_IDLE;
745 break;
746
747 default:
748 ace->fsm_state = ACE_FSM_STATE_IDLE;
749 break;
750 }
751 }
752
ace_fsm_tasklet(unsigned long data)753 static void ace_fsm_tasklet(unsigned long data)
754 {
755 struct ace_device *ace = (void *)data;
756 unsigned long flags;
757
758 spin_lock_irqsave(&ace->lock, flags);
759
760 /* Loop over state machine until told to stop */
761 ace->fsm_continue_flag = 1;
762 while (ace->fsm_continue_flag)
763 ace_fsm_dostate(ace);
764
765 spin_unlock_irqrestore(&ace->lock, flags);
766 }
767
ace_stall_timer(unsigned long data)768 static void ace_stall_timer(unsigned long data)
769 {
770 struct ace_device *ace = (void *)data;
771 unsigned long flags;
772
773 dev_warn(ace->dev,
774 "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n",
775 ace->fsm_state, ace->fsm_task, ace->fsm_iter_num,
776 ace->data_count);
777 spin_lock_irqsave(&ace->lock, flags);
778
779 /* Rearm the stall timer *before* entering FSM (which may then
780 * delete the timer) */
781 mod_timer(&ace->stall_timer, jiffies + HZ);
782
783 /* Loop over state machine until told to stop */
784 ace->fsm_continue_flag = 1;
785 while (ace->fsm_continue_flag)
786 ace_fsm_dostate(ace);
787
788 spin_unlock_irqrestore(&ace->lock, flags);
789 }
790
791 /* ---------------------------------------------------------------------
792 * Interrupt handling routines
793 */
ace_interrupt_checkstate(struct ace_device * ace)794 static int ace_interrupt_checkstate(struct ace_device *ace)
795 {
796 u32 sreg = ace_in32(ace, ACE_STATUS);
797 u16 creg = ace_in(ace, ACE_CTRL);
798
799 /* Check for error occurance */
800 if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) &&
801 (creg & ACE_CTRL_ERRORIRQ)) {
802 dev_err(ace->dev, "transfer failure\n");
803 ace_dump_regs(ace);
804 return -EIO;
805 }
806
807 return 0;
808 }
809
ace_interrupt(int irq,void * dev_id)810 static irqreturn_t ace_interrupt(int irq, void *dev_id)
811 {
812 u16 creg;
813 struct ace_device *ace = dev_id;
814
815 /* be safe and get the lock */
816 spin_lock(&ace->lock);
817 ace->in_irq = 1;
818
819 /* clear the interrupt */
820 creg = ace_in(ace, ACE_CTRL);
821 ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ);
822 ace_out(ace, ACE_CTRL, creg);
823
824 /* check for IO failures */
825 if (ace_interrupt_checkstate(ace))
826 ace->data_result = -EIO;
827
828 if (ace->fsm_task == 0) {
829 dev_err(ace->dev,
830 "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n",
831 ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL),
832 ace_in(ace, ACE_SECCNTCMD));
833 dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n",
834 ace->fsm_task, ace->fsm_state, ace->data_count);
835 }
836
837 /* Loop over state machine until told to stop */
838 ace->fsm_continue_flag = 1;
839 while (ace->fsm_continue_flag)
840 ace_fsm_dostate(ace);
841
842 /* done with interrupt; drop the lock */
843 ace->in_irq = 0;
844 spin_unlock(&ace->lock);
845
846 return IRQ_HANDLED;
847 }
848
849 /* ---------------------------------------------------------------------
850 * Block ops
851 */
ace_request(struct request_queue * q)852 static void ace_request(struct request_queue * q)
853 {
854 struct request *req;
855 struct ace_device *ace;
856
857 req = ace_get_next_request(q);
858
859 if (req) {
860 ace = req->rq_disk->private_data;
861 tasklet_schedule(&ace->fsm_tasklet);
862 }
863 }
864
ace_media_changed(struct gendisk * gd)865 static int ace_media_changed(struct gendisk *gd)
866 {
867 struct ace_device *ace = gd->private_data;
868 dev_dbg(ace->dev, "ace_media_changed(): %i\n", ace->media_change);
869
870 return ace->media_change;
871 }
872
ace_revalidate_disk(struct gendisk * gd)873 static int ace_revalidate_disk(struct gendisk *gd)
874 {
875 struct ace_device *ace = gd->private_data;
876 unsigned long flags;
877
878 dev_dbg(ace->dev, "ace_revalidate_disk()\n");
879
880 if (ace->media_change) {
881 dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n");
882
883 spin_lock_irqsave(&ace->lock, flags);
884 ace->id_req_count++;
885 spin_unlock_irqrestore(&ace->lock, flags);
886
887 tasklet_schedule(&ace->fsm_tasklet);
888 wait_for_completion(&ace->id_completion);
889 }
890
891 dev_dbg(ace->dev, "revalidate complete\n");
892 return ace->id_result;
893 }
894
ace_open(struct block_device * bdev,fmode_t mode)895 static int ace_open(struct block_device *bdev, fmode_t mode)
896 {
897 struct ace_device *ace = bdev->bd_disk->private_data;
898 unsigned long flags;
899
900 dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1);
901
902 spin_lock_irqsave(&ace->lock, flags);
903 ace->users++;
904 spin_unlock_irqrestore(&ace->lock, flags);
905
906 check_disk_change(bdev);
907 return 0;
908 }
909
ace_release(struct gendisk * disk,fmode_t mode)910 static int ace_release(struct gendisk *disk, fmode_t mode)
911 {
912 struct ace_device *ace = disk->private_data;
913 unsigned long flags;
914 u16 val;
915
916 dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1);
917
918 spin_lock_irqsave(&ace->lock, flags);
919 ace->users--;
920 if (ace->users == 0) {
921 val = ace_in(ace, ACE_CTRL);
922 ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ);
923 }
924 spin_unlock_irqrestore(&ace->lock, flags);
925 return 0;
926 }
927
ace_getgeo(struct block_device * bdev,struct hd_geometry * geo)928 static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo)
929 {
930 struct ace_device *ace = bdev->bd_disk->private_data;
931
932 dev_dbg(ace->dev, "ace_getgeo()\n");
933
934 geo->heads = ace->cf_id.heads;
935 geo->sectors = ace->cf_id.sectors;
936 geo->cylinders = ace->cf_id.cyls;
937
938 return 0;
939 }
940
941 static struct block_device_operations ace_fops = {
942 .owner = THIS_MODULE,
943 .open = ace_open,
944 .release = ace_release,
945 .media_changed = ace_media_changed,
946 .revalidate_disk = ace_revalidate_disk,
947 .getgeo = ace_getgeo,
948 };
949
950 /* --------------------------------------------------------------------
951 * SystemACE device setup/teardown code
952 */
ace_setup(struct ace_device * ace)953 static int __devinit ace_setup(struct ace_device *ace)
954 {
955 u16 version;
956 u16 val;
957 int rc;
958
959 dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace);
960 dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n",
961 (unsigned long long)ace->physaddr, ace->irq);
962
963 spin_lock_init(&ace->lock);
964 init_completion(&ace->id_completion);
965
966 /*
967 * Map the device
968 */
969 ace->baseaddr = ioremap(ace->physaddr, 0x80);
970 if (!ace->baseaddr)
971 goto err_ioremap;
972
973 /*
974 * Initialize the state machine tasklet and stall timer
975 */
976 tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace);
977 setup_timer(&ace->stall_timer, ace_stall_timer, (unsigned long)ace);
978
979 /*
980 * Initialize the request queue
981 */
982 ace->queue = blk_init_queue(ace_request, &ace->lock);
983 if (ace->queue == NULL)
984 goto err_blk_initq;
985 blk_queue_hardsect_size(ace->queue, 512);
986
987 /*
988 * Allocate and initialize GD structure
989 */
990 ace->gd = alloc_disk(ACE_NUM_MINORS);
991 if (!ace->gd)
992 goto err_alloc_disk;
993
994 ace->gd->major = ace_major;
995 ace->gd->first_minor = ace->id * ACE_NUM_MINORS;
996 ace->gd->fops = &ace_fops;
997 ace->gd->queue = ace->queue;
998 ace->gd->private_data = ace;
999 snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a');
1000
1001 /* set bus width */
1002 if (ace->bus_width == ACE_BUS_WIDTH_16) {
1003 /* 0x0101 should work regardless of endianess */
1004 ace_out_le16(ace, ACE_BUSMODE, 0x0101);
1005
1006 /* read it back to determine endianess */
1007 if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001)
1008 ace->reg_ops = &ace_reg_le16_ops;
1009 else
1010 ace->reg_ops = &ace_reg_be16_ops;
1011 } else {
1012 ace_out_8(ace, ACE_BUSMODE, 0x00);
1013 ace->reg_ops = &ace_reg_8_ops;
1014 }
1015
1016 /* Make sure version register is sane */
1017 version = ace_in(ace, ACE_VERSION);
1018 if ((version == 0) || (version == 0xFFFF))
1019 goto err_read;
1020
1021 /* Put sysace in a sane state by clearing most control reg bits */
1022 ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE |
1023 ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ);
1024
1025 /* Now we can hook up the irq handler */
1026 if (ace->irq != NO_IRQ) {
1027 rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace);
1028 if (rc) {
1029 /* Failure - fall back to polled mode */
1030 dev_err(ace->dev, "request_irq failed\n");
1031 ace->irq = NO_IRQ;
1032 }
1033 }
1034
1035 /* Enable interrupts */
1036 val = ace_in(ace, ACE_CTRL);
1037 val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ;
1038 ace_out(ace, ACE_CTRL, val);
1039
1040 /* Print the identification */
1041 dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n",
1042 (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff);
1043 dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n",
1044 (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq);
1045
1046 ace->media_change = 1;
1047 ace_revalidate_disk(ace->gd);
1048
1049 /* Make the sysace device 'live' */
1050 add_disk(ace->gd);
1051
1052 return 0;
1053
1054 err_read:
1055 put_disk(ace->gd);
1056 err_alloc_disk:
1057 blk_cleanup_queue(ace->queue);
1058 err_blk_initq:
1059 iounmap(ace->baseaddr);
1060 err_ioremap:
1061 dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n",
1062 (unsigned long long) ace->physaddr);
1063 return -ENOMEM;
1064 }
1065
ace_teardown(struct ace_device * ace)1066 static void __devexit ace_teardown(struct ace_device *ace)
1067 {
1068 if (ace->gd) {
1069 del_gendisk(ace->gd);
1070 put_disk(ace->gd);
1071 }
1072
1073 if (ace->queue)
1074 blk_cleanup_queue(ace->queue);
1075
1076 tasklet_kill(&ace->fsm_tasklet);
1077
1078 if (ace->irq != NO_IRQ)
1079 free_irq(ace->irq, ace);
1080
1081 iounmap(ace->baseaddr);
1082 }
1083
1084 static int __devinit
ace_alloc(struct device * dev,int id,resource_size_t physaddr,int irq,int bus_width)1085 ace_alloc(struct device *dev, int id, resource_size_t physaddr,
1086 int irq, int bus_width)
1087 {
1088 struct ace_device *ace;
1089 int rc;
1090 dev_dbg(dev, "ace_alloc(%p)\n", dev);
1091
1092 if (!physaddr) {
1093 rc = -ENODEV;
1094 goto err_noreg;
1095 }
1096
1097 /* Allocate and initialize the ace device structure */
1098 ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL);
1099 if (!ace) {
1100 rc = -ENOMEM;
1101 goto err_alloc;
1102 }
1103
1104 ace->dev = dev;
1105 ace->id = id;
1106 ace->physaddr = physaddr;
1107 ace->irq = irq;
1108 ace->bus_width = bus_width;
1109
1110 /* Call the setup code */
1111 rc = ace_setup(ace);
1112 if (rc)
1113 goto err_setup;
1114
1115 dev_set_drvdata(dev, ace);
1116 return 0;
1117
1118 err_setup:
1119 dev_set_drvdata(dev, NULL);
1120 kfree(ace);
1121 err_alloc:
1122 err_noreg:
1123 dev_err(dev, "could not initialize device, err=%i\n", rc);
1124 return rc;
1125 }
1126
ace_free(struct device * dev)1127 static void __devexit ace_free(struct device *dev)
1128 {
1129 struct ace_device *ace = dev_get_drvdata(dev);
1130 dev_dbg(dev, "ace_free(%p)\n", dev);
1131
1132 if (ace) {
1133 ace_teardown(ace);
1134 dev_set_drvdata(dev, NULL);
1135 kfree(ace);
1136 }
1137 }
1138
1139 /* ---------------------------------------------------------------------
1140 * Platform Bus Support
1141 */
1142
ace_probe(struct platform_device * dev)1143 static int __devinit ace_probe(struct platform_device *dev)
1144 {
1145 resource_size_t physaddr = 0;
1146 int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */
1147 int id = dev->id;
1148 int irq = NO_IRQ;
1149 int i;
1150
1151 dev_dbg(&dev->dev, "ace_probe(%p)\n", dev);
1152
1153 for (i = 0; i < dev->num_resources; i++) {
1154 if (dev->resource[i].flags & IORESOURCE_MEM)
1155 physaddr = dev->resource[i].start;
1156 if (dev->resource[i].flags & IORESOURCE_IRQ)
1157 irq = dev->resource[i].start;
1158 }
1159
1160 /* Call the bus-independant setup code */
1161 return ace_alloc(&dev->dev, id, physaddr, irq, bus_width);
1162 }
1163
1164 /*
1165 * Platform bus remove() method
1166 */
ace_remove(struct platform_device * dev)1167 static int __devexit ace_remove(struct platform_device *dev)
1168 {
1169 ace_free(&dev->dev);
1170 return 0;
1171 }
1172
1173 static struct platform_driver ace_platform_driver = {
1174 .probe = ace_probe,
1175 .remove = __devexit_p(ace_remove),
1176 .driver = {
1177 .owner = THIS_MODULE,
1178 .name = "xsysace",
1179 },
1180 };
1181
1182 /* ---------------------------------------------------------------------
1183 * OF_Platform Bus Support
1184 */
1185
1186 #if defined(CONFIG_OF)
1187 static int __devinit
ace_of_probe(struct of_device * op,const struct of_device_id * match)1188 ace_of_probe(struct of_device *op, const struct of_device_id *match)
1189 {
1190 struct resource res;
1191 resource_size_t physaddr;
1192 const u32 *id;
1193 int irq, bus_width, rc;
1194
1195 dev_dbg(&op->dev, "ace_of_probe(%p, %p)\n", op, match);
1196
1197 /* device id */
1198 id = of_get_property(op->node, "port-number", NULL);
1199
1200 /* physaddr */
1201 rc = of_address_to_resource(op->node, 0, &res);
1202 if (rc) {
1203 dev_err(&op->dev, "invalid address\n");
1204 return rc;
1205 }
1206 physaddr = res.start;
1207
1208 /* irq */
1209 irq = irq_of_parse_and_map(op->node, 0);
1210
1211 /* bus width */
1212 bus_width = ACE_BUS_WIDTH_16;
1213 if (of_find_property(op->node, "8-bit", NULL))
1214 bus_width = ACE_BUS_WIDTH_8;
1215
1216 /* Call the bus-independant setup code */
1217 return ace_alloc(&op->dev, id ? *id : 0, physaddr, irq, bus_width);
1218 }
1219
ace_of_remove(struct of_device * op)1220 static int __devexit ace_of_remove(struct of_device *op)
1221 {
1222 ace_free(&op->dev);
1223 return 0;
1224 }
1225
1226 /* Match table for of_platform binding */
1227 static struct of_device_id ace_of_match[] __devinitdata = {
1228 { .compatible = "xlnx,opb-sysace-1.00.b", },
1229 { .compatible = "xlnx,opb-sysace-1.00.c", },
1230 { .compatible = "xlnx,xps-sysace-1.00.a", },
1231 { .compatible = "xlnx,sysace", },
1232 {},
1233 };
1234 MODULE_DEVICE_TABLE(of, ace_of_match);
1235
1236 static struct of_platform_driver ace_of_driver = {
1237 .owner = THIS_MODULE,
1238 .name = "xsysace",
1239 .match_table = ace_of_match,
1240 .probe = ace_of_probe,
1241 .remove = __devexit_p(ace_of_remove),
1242 .driver = {
1243 .name = "xsysace",
1244 },
1245 };
1246
1247 /* Registration helpers to keep the number of #ifdefs to a minimum */
ace_of_register(void)1248 static inline int __init ace_of_register(void)
1249 {
1250 pr_debug("xsysace: registering OF binding\n");
1251 return of_register_platform_driver(&ace_of_driver);
1252 }
1253
ace_of_unregister(void)1254 static inline void __exit ace_of_unregister(void)
1255 {
1256 of_unregister_platform_driver(&ace_of_driver);
1257 }
1258 #else /* CONFIG_OF */
1259 /* CONFIG_OF not enabled; do nothing helpers */
ace_of_register(void)1260 static inline int __init ace_of_register(void) { return 0; }
ace_of_unregister(void)1261 static inline void __exit ace_of_unregister(void) { }
1262 #endif /* CONFIG_OF */
1263
1264 /* ---------------------------------------------------------------------
1265 * Module init/exit routines
1266 */
ace_init(void)1267 static int __init ace_init(void)
1268 {
1269 int rc;
1270
1271 ace_major = register_blkdev(ace_major, "xsysace");
1272 if (ace_major <= 0) {
1273 rc = -ENOMEM;
1274 goto err_blk;
1275 }
1276
1277 rc = ace_of_register();
1278 if (rc)
1279 goto err_of;
1280
1281 pr_debug("xsysace: registering platform binding\n");
1282 rc = platform_driver_register(&ace_platform_driver);
1283 if (rc)
1284 goto err_plat;
1285
1286 pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major);
1287 return 0;
1288
1289 err_plat:
1290 ace_of_unregister();
1291 err_of:
1292 unregister_blkdev(ace_major, "xsysace");
1293 err_blk:
1294 printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc);
1295 return rc;
1296 }
1297
ace_exit(void)1298 static void __exit ace_exit(void)
1299 {
1300 pr_debug("Unregistering Xilinx SystemACE driver\n");
1301 platform_driver_unregister(&ace_platform_driver);
1302 ace_of_unregister();
1303 unregister_blkdev(ace_major, "xsysace");
1304 }
1305
1306 module_init(ace_init);
1307 module_exit(ace_exit);
1308