1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32
33 /** @file i915_gem_tiling.c
34 *
35 * Support for managing tiling state of buffer objects.
36 *
37 * The idea behind tiling is to increase cache hit rates by rearranging
38 * pixel data so that a group of pixel accesses are in the same cacheline.
39 * Performance improvement from doing this on the back/depth buffer are on
40 * the order of 30%.
41 *
42 * Intel architectures make this somewhat more complicated, though, by
43 * adjustments made to addressing of data when the memory is in interleaved
44 * mode (matched pairs of DIMMS) to improve memory bandwidth.
45 * For interleaved memory, the CPU sends every sequential 64 bytes
46 * to an alternate memory channel so it can get the bandwidth from both.
47 *
48 * The GPU also rearranges its accesses for increased bandwidth to interleaved
49 * memory, and it matches what the CPU does for non-tiled. However, when tiled
50 * it does it a little differently, since one walks addresses not just in the
51 * X direction but also Y. So, along with alternating channels when bit
52 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
53 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
54 * are common to both the 915 and 965-class hardware.
55 *
56 * The CPU also sometimes XORs in higher bits as well, to improve
57 * bandwidth doing strided access like we do so frequently in graphics. This
58 * is called "Channel XOR Randomization" in the MCH documentation. The result
59 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
60 * decode.
61 *
62 * All of this bit 6 XORing has an effect on our memory management,
63 * as we need to make sure that the 3d driver can correctly address object
64 * contents.
65 *
66 * If we don't have interleaved memory, all tiling is safe and no swizzling is
67 * required.
68 *
69 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
70 * 17 is not just a page offset, so as we page an objet out and back in,
71 * individual pages in it will have different bit 17 addresses, resulting in
72 * each 64 bytes being swapped with its neighbor!
73 *
74 * Otherwise, if interleaved, we have to tell the 3d driver what the address
75 * swizzling it needs to do is, since it's writing with the CPU to the pages
76 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
77 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
78 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
79 * to match what the GPU expects.
80 */
81
82 /**
83 * Detects bit 6 swizzling of address lookup between IGD access and CPU
84 * access through main memory.
85 */
86 void
i915_gem_detect_bit_6_swizzle(struct drm_device * dev)87 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
88 {
89 drm_i915_private_t *dev_priv = dev->dev_private;
90 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
91 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
92
93 if (!IS_I9XX(dev)) {
94 /* As far as we know, the 865 doesn't have these bit 6
95 * swizzling issues.
96 */
97 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
98 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
99 } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev) ||
100 IS_GM45(dev)) {
101 uint32_t dcc;
102
103 /* On 915-945 and GM965, channel interleave by the CPU is
104 * determined by DCC. The CPU will alternate based on bit 6
105 * in interleaved mode, and the GPU will then also alternate
106 * on bit 6, 9, and 10 for X, but the CPU may also optionally
107 * alternate based on bit 17 (XOR not disabled and XOR
108 * bit == 17).
109 */
110 dcc = I915_READ(DCC);
111 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
112 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
113 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
114 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
115 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
116 break;
117 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
118 if (IS_I915G(dev) || IS_I915GM(dev) ||
119 dcc & DCC_CHANNEL_XOR_DISABLE) {
120 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
121 swizzle_y = I915_BIT_6_SWIZZLE_9;
122 } else if ((IS_I965GM(dev) || IS_GM45(dev)) &&
123 (dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
124 /* GM965/GM45 does either bit 11 or bit 17
125 * swizzling.
126 */
127 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
128 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
129 } else {
130 /* Bit 17 or perhaps other swizzling */
131 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
132 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
133 }
134 break;
135 }
136 if (dcc == 0xffffffff) {
137 DRM_ERROR("Couldn't read from MCHBAR. "
138 "Disabling tiling.\n");
139 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
140 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
141 }
142 } else {
143 /* The 965, G33, and newer, have a very flexible memory
144 * configuration. It will enable dual-channel mode
145 * (interleaving) on as much memory as it can, and the GPU
146 * will additionally sometimes enable different bit 6
147 * swizzling for tiled objects from the CPU.
148 *
149 * Here's what I found on the G965:
150 * slot fill memory size swizzling
151 * 0A 0B 1A 1B 1-ch 2-ch
152 * 512 0 0 0 512 0 O
153 * 512 0 512 0 16 1008 X
154 * 512 0 0 512 16 1008 X
155 * 0 512 0 512 16 1008 X
156 * 1024 1024 1024 0 2048 1024 O
157 *
158 * We could probably detect this based on either the DRB
159 * matching, which was the case for the swizzling required in
160 * the table above, or from the 1-ch value being less than
161 * the minimum size of a rank.
162 */
163 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
164 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
165 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
166 } else {
167 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
168 swizzle_y = I915_BIT_6_SWIZZLE_9;
169 }
170 }
171
172 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
173 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
174 }
175
176
177 /**
178 * Returns the size of the fence for a tiled object of the given size.
179 */
180 static int
i915_get_fence_size(struct drm_device * dev,int size)181 i915_get_fence_size(struct drm_device *dev, int size)
182 {
183 int i;
184 int start;
185
186 if (IS_I965G(dev)) {
187 /* The 965 can have fences at any page boundary. */
188 return ALIGN(size, 4096);
189 } else {
190 /* Align the size to a power of two greater than the smallest
191 * fence size.
192 */
193 if (IS_I9XX(dev))
194 start = 1024 * 1024;
195 else
196 start = 512 * 1024;
197
198 for (i = start; i < size; i <<= 1)
199 ;
200
201 return i;
202 }
203 }
204
205 /* Check pitch constriants for all chips & tiling formats */
206 static bool
i915_tiling_ok(struct drm_device * dev,int stride,int size,int tiling_mode)207 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
208 {
209 int tile_width;
210
211 /* Linear is always fine */
212 if (tiling_mode == I915_TILING_NONE)
213 return true;
214
215 if (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
216 tile_width = 128;
217 else
218 tile_width = 512;
219
220 /* 965+ just needs multiples of tile width */
221 if (IS_I965G(dev)) {
222 if (stride & (tile_width - 1))
223 return false;
224 return true;
225 }
226
227 /* Pre-965 needs power of two tile widths */
228 if (stride < tile_width)
229 return false;
230
231 if (stride & (stride - 1))
232 return false;
233
234 /* We don't handle the aperture area covered by the fence being bigger
235 * than the object size.
236 */
237 if (i915_get_fence_size(dev, size) != size)
238 return false;
239
240 return true;
241 }
242
243 /**
244 * Sets the tiling mode of an object, returning the required swizzling of
245 * bit 6 of addresses in the object.
246 */
247 int
i915_gem_set_tiling(struct drm_device * dev,void * data,struct drm_file * file_priv)248 i915_gem_set_tiling(struct drm_device *dev, void *data,
249 struct drm_file *file_priv)
250 {
251 struct drm_i915_gem_set_tiling *args = data;
252 drm_i915_private_t *dev_priv = dev->dev_private;
253 struct drm_gem_object *obj;
254 struct drm_i915_gem_object *obj_priv;
255
256 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
257 if (obj == NULL)
258 return -EINVAL;
259 obj_priv = obj->driver_private;
260
261 if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) {
262 drm_gem_object_unreference(obj);
263 return -EINVAL;
264 }
265
266 mutex_lock(&dev->struct_mutex);
267
268 if (args->tiling_mode == I915_TILING_NONE) {
269 obj_priv->tiling_mode = I915_TILING_NONE;
270 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
271 } else {
272 if (args->tiling_mode == I915_TILING_X)
273 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
274 else
275 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
276 /* If we can't handle the swizzling, make it untiled. */
277 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
278 args->tiling_mode = I915_TILING_NONE;
279 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
280 }
281 }
282 if (args->tiling_mode != obj_priv->tiling_mode) {
283 int ret;
284
285 /* Unbind the object, as switching tiling means we're
286 * switching the cache organization due to fencing, probably.
287 */
288 ret = i915_gem_object_unbind(obj);
289 if (ret != 0) {
290 WARN(ret != -ERESTARTSYS,
291 "failed to unbind object for tiling switch");
292 args->tiling_mode = obj_priv->tiling_mode;
293 mutex_unlock(&dev->struct_mutex);
294 drm_gem_object_unreference(obj);
295
296 return ret;
297 }
298 obj_priv->tiling_mode = args->tiling_mode;
299 }
300 obj_priv->stride = args->stride;
301
302 drm_gem_object_unreference(obj);
303 mutex_unlock(&dev->struct_mutex);
304
305 return 0;
306 }
307
308 /**
309 * Returns the current tiling mode and required bit 6 swizzling for the object.
310 */
311 int
i915_gem_get_tiling(struct drm_device * dev,void * data,struct drm_file * file_priv)312 i915_gem_get_tiling(struct drm_device *dev, void *data,
313 struct drm_file *file_priv)
314 {
315 struct drm_i915_gem_get_tiling *args = data;
316 drm_i915_private_t *dev_priv = dev->dev_private;
317 struct drm_gem_object *obj;
318 struct drm_i915_gem_object *obj_priv;
319
320 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
321 if (obj == NULL)
322 return -EINVAL;
323 obj_priv = obj->driver_private;
324
325 mutex_lock(&dev->struct_mutex);
326
327 args->tiling_mode = obj_priv->tiling_mode;
328 switch (obj_priv->tiling_mode) {
329 case I915_TILING_X:
330 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
331 break;
332 case I915_TILING_Y:
333 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
334 break;
335 case I915_TILING_NONE:
336 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
337 break;
338 default:
339 DRM_ERROR("unknown tiling mode\n");
340 }
341
342 drm_gem_object_unreference(obj);
343 mutex_unlock(&dev->struct_mutex);
344
345 return 0;
346 }
347