1 /* 2 * Copyright � 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 /** 28 * @file SDVO command definitions and structures. 29 */ 30 31 #define SDVO_OUTPUT_FIRST (0) 32 #define SDVO_OUTPUT_TMDS0 (1 << 0) 33 #define SDVO_OUTPUT_RGB0 (1 << 1) 34 #define SDVO_OUTPUT_CVBS0 (1 << 2) 35 #define SDVO_OUTPUT_SVID0 (1 << 3) 36 #define SDVO_OUTPUT_YPRPB0 (1 << 4) 37 #define SDVO_OUTPUT_SCART0 (1 << 5) 38 #define SDVO_OUTPUT_LVDS0 (1 << 6) 39 #define SDVO_OUTPUT_TMDS1 (1 << 8) 40 #define SDVO_OUTPUT_RGB1 (1 << 9) 41 #define SDVO_OUTPUT_CVBS1 (1 << 10) 42 #define SDVO_OUTPUT_SVID1 (1 << 11) 43 #define SDVO_OUTPUT_YPRPB1 (1 << 12) 44 #define SDVO_OUTPUT_SCART1 (1 << 13) 45 #define SDVO_OUTPUT_LVDS1 (1 << 14) 46 #define SDVO_OUTPUT_LAST (14) 47 48 struct intel_sdvo_caps { 49 u8 vendor_id; 50 u8 device_id; 51 u8 device_rev_id; 52 u8 sdvo_version_major; 53 u8 sdvo_version_minor; 54 unsigned int sdvo_inputs_mask:2; 55 unsigned int smooth_scaling:1; 56 unsigned int sharp_scaling:1; 57 unsigned int up_scaling:1; 58 unsigned int down_scaling:1; 59 unsigned int stall_support:1; 60 unsigned int pad:1; 61 u16 output_flags; 62 } __attribute__((packed)); 63 64 /** This matches the EDID DTD structure, more or less */ 65 struct intel_sdvo_dtd { 66 struct { 67 u16 clock; /**< pixel clock, in 10kHz units */ 68 u8 h_active; /**< lower 8 bits (pixels) */ 69 u8 h_blank; /**< lower 8 bits (pixels) */ 70 u8 h_high; /**< upper 4 bits each h_active, h_blank */ 71 u8 v_active; /**< lower 8 bits (lines) */ 72 u8 v_blank; /**< lower 8 bits (lines) */ 73 u8 v_high; /**< upper 4 bits each v_active, v_blank */ 74 } part1; 75 76 struct { 77 u8 h_sync_off; /**< lower 8 bits, from hblank start */ 78 u8 h_sync_width; /**< lower 8 bits (pixels) */ 79 /** lower 4 bits each vsync offset, vsync width */ 80 u8 v_sync_off_width; 81 /** 82 * 2 high bits of hsync offset, 2 high bits of hsync width, 83 * bits 4-5 of vsync offset, and 2 high bits of vsync width. 84 */ 85 u8 sync_off_width_high; 86 u8 dtd_flags; 87 u8 sdvo_flags; 88 /** bits 6-7 of vsync offset at bits 6-7 */ 89 u8 v_sync_off_high; 90 u8 reserved; 91 } part2; 92 } __attribute__((packed)); 93 94 struct intel_sdvo_pixel_clock_range { 95 u16 min; /**< pixel clock, in 10kHz units */ 96 u16 max; /**< pixel clock, in 10kHz units */ 97 } __attribute__((packed)); 98 99 struct intel_sdvo_preferred_input_timing_args { 100 u16 clock; 101 u16 width; 102 u16 height; 103 } __attribute__((packed)); 104 105 /* I2C registers for SDVO */ 106 #define SDVO_I2C_ARG_0 0x07 107 #define SDVO_I2C_ARG_1 0x06 108 #define SDVO_I2C_ARG_2 0x05 109 #define SDVO_I2C_ARG_3 0x04 110 #define SDVO_I2C_ARG_4 0x03 111 #define SDVO_I2C_ARG_5 0x02 112 #define SDVO_I2C_ARG_6 0x01 113 #define SDVO_I2C_ARG_7 0x00 114 #define SDVO_I2C_OPCODE 0x08 115 #define SDVO_I2C_CMD_STATUS 0x09 116 #define SDVO_I2C_RETURN_0 0x0a 117 #define SDVO_I2C_RETURN_1 0x0b 118 #define SDVO_I2C_RETURN_2 0x0c 119 #define SDVO_I2C_RETURN_3 0x0d 120 #define SDVO_I2C_RETURN_4 0x0e 121 #define SDVO_I2C_RETURN_5 0x0f 122 #define SDVO_I2C_RETURN_6 0x10 123 #define SDVO_I2C_RETURN_7 0x11 124 #define SDVO_I2C_VENDOR_BEGIN 0x20 125 126 /* Status results */ 127 #define SDVO_CMD_STATUS_POWER_ON 0x0 128 #define SDVO_CMD_STATUS_SUCCESS 0x1 129 #define SDVO_CMD_STATUS_NOTSUPP 0x2 130 #define SDVO_CMD_STATUS_INVALID_ARG 0x3 131 #define SDVO_CMD_STATUS_PENDING 0x4 132 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5 133 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6 134 135 /* SDVO commands, argument/result registers */ 136 137 #define SDVO_CMD_RESET 0x01 138 139 /** Returns a struct intel_sdvo_caps */ 140 #define SDVO_CMD_GET_DEVICE_CAPS 0x02 141 142 #define SDVO_CMD_GET_FIRMWARE_REV 0x86 143 # define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0 144 # define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1 145 # define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2 146 147 /** 148 * Reports which inputs are trained (managed to sync). 149 * 150 * Devices must have trained within 2 vsyncs of a mode change. 151 */ 152 #define SDVO_CMD_GET_TRAINED_INPUTS 0x03 153 struct intel_sdvo_get_trained_inputs_response { 154 unsigned int input0_trained:1; 155 unsigned int input1_trained:1; 156 unsigned int pad:6; 157 } __attribute__((packed)); 158 159 /** Returns a struct intel_sdvo_output_flags of active outputs. */ 160 #define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04 161 162 /** 163 * Sets the current set of active outputs. 164 * 165 * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP 166 * on multi-output devices. 167 */ 168 #define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05 169 170 /** 171 * Returns the current mapping of SDVO inputs to outputs on the device. 172 * 173 * Returns two struct intel_sdvo_output_flags structures. 174 */ 175 #define SDVO_CMD_GET_IN_OUT_MAP 0x06 176 struct intel_sdvo_in_out_map { 177 u16 in0, in1; 178 }; 179 180 /** 181 * Sets the current mapping of SDVO inputs to outputs on the device. 182 * 183 * Takes two struct i380_sdvo_output_flags structures. 184 */ 185 #define SDVO_CMD_SET_IN_OUT_MAP 0x07 186 187 /** 188 * Returns a struct intel_sdvo_output_flags of attached displays. 189 */ 190 #define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b 191 192 /** 193 * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging. 194 */ 195 #define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c 196 197 /** 198 * Takes a struct intel_sdvo_output_flags. 199 */ 200 #define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d 201 202 /** 203 * Returns a struct intel_sdvo_output_flags of displays with hot plug 204 * interrupts enabled. 205 */ 206 #define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e 207 208 #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f 209 struct intel_sdvo_get_interrupt_event_source_response { 210 u16 interrupt_status; 211 unsigned int ambient_light_interrupt:1; 212 unsigned int hdmi_audio_encrypt_change:1; 213 unsigned int pad:6; 214 } __attribute__((packed)); 215 216 /** 217 * Selects which input is affected by future input commands. 218 * 219 * Commands affected include SET_INPUT_TIMINGS_PART[12], 220 * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12], 221 * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS. 222 */ 223 #define SDVO_CMD_SET_TARGET_INPUT 0x10 224 struct intel_sdvo_set_target_input_args { 225 unsigned int target_1:1; 226 unsigned int pad:7; 227 } __attribute__((packed)); 228 229 /** 230 * Takes a struct intel_sdvo_output_flags of which outputs are targetted by 231 * future output commands. 232 * 233 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], 234 * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE. 235 */ 236 #define SDVO_CMD_SET_TARGET_OUTPUT 0x11 237 238 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12 239 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13 240 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14 241 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15 242 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16 243 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17 244 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18 245 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19 246 /* Part 1 */ 247 # define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0 248 # define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1 249 # define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2 250 # define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3 251 # define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4 252 # define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5 253 # define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6 254 # define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7 255 /* Part 2 */ 256 # define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0 257 # define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1 258 # define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2 259 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3 260 # define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4 261 # define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7) 262 # define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5) 263 # define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3) 264 # define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1) 265 # define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5 266 # define SDVO_DTD_SDVO_FLAG_STALL (1 << 7) 267 # define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6) 268 # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6) 269 # define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4) 270 # define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4) 271 # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4) 272 # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4) 273 # define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6 274 275 /** 276 * Generates a DTD based on the given width, height, and flags. 277 * 278 * This will be supported by any device supporting scaling or interlaced 279 * modes. 280 */ 281 #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a 282 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0 283 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1 284 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2 285 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3 286 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4 287 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5 288 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6 289 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0) 290 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1) 291 292 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b 293 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c 294 295 /** Returns a struct intel_sdvo_pixel_clock_range */ 296 #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d 297 /** Returns a struct intel_sdvo_pixel_clock_range */ 298 #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e 299 300 /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ 301 #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f 302 303 /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 304 #define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20 305 /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 306 #define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21 307 # define SDVO_CLOCK_RATE_MULT_1X (1 << 0) 308 # define SDVO_CLOCK_RATE_MULT_2X (1 << 1) 309 # define SDVO_CLOCK_RATE_MULT_4X (1 << 3) 310 311 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 312 /** 5 bytes of bit flags for TV formats shared by all TV format functions */ 313 struct intel_sdvo_tv_format { 314 unsigned int ntsc_m:1; 315 unsigned int ntsc_j:1; 316 unsigned int ntsc_443:1; 317 unsigned int pal_b:1; 318 unsigned int pal_d:1; 319 unsigned int pal_g:1; 320 unsigned int pal_h:1; 321 unsigned int pal_i:1; 322 323 unsigned int pal_m:1; 324 unsigned int pal_n:1; 325 unsigned int pal_nc:1; 326 unsigned int pal_60:1; 327 unsigned int secam_b:1; 328 unsigned int secam_d:1; 329 unsigned int secam_g:1; 330 unsigned int secam_k:1; 331 332 unsigned int secam_k1:1; 333 unsigned int secam_l:1; 334 unsigned int secam_60:1; 335 unsigned int hdtv_std_smpte_240m_1080i_59:1; 336 unsigned int hdtv_std_smpte_240m_1080i_60:1; 337 unsigned int hdtv_std_smpte_260m_1080i_59:1; 338 unsigned int hdtv_std_smpte_260m_1080i_60:1; 339 unsigned int hdtv_std_smpte_274m_1080i_50:1; 340 341 unsigned int hdtv_std_smpte_274m_1080i_59:1; 342 unsigned int hdtv_std_smpte_274m_1080i_60:1; 343 unsigned int hdtv_std_smpte_274m_1080p_23:1; 344 unsigned int hdtv_std_smpte_274m_1080p_24:1; 345 unsigned int hdtv_std_smpte_274m_1080p_25:1; 346 unsigned int hdtv_std_smpte_274m_1080p_29:1; 347 unsigned int hdtv_std_smpte_274m_1080p_30:1; 348 unsigned int hdtv_std_smpte_274m_1080p_50:1; 349 350 unsigned int hdtv_std_smpte_274m_1080p_59:1; 351 unsigned int hdtv_std_smpte_274m_1080p_60:1; 352 unsigned int hdtv_std_smpte_295m_1080i_50:1; 353 unsigned int hdtv_std_smpte_295m_1080p_50:1; 354 unsigned int hdtv_std_smpte_296m_720p_59:1; 355 unsigned int hdtv_std_smpte_296m_720p_60:1; 356 unsigned int hdtv_std_smpte_296m_720p_50:1; 357 unsigned int hdtv_std_smpte_293m_480p_59:1; 358 359 unsigned int hdtv_std_smpte_170m_480i_59:1; 360 unsigned int hdtv_std_iturbt601_576i_50:1; 361 unsigned int hdtv_std_iturbt601_576p_50:1; 362 unsigned int hdtv_std_eia_7702a_480i_60:1; 363 unsigned int hdtv_std_eia_7702a_480p_60:1; 364 unsigned int pad:3; 365 } __attribute__((packed)); 366 367 #define SDVO_CMD_GET_TV_FORMAT 0x28 368 369 #define SDVO_CMD_SET_TV_FORMAT 0x29 370 371 /** Returns the resolutiosn that can be used with the given TV format */ 372 #define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83 373 struct intel_sdvo_sdtv_resolution_request { 374 unsigned int ntsc_m:1; 375 unsigned int ntsc_j:1; 376 unsigned int ntsc_443:1; 377 unsigned int pal_b:1; 378 unsigned int pal_d:1; 379 unsigned int pal_g:1; 380 unsigned int pal_h:1; 381 unsigned int pal_i:1; 382 383 unsigned int pal_m:1; 384 unsigned int pal_n:1; 385 unsigned int pal_nc:1; 386 unsigned int pal_60:1; 387 unsigned int secam_b:1; 388 unsigned int secam_d:1; 389 unsigned int secam_g:1; 390 unsigned int secam_k:1; 391 392 unsigned int secam_k1:1; 393 unsigned int secam_l:1; 394 unsigned int secam_60:1; 395 unsigned int pad:5; 396 } __attribute__((packed)); 397 398 struct intel_sdvo_sdtv_resolution_reply { 399 unsigned int res_320x200:1; 400 unsigned int res_320x240:1; 401 unsigned int res_400x300:1; 402 unsigned int res_640x350:1; 403 unsigned int res_640x400:1; 404 unsigned int res_640x480:1; 405 unsigned int res_704x480:1; 406 unsigned int res_704x576:1; 407 408 unsigned int res_720x350:1; 409 unsigned int res_720x400:1; 410 unsigned int res_720x480:1; 411 unsigned int res_720x540:1; 412 unsigned int res_720x576:1; 413 unsigned int res_768x576:1; 414 unsigned int res_800x600:1; 415 unsigned int res_832x624:1; 416 417 unsigned int res_920x766:1; 418 unsigned int res_1024x768:1; 419 unsigned int res_1280x1024:1; 420 unsigned int pad:5; 421 } __attribute__((packed)); 422 423 /* Get supported resolution with squire pixel aspect ratio that can be 424 scaled for the requested HDTV format */ 425 #define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85 426 427 struct intel_sdvo_hdtv_resolution_request { 428 unsigned int hdtv_std_smpte_240m_1080i_59:1; 429 unsigned int hdtv_std_smpte_240m_1080i_60:1; 430 unsigned int hdtv_std_smpte_260m_1080i_59:1; 431 unsigned int hdtv_std_smpte_260m_1080i_60:1; 432 unsigned int hdtv_std_smpte_274m_1080i_50:1; 433 unsigned int hdtv_std_smpte_274m_1080i_59:1; 434 unsigned int hdtv_std_smpte_274m_1080i_60:1; 435 unsigned int hdtv_std_smpte_274m_1080p_23:1; 436 437 unsigned int hdtv_std_smpte_274m_1080p_24:1; 438 unsigned int hdtv_std_smpte_274m_1080p_25:1; 439 unsigned int hdtv_std_smpte_274m_1080p_29:1; 440 unsigned int hdtv_std_smpte_274m_1080p_30:1; 441 unsigned int hdtv_std_smpte_274m_1080p_50:1; 442 unsigned int hdtv_std_smpte_274m_1080p_59:1; 443 unsigned int hdtv_std_smpte_274m_1080p_60:1; 444 unsigned int hdtv_std_smpte_295m_1080i_50:1; 445 446 unsigned int hdtv_std_smpte_295m_1080p_50:1; 447 unsigned int hdtv_std_smpte_296m_720p_59:1; 448 unsigned int hdtv_std_smpte_296m_720p_60:1; 449 unsigned int hdtv_std_smpte_296m_720p_50:1; 450 unsigned int hdtv_std_smpte_293m_480p_59:1; 451 unsigned int hdtv_std_smpte_170m_480i_59:1; 452 unsigned int hdtv_std_iturbt601_576i_50:1; 453 unsigned int hdtv_std_iturbt601_576p_50:1; 454 455 unsigned int hdtv_std_eia_7702a_480i_60:1; 456 unsigned int hdtv_std_eia_7702a_480p_60:1; 457 unsigned int pad:6; 458 } __attribute__((packed)); 459 460 struct intel_sdvo_hdtv_resolution_reply { 461 unsigned int res_640x480:1; 462 unsigned int res_800x600:1; 463 unsigned int res_1024x768:1; 464 unsigned int res_1280x960:1; 465 unsigned int res_1400x1050:1; 466 unsigned int res_1600x1200:1; 467 unsigned int res_1920x1440:1; 468 unsigned int res_2048x1536:1; 469 470 unsigned int res_2560x1920:1; 471 unsigned int res_3200x2400:1; 472 unsigned int res_3840x2880:1; 473 unsigned int pad1:5; 474 475 unsigned int res_848x480:1; 476 unsigned int res_1064x600:1; 477 unsigned int res_1280x720:1; 478 unsigned int res_1360x768:1; 479 unsigned int res_1704x960:1; 480 unsigned int res_1864x1050:1; 481 unsigned int res_1920x1080:1; 482 unsigned int res_2128x1200:1; 483 484 unsigned int res_2560x1400:1; 485 unsigned int res_2728x1536:1; 486 unsigned int res_3408x1920:1; 487 unsigned int res_4264x2400:1; 488 unsigned int res_5120x2880:1; 489 unsigned int pad2:3; 490 491 unsigned int res_768x480:1; 492 unsigned int res_960x600:1; 493 unsigned int res_1152x720:1; 494 unsigned int res_1124x768:1; 495 unsigned int res_1536x960:1; 496 unsigned int res_1680x1050:1; 497 unsigned int res_1728x1080:1; 498 unsigned int res_1920x1200:1; 499 500 unsigned int res_2304x1440:1; 501 unsigned int res_2456x1536:1; 502 unsigned int res_3072x1920:1; 503 unsigned int res_3840x2400:1; 504 unsigned int res_4608x2880:1; 505 unsigned int pad3:3; 506 507 unsigned int res_1280x1024:1; 508 unsigned int pad4:7; 509 510 unsigned int res_1280x768:1; 511 unsigned int pad5:7; 512 } __attribute__((packed)); 513 514 /* Get supported power state returns info for encoder and monitor, rely on 515 last SetTargetInput and SetTargetOutput calls */ 516 #define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a 517 /* Get power state returns info for encoder and monitor, rely on last 518 SetTargetInput and SetTargetOutput calls */ 519 #define SDVO_CMD_GET_POWER_STATE 0x2b 520 #define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b 521 #define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c 522 # define SDVO_ENCODER_STATE_ON (1 << 0) 523 # define SDVO_ENCODER_STATE_STANDBY (1 << 1) 524 # define SDVO_ENCODER_STATE_SUSPEND (1 << 2) 525 # define SDVO_ENCODER_STATE_OFF (1 << 3) 526 # define SDVO_MONITOR_STATE_ON (1 << 4) 527 # define SDVO_MONITOR_STATE_STANDBY (1 << 5) 528 # define SDVO_MONITOR_STATE_SUSPEND (1 << 6) 529 # define SDVO_MONITOR_STATE_OFF (1 << 7) 530 531 #define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d 532 #define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e 533 #define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f 534 /** 535 * The panel power sequencing parameters are in units of milliseconds. 536 * The high fields are bits 8:9 of the 10-bit values. 537 */ 538 struct sdvo_panel_power_sequencing { 539 u8 t0; 540 u8 t1; 541 u8 t2; 542 u8 t3; 543 u8 t4; 544 545 unsigned int t0_high:2; 546 unsigned int t1_high:2; 547 unsigned int t2_high:2; 548 unsigned int t3_high:2; 549 550 unsigned int t4_high:2; 551 unsigned int pad:6; 552 } __attribute__((packed)); 553 554 #define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30 555 struct sdvo_max_backlight_reply { 556 u8 max_value; 557 u8 default_value; 558 } __attribute__((packed)); 559 560 #define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31 561 #define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32 562 563 #define SDVO_CMD_GET_AMBIENT_LIGHT 0x33 564 struct sdvo_get_ambient_light_reply { 565 u16 trip_low; 566 u16 trip_high; 567 u16 value; 568 } __attribute__((packed)); 569 #define SDVO_CMD_SET_AMBIENT_LIGHT 0x34 570 struct sdvo_set_ambient_light_reply { 571 u16 trip_low; 572 u16 trip_high; 573 unsigned int enable:1; 574 unsigned int pad:7; 575 } __attribute__((packed)); 576 577 /* Set display power state */ 578 #define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d 579 # define SDVO_DISPLAY_STATE_ON (1 << 0) 580 # define SDVO_DISPLAY_STATE_STANDBY (1 << 1) 581 # define SDVO_DISPLAY_STATE_SUSPEND (1 << 2) 582 # define SDVO_DISPLAY_STATE_OFF (1 << 3) 583 584 #define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84 585 struct intel_sdvo_enhancements_reply { 586 unsigned int flicker_filter:1; 587 unsigned int flicker_filter_adaptive:1; 588 unsigned int flicker_filter_2d:1; 589 unsigned int saturation:1; 590 unsigned int hue:1; 591 unsigned int brightness:1; 592 unsigned int contrast:1; 593 unsigned int overscan_h:1; 594 595 unsigned int overscan_v:1; 596 unsigned int position_h:1; 597 unsigned int position_v:1; 598 unsigned int sharpness:1; 599 unsigned int dot_crawl:1; 600 unsigned int dither:1; 601 unsigned int max_tv_chroma_filter:1; 602 unsigned int max_tv_luma_filter:1; 603 } __attribute__((packed)); 604 605 /* Picture enhancement limits below are dependent on the current TV format, 606 * and thus need to be queried and set after it. 607 */ 608 #define SDVO_CMD_GET_MAX_FLICKER_FITER 0x4d 609 #define SDVO_CMD_GET_MAX_ADAPTIVE_FLICKER_FITER 0x7b 610 #define SDVO_CMD_GET_MAX_2D_FLICKER_FITER 0x52 611 #define SDVO_CMD_GET_MAX_SATURATION 0x55 612 #define SDVO_CMD_GET_MAX_HUE 0x58 613 #define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b 614 #define SDVO_CMD_GET_MAX_CONTRAST 0x5e 615 #define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61 616 #define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64 617 #define SDVO_CMD_GET_MAX_POSITION_H 0x67 618 #define SDVO_CMD_GET_MAX_POSITION_V 0x6a 619 #define SDVO_CMD_GET_MAX_SHARPNESS_V 0x6d 620 #define SDVO_CMD_GET_MAX_TV_CHROMA 0x74 621 #define SDVO_CMD_GET_MAX_TV_LUMA 0x77 622 struct intel_sdvo_enhancement_limits_reply { 623 u16 max_value; 624 u16 default_value; 625 } __attribute__((packed)); 626 627 #define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f 628 #define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80 629 # define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0) 630 # define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0) 631 # define SDVO_LVDS_CONNECTOR_SPWG (0 << 2) 632 # define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2) 633 # define SDVO_LVDS_SINGLE_CHANNEL (0 << 4) 634 # define SDVO_LVDS_DUAL_CHANNEL (1 << 4) 635 636 #define SDVO_CMD_GET_FLICKER_FILTER 0x4e 637 #define SDVO_CMD_SET_FLICKER_FILTER 0x4f 638 #define SDVO_CMD_GET_ADAPTIVE_FLICKER_FITER 0x50 639 #define SDVO_CMD_SET_ADAPTIVE_FLICKER_FITER 0x51 640 #define SDVO_CMD_GET_2D_FLICKER_FITER 0x53 641 #define SDVO_CMD_SET_2D_FLICKER_FITER 0x54 642 #define SDVO_CMD_GET_SATURATION 0x56 643 #define SDVO_CMD_SET_SATURATION 0x57 644 #define SDVO_CMD_GET_HUE 0x59 645 #define SDVO_CMD_SET_HUE 0x5a 646 #define SDVO_CMD_GET_BRIGHTNESS 0x5c 647 #define SDVO_CMD_SET_BRIGHTNESS 0x5d 648 #define SDVO_CMD_GET_CONTRAST 0x5f 649 #define SDVO_CMD_SET_CONTRAST 0x60 650 #define SDVO_CMD_GET_OVERSCAN_H 0x62 651 #define SDVO_CMD_SET_OVERSCAN_H 0x63 652 #define SDVO_CMD_GET_OVERSCAN_V 0x65 653 #define SDVO_CMD_SET_OVERSCAN_V 0x66 654 #define SDVO_CMD_GET_POSITION_H 0x68 655 #define SDVO_CMD_SET_POSITION_H 0x69 656 #define SDVO_CMD_GET_POSITION_V 0x6b 657 #define SDVO_CMD_SET_POSITION_V 0x6c 658 #define SDVO_CMD_GET_SHARPNESS 0x6e 659 #define SDVO_CMD_SET_SHARPNESS 0x6f 660 #define SDVO_CMD_GET_TV_CHROMA 0x75 661 #define SDVO_CMD_SET_TV_CHROMA 0x76 662 #define SDVO_CMD_GET_TV_LUMA 0x78 663 #define SDVO_CMD_SET_TV_LUMA 0x79 664 struct intel_sdvo_enhancements_arg { 665 u16 value; 666 }__attribute__((packed)); 667 668 #define SDVO_CMD_GET_DOT_CRAWL 0x70 669 #define SDVO_CMD_SET_DOT_CRAWL 0x71 670 # define SDVO_DOT_CRAWL_ON (1 << 0) 671 # define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1) 672 673 #define SDVO_CMD_GET_DITHER 0x72 674 #define SDVO_CMD_SET_DITHER 0x73 675 # define SDVO_DITHER_ON (1 << 0) 676 # define SDVO_DITHER_DEFAULT_ON (1 << 1) 677 678 #define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a 679 # define SDVO_CONTROL_BUS_PROM (1 << 0) 680 # define SDVO_CONTROL_BUS_DDC1 (1 << 1) 681 # define SDVO_CONTROL_BUS_DDC2 (1 << 2) 682 # define SDVO_CONTROL_BUS_DDC3 (1 << 3) 683 684 /* HDMI op codes */ 685 #define SDVO_CMD_GET_SUPP_ENCODE 0x9d 686 #define SDVO_CMD_GET_ENCODE 0x9e 687 #define SDVO_CMD_SET_ENCODE 0x9f 688 #define SDVO_ENCODE_DVI 0x0 689 #define SDVO_ENCODE_HDMI 0x1 690 #define SDVO_CMD_SET_PIXEL_REPLI 0x8b 691 #define SDVO_CMD_GET_PIXEL_REPLI 0x8c 692 #define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d 693 #define SDVO_CMD_SET_COLORIMETRY 0x8e 694 #define SDVO_COLORIMETRY_RGB256 0x0 695 #define SDVO_COLORIMETRY_RGB220 0x1 696 #define SDVO_COLORIMETRY_YCrCb422 0x3 697 #define SDVO_COLORIMETRY_YCrCb444 0x4 698 #define SDVO_CMD_GET_COLORIMETRY 0x8f 699 #define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90 700 #define SDVO_CMD_SET_AUDIO_STAT 0x91 701 #define SDVO_CMD_GET_AUDIO_STAT 0x92 702 #define SDVO_CMD_SET_HBUF_INDEX 0x93 703 #define SDVO_CMD_GET_HBUF_INDEX 0x94 704 #define SDVO_CMD_GET_HBUF_INFO 0x95 705 #define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96 706 #define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97 707 #define SDVO_CMD_SET_HBUF_DATA 0x98 708 #define SDVO_CMD_GET_HBUF_DATA 0x99 709 #define SDVO_CMD_SET_HBUF_TXRATE 0x9a 710 #define SDVO_CMD_GET_HBUF_TXRATE 0x9b 711 #define SDVO_HBUF_TX_DISABLED (0 << 6) 712 #define SDVO_HBUF_TX_ONCE (2 << 6) 713 #define SDVO_HBUF_TX_VSYNC (3 << 6) 714 #define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c 715 716 struct intel_sdvo_encode{ 717 u8 dvi_rev; 718 u8 hdmi_rev; 719 } __attribute__ ((packed)); 720