1 /*
2 * Copyright (C) 1995-1996 Linus Torvalds & authors (see below)
3 */
4
5 /*
6 * Original authors: abramov@cecmow.enet.dec.com (Igor Abramov)
7 * mlord@pobox.com (Mark Lord)
8 *
9 * See linux/MAINTAINERS for address of current maintainer.
10 *
11 * This file provides support for the advanced features and bugs
12 * of IDE interfaces using the CMD Technologies 0640 IDE interface chip.
13 *
14 * These chips are basically fucked by design, and getting this driver
15 * to work on every motherboard design that uses this screwed chip seems
16 * bloody well impossible. However, we're still trying.
17 *
18 * Version 0.97 worked for everybody.
19 *
20 * User feedback is essential. Many thanks to the beta test team:
21 *
22 * A.Hartgers@stud.tue.nl, JZDQC@CUNYVM.CUNY.edu, abramov@cecmow.enet.dec.com,
23 * bardj@utopia.ppp.sn.no, bart@gaga.tue.nl, bbol001@cs.auckland.ac.nz,
24 * chrisc@dbass.demon.co.uk, dalecki@namu26.Num.Math.Uni-Goettingen.de,
25 * derekn@vw.ece.cmu.edu, florian@btp2x3.phy.uni-bayreuth.de,
26 * flynn@dei.unipd.it, gadio@netvision.net.il, godzilla@futuris.net,
27 * j@pobox.com, jkemp1@mises.uni-paderborn.de, jtoppe@hiwaay.net,
28 * kerouac@ssnet.com, meskes@informatik.rwth-aachen.de, hzoli@cs.elte.hu,
29 * peter@udgaard.isgtec.com, phil@tazenda.demon.co.uk, roadcapw@cfw.com,
30 * s0033las@sun10.vsz.bme.hu, schaffer@tam.cornell.edu, sjd@slip.net,
31 * steve@ei.org, ulrpeg@bigcomm.gun.de, ism@tardis.ed.ac.uk, mack@cray.com
32 * liug@mama.indstate.edu, and others.
33 *
34 * Version 0.01 Initial version, hacked out of ide.c,
35 * and #include'd rather than compiled separately.
36 * This will get cleaned up in a subsequent release.
37 *
38 * Version 0.02 Fixes for vlb initialization code, enable prefetch
39 * for versions 'B' and 'C' of chip by default,
40 * some code cleanup.
41 *
42 * Version 0.03 Added reset of secondary interface,
43 * and black list for devices which are not compatible
44 * with prefetch mode. Separate function for setting
45 * prefetch is added, possibly it will be called some
46 * day from ioctl processing code.
47 *
48 * Version 0.04 Now configs/compiles separate from ide.c
49 *
50 * Version 0.05 Major rewrite of interface timing code.
51 * Added new function cmd640_set_mode to set PIO mode
52 * from ioctl call. New drives added to black list.
53 *
54 * Version 0.06 More code cleanup. Prefetch is enabled only for
55 * detected hard drives, not included in prefetch
56 * black list.
57 *
58 * Version 0.07 Changed to more conservative drive tuning policy.
59 * Unknown drives, which report PIO < 4 are set to
60 * (reported_PIO - 1) if it is supported, or to PIO0.
61 * List of known drives extended by info provided by
62 * CMD at their ftp site.
63 *
64 * Version 0.08 Added autotune/noautotune support.
65 *
66 * Version 0.09 Try to be smarter about 2nd port enabling.
67 * Version 0.10 Be nice and don't reset 2nd port.
68 * Version 0.11 Try to handle more weird situations.
69 *
70 * Version 0.12 Lots of bug fixes from Laszlo Peter
71 * irq unmasking disabled for reliability.
72 * try to be even smarter about the second port.
73 * tidy up source code formatting.
74 * Version 0.13 permit irq unmasking again.
75 * Version 0.90 massive code cleanup, some bugs fixed.
76 * defaults all drives to PIO mode0, prefetch off.
77 * autotune is OFF by default, with compile time flag.
78 * prefetch can be turned OFF/ON using "hdparm -p8/-p9"
79 * (requires hdparm-3.1 or newer)
80 * Version 0.91 first release to linux-kernel list.
81 * Version 0.92 move initial reg dump to separate callable function
82 * change "readahead" to "prefetch" to avoid confusion
83 * Version 0.95 respect original BIOS timings unless autotuning.
84 * tons of code cleanup and rearrangement.
85 * added CONFIG_BLK_DEV_CMD640_ENHANCED option
86 * prevent use of unmask when prefetch is on
87 * Version 0.96 prevent use of io_32bit when prefetch is off
88 * Version 0.97 fix VLB secondary interface for sjd@slip.net
89 * other minor tune-ups: 0.96 was very good.
90 * Version 0.98 ignore PCI version when disabled by BIOS
91 * Version 0.99 display setup/active/recovery clocks with PIO mode
92 * Version 1.00 Mmm.. cannot depend on PCMD_ENA in all systems
93 * Version 1.01 slow/fast devsel can be selected with "hdparm -p6/-p7"
94 * ("fast" is necessary for 32bit I/O in some systems)
95 * Version 1.02 fix bug that resulted in slow "setup times"
96 * (patch courtesy of Zoltan Hidvegi)
97 */
98
99 #define CMD640_PREFETCH_MASKS 1
100
101 /*#define CMD640_DUMP_REGS */
102
103 #include <linux/types.h>
104 #include <linux/kernel.h>
105 #include <linux/delay.h>
106 #include <linux/ide.h>
107 #include <linux/init.h>
108
109 #include <asm/io.h>
110
111 #define DRV_NAME "cmd640"
112
113 static int cmd640_vlb;
114
115 /*
116 * CMD640 specific registers definition.
117 */
118
119 #define VID 0x00
120 #define DID 0x02
121 #define PCMD 0x04
122 #define PCMD_ENA 0x01
123 #define PSTTS 0x06
124 #define REVID 0x08
125 #define PROGIF 0x09
126 #define SUBCL 0x0a
127 #define BASCL 0x0b
128 #define BaseA0 0x10
129 #define BaseA1 0x14
130 #define BaseA2 0x18
131 #define BaseA3 0x1c
132 #define INTLINE 0x3c
133 #define INPINE 0x3d
134
135 #define CFR 0x50
136 #define CFR_DEVREV 0x03
137 #define CFR_IDE01INTR 0x04
138 #define CFR_DEVID 0x18
139 #define CFR_AT_VESA_078h 0x20
140 #define CFR_DSA1 0x40
141 #define CFR_DSA0 0x80
142
143 #define CNTRL 0x51
144 #define CNTRL_DIS_RA0 0x40
145 #define CNTRL_DIS_RA1 0x80
146 #define CNTRL_ENA_2ND 0x08
147
148 #define CMDTIM 0x52
149 #define ARTTIM0 0x53
150 #define DRWTIM0 0x54
151 #define ARTTIM1 0x55
152 #define DRWTIM1 0x56
153 #define ARTTIM23 0x57
154 #define ARTTIM23_DIS_RA2 0x04
155 #define ARTTIM23_DIS_RA3 0x08
156 #define DRWTIM23 0x58
157 #define BRST 0x59
158
159 /*
160 * Registers and masks for easy access by drive index:
161 */
162 static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
163 static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
164
165 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
166
167 static u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
168 static u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM23, DRWTIM23};
169
170 /*
171 * Current cmd640 timing values for each drive.
172 * The defaults for each are the slowest possible timings.
173 */
174 static u8 setup_counts[4] = {4, 4, 4, 4}; /* Address setup count (in clocks) */
175 static u8 active_counts[4] = {16, 16, 16, 16}; /* Active count (encoded) */
176 static u8 recovery_counts[4] = {16, 16, 16, 16}; /* Recovery count (encoded) */
177
178 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
179
180 static DEFINE_SPINLOCK(cmd640_lock);
181
182 /*
183 * Interface to access cmd640x registers
184 */
185 static unsigned int cmd640_key;
186 static void (*__put_cmd640_reg)(u16 reg, u8 val);
187 static u8 (*__get_cmd640_reg)(u16 reg);
188
189 /*
190 * This is read from the CFR reg, and is used in several places.
191 */
192 static unsigned int cmd640_chip_version;
193
194 /*
195 * The CMD640x chip does not support DWORD config write cycles, but some
196 * of the BIOSes use them to implement the config services.
197 * Therefore, we must use direct IO instead.
198 */
199
200 /* PCI method 1 access */
201
put_cmd640_reg_pci1(u16 reg,u8 val)202 static void put_cmd640_reg_pci1(u16 reg, u8 val)
203 {
204 outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
205 outb_p(val, (reg & 3) | 0xcfc);
206 }
207
get_cmd640_reg_pci1(u16 reg)208 static u8 get_cmd640_reg_pci1(u16 reg)
209 {
210 outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
211 return inb_p((reg & 3) | 0xcfc);
212 }
213
214 /* PCI method 2 access (from CMD datasheet) */
215
put_cmd640_reg_pci2(u16 reg,u8 val)216 static void put_cmd640_reg_pci2(u16 reg, u8 val)
217 {
218 outb_p(0x10, 0xcf8);
219 outb_p(val, cmd640_key + reg);
220 outb_p(0, 0xcf8);
221 }
222
get_cmd640_reg_pci2(u16 reg)223 static u8 get_cmd640_reg_pci2(u16 reg)
224 {
225 u8 b;
226
227 outb_p(0x10, 0xcf8);
228 b = inb_p(cmd640_key + reg);
229 outb_p(0, 0xcf8);
230 return b;
231 }
232
233 /* VLB access */
234
put_cmd640_reg_vlb(u16 reg,u8 val)235 static void put_cmd640_reg_vlb(u16 reg, u8 val)
236 {
237 outb_p(reg, cmd640_key);
238 outb_p(val, cmd640_key + 4);
239 }
240
get_cmd640_reg_vlb(u16 reg)241 static u8 get_cmd640_reg_vlb(u16 reg)
242 {
243 outb_p(reg, cmd640_key);
244 return inb_p(cmd640_key + 4);
245 }
246
get_cmd640_reg(u16 reg)247 static u8 get_cmd640_reg(u16 reg)
248 {
249 unsigned long flags;
250 u8 b;
251
252 spin_lock_irqsave(&cmd640_lock, flags);
253 b = __get_cmd640_reg(reg);
254 spin_unlock_irqrestore(&cmd640_lock, flags);
255 return b;
256 }
257
put_cmd640_reg(u16 reg,u8 val)258 static void put_cmd640_reg(u16 reg, u8 val)
259 {
260 unsigned long flags;
261
262 spin_lock_irqsave(&cmd640_lock, flags);
263 __put_cmd640_reg(reg, val);
264 spin_unlock_irqrestore(&cmd640_lock, flags);
265 }
266
match_pci_cmd640_device(void)267 static int __init match_pci_cmd640_device(void)
268 {
269 const u8 ven_dev[4] = {0x95, 0x10, 0x40, 0x06};
270 unsigned int i;
271 for (i = 0; i < 4; i++) {
272 if (get_cmd640_reg(i) != ven_dev[i])
273 return 0;
274 }
275 #ifdef STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT
276 if ((get_cmd640_reg(PCMD) & PCMD_ENA) == 0) {
277 printk("ide: cmd640 on PCI disabled by BIOS\n");
278 return 0;
279 }
280 #endif /* STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT */
281 return 1; /* success */
282 }
283
284 /*
285 * Probe for CMD640x -- pci method 1
286 */
probe_for_cmd640_pci1(void)287 static int __init probe_for_cmd640_pci1(void)
288 {
289 __get_cmd640_reg = get_cmd640_reg_pci1;
290 __put_cmd640_reg = put_cmd640_reg_pci1;
291 for (cmd640_key = 0x80000000;
292 cmd640_key <= 0x8000f800;
293 cmd640_key += 0x800) {
294 if (match_pci_cmd640_device())
295 return 1; /* success */
296 }
297 return 0;
298 }
299
300 /*
301 * Probe for CMD640x -- pci method 2
302 */
probe_for_cmd640_pci2(void)303 static int __init probe_for_cmd640_pci2(void)
304 {
305 __get_cmd640_reg = get_cmd640_reg_pci2;
306 __put_cmd640_reg = put_cmd640_reg_pci2;
307 for (cmd640_key = 0xc000; cmd640_key <= 0xcf00; cmd640_key += 0x100) {
308 if (match_pci_cmd640_device())
309 return 1; /* success */
310 }
311 return 0;
312 }
313
314 /*
315 * Probe for CMD640x -- vlb
316 */
probe_for_cmd640_vlb(void)317 static int __init probe_for_cmd640_vlb(void)
318 {
319 u8 b;
320
321 __get_cmd640_reg = get_cmd640_reg_vlb;
322 __put_cmd640_reg = put_cmd640_reg_vlb;
323 cmd640_key = 0x178;
324 b = get_cmd640_reg(CFR);
325 if (b == 0xff || b == 0x00 || (b & CFR_AT_VESA_078h)) {
326 cmd640_key = 0x78;
327 b = get_cmd640_reg(CFR);
328 if (b == 0xff || b == 0x00 || !(b & CFR_AT_VESA_078h))
329 return 0;
330 }
331 return 1; /* success */
332 }
333
334 /*
335 * Returns 1 if an IDE interface/drive exists at 0x170,
336 * Returns 0 otherwise.
337 */
secondary_port_responding(void)338 static int __init secondary_port_responding(void)
339 {
340 unsigned long flags;
341
342 spin_lock_irqsave(&cmd640_lock, flags);
343
344 outb_p(0x0a, 0x176); /* select drive0 */
345 udelay(100);
346 if ((inb_p(0x176) & 0x1f) != 0x0a) {
347 outb_p(0x1a, 0x176); /* select drive1 */
348 udelay(100);
349 if ((inb_p(0x176) & 0x1f) != 0x1a) {
350 spin_unlock_irqrestore(&cmd640_lock, flags);
351 return 0; /* nothing responded */
352 }
353 }
354 spin_unlock_irqrestore(&cmd640_lock, flags);
355 return 1; /* success */
356 }
357
358 #ifdef CMD640_DUMP_REGS
359 /*
360 * Dump out all cmd640 registers. May be called from ide.c
361 */
cmd640_dump_regs(void)362 static void cmd640_dump_regs(void)
363 {
364 unsigned int reg = cmd640_vlb ? 0x50 : 0x00;
365
366 /* Dump current state of chip registers */
367 printk("ide: cmd640 internal register dump:");
368 for (; reg <= 0x59; reg++) {
369 if (!(reg & 0x0f))
370 printk("\n%04x:", reg);
371 printk(" %02x", get_cmd640_reg(reg));
372 }
373 printk("\n");
374 }
375 #endif
376
__set_prefetch_mode(ide_drive_t * drive,int mode)377 static void __set_prefetch_mode(ide_drive_t *drive, int mode)
378 {
379 if (mode) { /* want prefetch on? */
380 #if CMD640_PREFETCH_MASKS
381 drive->dev_flags |= IDE_DFLAG_NO_UNMASK;
382 drive->dev_flags &= ~IDE_DFLAG_UNMASK;
383 #endif
384 drive->dev_flags &= ~IDE_DFLAG_NO_IO_32BIT;
385 } else {
386 drive->dev_flags &= ~IDE_DFLAG_NO_UNMASK;
387 drive->dev_flags |= IDE_DFLAG_NO_IO_32BIT;
388 drive->io_32bit = 0;
389 }
390 }
391
392 #ifndef CONFIG_BLK_DEV_CMD640_ENHANCED
393 /*
394 * Check whether prefetch is on for a drive,
395 * and initialize the unmask flags for safe operation.
396 */
check_prefetch(ide_drive_t * drive,unsigned int index)397 static void __init check_prefetch(ide_drive_t *drive, unsigned int index)
398 {
399 u8 b = get_cmd640_reg(prefetch_regs[index]);
400
401 __set_prefetch_mode(drive, (b & prefetch_masks[index]) ? 0 : 1);
402 }
403 #else
404
405 /*
406 * Sets prefetch mode for a drive.
407 */
set_prefetch_mode(ide_drive_t * drive,unsigned int index,int mode)408 static void set_prefetch_mode(ide_drive_t *drive, unsigned int index, int mode)
409 {
410 unsigned long flags;
411 int reg = prefetch_regs[index];
412 u8 b;
413
414 spin_lock_irqsave(&cmd640_lock, flags);
415 b = __get_cmd640_reg(reg);
416 __set_prefetch_mode(drive, mode);
417 if (mode)
418 b &= ~prefetch_masks[index]; /* enable prefetch */
419 else
420 b |= prefetch_masks[index]; /* disable prefetch */
421 __put_cmd640_reg(reg, b);
422 spin_unlock_irqrestore(&cmd640_lock, flags);
423 }
424
425 /*
426 * Dump out current drive clocks settings
427 */
display_clocks(unsigned int index)428 static void display_clocks(unsigned int index)
429 {
430 u8 active_count, recovery_count;
431
432 active_count = active_counts[index];
433 if (active_count == 1)
434 ++active_count;
435 recovery_count = recovery_counts[index];
436 if (active_count > 3 && recovery_count == 1)
437 ++recovery_count;
438 if (cmd640_chip_version > 1)
439 recovery_count += 1; /* cmd640b uses (count + 1)*/
440 printk(", clocks=%d/%d/%d\n", setup_counts[index], active_count, recovery_count);
441 }
442
443 /*
444 * Pack active and recovery counts into single byte representation
445 * used by controller
446 */
pack_nibbles(u8 upper,u8 lower)447 static inline u8 pack_nibbles(u8 upper, u8 lower)
448 {
449 return ((upper & 0x0f) << 4) | (lower & 0x0f);
450 }
451
452 /*
453 * This routine writes the prepared setup/active/recovery counts
454 * for a drive into the cmd640 chipset registers to active them.
455 */
program_drive_counts(ide_drive_t * drive,unsigned int index)456 static void program_drive_counts(ide_drive_t *drive, unsigned int index)
457 {
458 unsigned long flags;
459 u8 setup_count = setup_counts[index];
460 u8 active_count = active_counts[index];
461 u8 recovery_count = recovery_counts[index];
462
463 /*
464 * Set up address setup count and drive read/write timing registers.
465 * Primary interface has individual count/timing registers for
466 * each drive. Secondary interface has one common set of registers,
467 * so we merge the timings, using the slowest value for each timing.
468 */
469 if (index > 1) {
470 ide_drive_t *peer = ide_get_pair_dev(drive);
471 unsigned int mate = index ^ 1;
472
473 if (peer) {
474 if (setup_count < setup_counts[mate])
475 setup_count = setup_counts[mate];
476 if (active_count < active_counts[mate])
477 active_count = active_counts[mate];
478 if (recovery_count < recovery_counts[mate])
479 recovery_count = recovery_counts[mate];
480 }
481 }
482
483 /*
484 * Convert setup_count to internal chipset representation
485 */
486 switch (setup_count) {
487 case 4: setup_count = 0x00; break;
488 case 3: setup_count = 0x80; break;
489 case 1:
490 case 2: setup_count = 0x40; break;
491 default: setup_count = 0xc0; /* case 5 */
492 }
493
494 /*
495 * Now that everything is ready, program the new timings
496 */
497 spin_lock_irqsave(&cmd640_lock, flags);
498 /*
499 * Program the address_setup clocks into ARTTIM reg,
500 * and then the active/recovery counts into the DRWTIM reg
501 * (this converts counts of 16 into counts of zero -- okay).
502 */
503 setup_count |= __get_cmd640_reg(arttim_regs[index]) & 0x3f;
504 __put_cmd640_reg(arttim_regs[index], setup_count);
505 __put_cmd640_reg(drwtim_regs[index], pack_nibbles(active_count, recovery_count));
506 spin_unlock_irqrestore(&cmd640_lock, flags);
507 }
508
509 /*
510 * Set a specific pio_mode for a drive
511 */
cmd640_set_mode(ide_drive_t * drive,unsigned int index,u8 pio_mode,unsigned int cycle_time)512 static void cmd640_set_mode(ide_drive_t *drive, unsigned int index,
513 u8 pio_mode, unsigned int cycle_time)
514 {
515 struct ide_timing *t;
516 int setup_time, active_time, recovery_time, clock_time;
517 u8 setup_count, active_count, recovery_count, recovery_count2, cycle_count;
518 int bus_speed;
519
520 if (cmd640_vlb)
521 bus_speed = ide_vlb_clk ? ide_vlb_clk : 50;
522 else
523 bus_speed = ide_pci_clk ? ide_pci_clk : 33;
524
525 if (pio_mode > 5)
526 pio_mode = 5;
527
528 t = ide_timing_find_mode(XFER_PIO_0 + pio_mode);
529 setup_time = t->setup;
530 active_time = t->active;
531
532 recovery_time = cycle_time - (setup_time + active_time);
533 clock_time = 1000 / bus_speed;
534 cycle_count = DIV_ROUND_UP(cycle_time, clock_time);
535
536 setup_count = DIV_ROUND_UP(setup_time, clock_time);
537
538 active_count = DIV_ROUND_UP(active_time, clock_time);
539 if (active_count < 2)
540 active_count = 2; /* minimum allowed by cmd640 */
541
542 recovery_count = DIV_ROUND_UP(recovery_time, clock_time);
543 recovery_count2 = cycle_count - (setup_count + active_count);
544 if (recovery_count2 > recovery_count)
545 recovery_count = recovery_count2;
546 if (recovery_count < 2)
547 recovery_count = 2; /* minimum allowed by cmd640 */
548 if (recovery_count > 17) {
549 active_count += recovery_count - 17;
550 recovery_count = 17;
551 }
552 if (active_count > 16)
553 active_count = 16; /* maximum allowed by cmd640 */
554 if (cmd640_chip_version > 1)
555 recovery_count -= 1; /* cmd640b uses (count + 1)*/
556 if (recovery_count > 16)
557 recovery_count = 16; /* maximum allowed by cmd640 */
558
559 setup_counts[index] = setup_count;
560 active_counts[index] = active_count;
561 recovery_counts[index] = recovery_count;
562
563 /*
564 * In a perfect world, we might set the drive pio mode here
565 * (using WIN_SETFEATURE) before continuing.
566 *
567 * But we do not, because:
568 * 1) this is the wrong place to do it (proper is do_special() in ide.c)
569 * 2) in practice this is rarely, if ever, necessary
570 */
571 program_drive_counts(drive, index);
572 }
573
cmd640_set_pio_mode(ide_drive_t * drive,const u8 pio)574 static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio)
575 {
576 unsigned int index = 0, cycle_time;
577 u8 b;
578
579 switch (pio) {
580 case 6: /* set fast-devsel off */
581 case 7: /* set fast-devsel on */
582 b = get_cmd640_reg(CNTRL) & ~0x27;
583 if (pio & 1)
584 b |= 0x27;
585 put_cmd640_reg(CNTRL, b);
586 printk("%s: %sabled cmd640 fast host timing (devsel)\n",
587 drive->name, (pio & 1) ? "en" : "dis");
588 return;
589 case 8: /* set prefetch off */
590 case 9: /* set prefetch on */
591 set_prefetch_mode(drive, index, pio & 1);
592 printk("%s: %sabled cmd640 prefetch\n",
593 drive->name, (pio & 1) ? "en" : "dis");
594 return;
595 }
596
597 cycle_time = ide_pio_cycle_time(drive, pio);
598 cmd640_set_mode(drive, index, pio, cycle_time);
599
600 printk("%s: selected cmd640 PIO mode%d (%dns)",
601 drive->name, pio, cycle_time);
602
603 display_clocks(index);
604 }
605 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
606
cmd640_init_dev(ide_drive_t * drive)607 static void cmd640_init_dev(ide_drive_t *drive)
608 {
609 unsigned int i = drive->hwif->channel * 2 + (drive->dn & 1);
610
611 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
612 /*
613 * Reset timing to the slowest speed and turn off prefetch.
614 * This way, the drive identify code has a better chance.
615 */
616 setup_counts[i] = 4; /* max possible */
617 active_counts[i] = 16; /* max possible */
618 recovery_counts[i] = 16; /* max possible */
619 program_drive_counts(drive, i);
620 set_prefetch_mode(drive, i, 0);
621 printk(KERN_INFO DRV_NAME ": drive%d timings/prefetch cleared\n", i);
622 #else
623 /*
624 * Set the drive unmask flags to match the prefetch setting.
625 */
626 check_prefetch(drive, i);
627 printk(KERN_INFO DRV_NAME ": drive%d timings/prefetch(%s) preserved\n",
628 i, (drive->dev_flags & IDE_DFLAG_NO_IO_32BIT) ? "off" : "on");
629 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
630 }
631
632
633 static const struct ide_port_ops cmd640_port_ops = {
634 .init_dev = cmd640_init_dev,
635 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
636 .set_pio_mode = cmd640_set_pio_mode,
637 #endif
638 };
639
pci_conf1(void)640 static int pci_conf1(void)
641 {
642 unsigned long flags;
643 u32 tmp;
644
645 spin_lock_irqsave(&cmd640_lock, flags);
646 outb(0x01, 0xCFB);
647 tmp = inl(0xCF8);
648 outl(0x80000000, 0xCF8);
649 if (inl(0xCF8) == 0x80000000) {
650 outl(tmp, 0xCF8);
651 spin_unlock_irqrestore(&cmd640_lock, flags);
652 return 1;
653 }
654 outl(tmp, 0xCF8);
655 spin_unlock_irqrestore(&cmd640_lock, flags);
656 return 0;
657 }
658
pci_conf2(void)659 static int pci_conf2(void)
660 {
661 unsigned long flags;
662
663 spin_lock_irqsave(&cmd640_lock, flags);
664 outb(0x00, 0xCFB);
665 outb(0x00, 0xCF8);
666 outb(0x00, 0xCFA);
667 if (inb(0xCF8) == 0x00 && inb(0xCF8) == 0x00) {
668 spin_unlock_irqrestore(&cmd640_lock, flags);
669 return 1;
670 }
671 spin_unlock_irqrestore(&cmd640_lock, flags);
672 return 0;
673 }
674
675 static const struct ide_port_info cmd640_port_info __initdata = {
676 .chipset = ide_cmd640,
677 .host_flags = IDE_HFLAG_SERIALIZE |
678 IDE_HFLAG_NO_DMA |
679 IDE_HFLAG_ABUSE_PREFETCH |
680 IDE_HFLAG_ABUSE_FAST_DEVSEL,
681 .port_ops = &cmd640_port_ops,
682 .pio_mask = ATA_PIO5,
683 };
684
cmd640x_init_one(unsigned long base,unsigned long ctl)685 static int cmd640x_init_one(unsigned long base, unsigned long ctl)
686 {
687 if (!request_region(base, 8, DRV_NAME)) {
688 printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX not free.\n",
689 DRV_NAME, base, base + 7);
690 return -EBUSY;
691 }
692
693 if (!request_region(ctl, 1, DRV_NAME)) {
694 printk(KERN_ERR "%s: I/O resource 0x%lX not free.\n",
695 DRV_NAME, ctl);
696 release_region(base, 8);
697 return -EBUSY;
698 }
699
700 return 0;
701 }
702
703 /*
704 * Probe for a cmd640 chipset, and initialize it if found.
705 */
cmd640x_init(void)706 static int __init cmd640x_init(void)
707 {
708 int second_port_cmd640 = 0, rc;
709 const char *bus_type, *port2;
710 u8 b, cfr;
711 hw_regs_t hw[2], *hws[] = { NULL, NULL, NULL, NULL };
712
713 if (cmd640_vlb && probe_for_cmd640_vlb()) {
714 bus_type = "VLB";
715 } else {
716 cmd640_vlb = 0;
717 /* Find out what kind of PCI probing is supported otherwise
718 Justin Gibbs will sulk.. */
719 if (pci_conf1() && probe_for_cmd640_pci1())
720 bus_type = "PCI (type1)";
721 else if (pci_conf2() && probe_for_cmd640_pci2())
722 bus_type = "PCI (type2)";
723 else
724 return 0;
725 }
726 /*
727 * Undocumented magic (there is no 0x5b reg in specs)
728 */
729 put_cmd640_reg(0x5b, 0xbd);
730 if (get_cmd640_reg(0x5b) != 0xbd) {
731 printk(KERN_ERR "ide: cmd640 init failed: wrong value in reg 0x5b\n");
732 return 0;
733 }
734 put_cmd640_reg(0x5b, 0);
735
736 #ifdef CMD640_DUMP_REGS
737 cmd640_dump_regs();
738 #endif
739
740 /*
741 * Documented magic begins here
742 */
743 cfr = get_cmd640_reg(CFR);
744 cmd640_chip_version = cfr & CFR_DEVREV;
745 if (cmd640_chip_version == 0) {
746 printk("ide: bad cmd640 revision: %d\n", cmd640_chip_version);
747 return 0;
748 }
749
750 rc = cmd640x_init_one(0x1f0, 0x3f6);
751 if (rc)
752 return rc;
753
754 rc = cmd640x_init_one(0x170, 0x376);
755 if (rc) {
756 release_region(0x3f6, 1);
757 release_region(0x1f0, 8);
758 return rc;
759 }
760
761 memset(&hw, 0, sizeof(hw));
762
763 ide_std_init_ports(&hw[0], 0x1f0, 0x3f6);
764 hw[0].irq = 14;
765 hw[0].chipset = ide_cmd640;
766
767 ide_std_init_ports(&hw[1], 0x170, 0x376);
768 hw[1].irq = 15;
769 hw[1].chipset = ide_cmd640;
770
771 printk(KERN_INFO "cmd640: buggy cmd640%c interface on %s, config=0x%02x"
772 "\n", 'a' + cmd640_chip_version - 1, bus_type, cfr);
773
774 /*
775 * Initialize data for primary port
776 */
777 hws[0] = &hw[0];
778
779 /*
780 * Ensure compatibility by always using the slowest timings
781 * for access to the drive's command register block,
782 * and reset the prefetch burstsize to default (512 bytes).
783 *
784 * Maybe we need a way to NOT do these on *some* systems?
785 */
786 put_cmd640_reg(CMDTIM, 0);
787 put_cmd640_reg(BRST, 0x40);
788
789 b = get_cmd640_reg(CNTRL);
790
791 /*
792 * Try to enable the secondary interface, if not already enabled
793 */
794 if (secondary_port_responding()) {
795 if ((b & CNTRL_ENA_2ND)) {
796 second_port_cmd640 = 1;
797 port2 = "okay";
798 } else if (cmd640_vlb) {
799 second_port_cmd640 = 1;
800 port2 = "alive";
801 } else
802 port2 = "not cmd640";
803 } else {
804 put_cmd640_reg(CNTRL, b ^ CNTRL_ENA_2ND); /* toggle the bit */
805 if (secondary_port_responding()) {
806 second_port_cmd640 = 1;
807 port2 = "enabled";
808 } else {
809 put_cmd640_reg(CNTRL, b); /* restore original setting */
810 port2 = "not responding";
811 }
812 }
813
814 /*
815 * Initialize data for secondary cmd640 port, if enabled
816 */
817 if (second_port_cmd640)
818 hws[1] = &hw[1];
819
820 printk(KERN_INFO "cmd640: %sserialized, secondary interface %s\n",
821 second_port_cmd640 ? "" : "not ", port2);
822
823 #ifdef CMD640_DUMP_REGS
824 cmd640_dump_regs();
825 #endif
826
827 return ide_host_add(&cmd640_port_info, hws, NULL);
828 }
829
830 module_param_named(probe_vlb, cmd640_vlb, bool, 0);
831 MODULE_PARM_DESC(probe_vlb, "probe for VLB version of CMD640 chipset");
832
833 module_init(cmd640x_init);
834
835 MODULE_LICENSE("GPL");
836