1 /*
2 * IDE tuning and bus mastering support for the CS5510/CS5520
3 * chipsets
4 *
5 * The CS5510/CS5520 are slightly unusual devices. Unlike the
6 * typical IDE controllers they do bus mastering with the drive in
7 * PIO mode and smarter silicon.
8 *
9 * The practical upshot of this is that we must always tune the
10 * drive for the right PIO mode. We must also ignore all the blacklists
11 * and the drive bus mastering DMA information.
12 *
13 * *** This driver is strictly experimental ***
14 *
15 * (c) Copyright Red Hat Inc 2002
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2, or (at your option) any
20 * later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25 * General Public License for more details.
26 *
27 * For the avoidance of doubt the "preferred form" of this code is one which
28 * is in an open non patent encumbered format. Where cryptographic key signing
29 * forms part of the process of creating an executable the information
30 * including keys needed to generate an equivalently functional executable
31 * are deemed to be part of the source code.
32 *
33 */
34
35 #include <linux/module.h>
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/init.h>
39 #include <linux/pci.h>
40 #include <linux/ide.h>
41 #include <linux/dma-mapping.h>
42
43 #define DRV_NAME "cs5520"
44
45 struct pio_clocks
46 {
47 int address;
48 int assert;
49 int recovery;
50 };
51
52 static struct pio_clocks cs5520_pio_clocks[]={
53 {3, 6, 11},
54 {2, 5, 6},
55 {1, 4, 3},
56 {1, 3, 2},
57 {1, 2, 1}
58 };
59
cs5520_set_pio_mode(ide_drive_t * drive,const u8 pio)60 static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio)
61 {
62 ide_hwif_t *hwif = drive->hwif;
63 struct pci_dev *pdev = to_pci_dev(hwif->dev);
64 int controller = drive->dn > 1 ? 1 : 0;
65
66 /* 8bit CAT/CRT - 8bit command timing for channel */
67 pci_write_config_byte(pdev, 0x62 + controller,
68 (cs5520_pio_clocks[pio].recovery << 4) |
69 (cs5520_pio_clocks[pio].assert));
70
71 /* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
72
73 /* FIXME: should these use address ? */
74 /* Data read timing */
75 pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
76 (cs5520_pio_clocks[pio].recovery << 4) |
77 (cs5520_pio_clocks[pio].assert));
78 /* Write command timing */
79 pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
80 (cs5520_pio_clocks[pio].recovery << 4) |
81 (cs5520_pio_clocks[pio].assert));
82 }
83
cs5520_set_dma_mode(ide_drive_t * drive,const u8 speed)84 static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed)
85 {
86 printk(KERN_ERR "cs55x0: bad ide timing.\n");
87
88 cs5520_set_pio_mode(drive, 0);
89 }
90
91 static const struct ide_port_ops cs5520_port_ops = {
92 .set_pio_mode = cs5520_set_pio_mode,
93 .set_dma_mode = cs5520_set_dma_mode,
94 };
95
96 static const struct ide_port_info cyrix_chipset __devinitdata = {
97 .name = DRV_NAME,
98 .enablebits = { { 0x60, 0x01, 0x01 }, { 0x60, 0x02, 0x02 } },
99 .port_ops = &cs5520_port_ops,
100 .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_CS5520,
101 .pio_mask = ATA_PIO4,
102 };
103
104 /*
105 * The 5510/5520 are a bit weird. They don't quite set up the way
106 * the PCI helper layer expects so we must do much of the set up
107 * work longhand.
108 */
109
cs5520_init_one(struct pci_dev * dev,const struct pci_device_id * id)110 static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
111 {
112 const struct ide_port_info *d = &cyrix_chipset;
113 hw_regs_t hw[4], *hws[] = { NULL, NULL, NULL, NULL };
114
115 ide_setup_pci_noise(dev, d);
116
117 /* We must not grab the entire device, it has 'ISA' space in its
118 * BARS too and we will freak out other bits of the kernel
119 */
120 if (pci_enable_device_io(dev)) {
121 printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
122 return -ENODEV;
123 }
124 pci_set_master(dev);
125 if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
126 printk(KERN_WARNING "%s: No suitable DMA available.\n",
127 d->name);
128 return -ENODEV;
129 }
130
131 /*
132 * Now the chipset is configured we can let the core
133 * do all the device setup for us
134 */
135
136 ide_pci_setup_ports(dev, d, 14, &hw[0], &hws[0]);
137
138 return ide_host_add(d, hws, NULL);
139 }
140
141 static const struct pci_device_id cs5520_pci_tbl[] = {
142 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), 0 },
143 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), 1 },
144 { 0, },
145 };
146 MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
147
148 static struct pci_driver cs5520_pci_driver = {
149 .name = "Cyrix_IDE",
150 .id_table = cs5520_pci_tbl,
151 .probe = cs5520_init_one,
152 .suspend = ide_pci_suspend,
153 .resume = ide_pci_resume,
154 };
155
cs5520_ide_init(void)156 static int __init cs5520_ide_init(void)
157 {
158 return ide_pci_register_driver(&cs5520_pci_driver);
159 }
160
161 module_init(cs5520_ide_init);
162
163 MODULE_AUTHOR("Alan Cox");
164 MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
165 MODULE_LICENSE("GPL");
166