1 /*
2 * generic/default IDE host driver
3 *
4 * Copyright (C) 2004, 2008 Bartlomiej Zolnierkiewicz
5 * This code was split off from ide.c. See it for original copyrights.
6 *
7 * May be copied or modified under the terms of the GNU General Public License.
8 */
9
10 /*
11 * For special cases new interfaces may be added using sysfs, i.e.
12 *
13 * echo -n "0x168:0x36e:10" > /sys/class/ide_generic/add
14 *
15 * will add an interface using I/O ports 0x168-0x16f/0x36e and IRQ 10.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/ide.h>
22 #include <linux/pci_ids.h>
23
24 /* FIXME: convert m32r to use ide_platform host driver */
25 #ifdef CONFIG_M32R
26 #include <asm/m32r.h>
27 #endif
28
29 #define DRV_NAME "ide_generic"
30
31 static int probe_mask;
32 module_param(probe_mask, int, 0);
33 MODULE_PARM_DESC(probe_mask, "probe mask for legacy ISA IDE ports");
34
store_add(struct class * cls,const char * buf,size_t n)35 static ssize_t store_add(struct class *cls, const char *buf, size_t n)
36 {
37 unsigned int base, ctl;
38 int irq, rc;
39 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
40
41 if (sscanf(buf, "%x:%x:%d", &base, &ctl, &irq) != 3)
42 return -EINVAL;
43
44 memset(&hw, 0, sizeof(hw));
45 ide_std_init_ports(&hw, base, ctl);
46 hw.irq = irq;
47 hw.chipset = ide_generic;
48
49 rc = ide_host_add(NULL, hws, NULL);
50 if (rc)
51 return rc;
52
53 return n;
54 };
55
56 static struct class_attribute ide_generic_class_attrs[] = {
57 __ATTR(add, S_IWUSR, NULL, store_add),
58 __ATTR_NULL
59 };
60
ide_generic_class_release(struct class * cls)61 static void ide_generic_class_release(struct class *cls)
62 {
63 kfree(cls);
64 }
65
ide_generic_sysfs_init(void)66 static int __init ide_generic_sysfs_init(void)
67 {
68 struct class *cls;
69 int rc;
70
71 cls = kzalloc(sizeof(*cls), GFP_KERNEL);
72 if (!cls)
73 return -ENOMEM;
74
75 cls->name = DRV_NAME;
76 cls->owner = THIS_MODULE;
77 cls->class_release = ide_generic_class_release;
78 cls->class_attrs = ide_generic_class_attrs;
79
80 rc = class_register(cls);
81 if (rc) {
82 kfree(cls);
83 return rc;
84 }
85
86 return 0;
87 }
88
89 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) \
90 || defined(CONFIG_PLAT_OPSPUT)
91 static const u16 legacy_bases[] = { 0x1f0 };
92 static const int legacy_irqs[] = { PLD_IRQ_CFIREQ };
93 #elif defined(CONFIG_PLAT_MAPPI3)
94 static const u16 legacy_bases[] = { 0x1f0, 0x170 };
95 static const int legacy_irqs[] = { PLD_IRQ_CFIREQ, PLD_IRQ_IDEIREQ };
96 #elif defined(CONFIG_ALPHA)
97 static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168 };
98 static const int legacy_irqs[] = { 14, 15, 11, 10 };
99 #else
100 static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
101 static const int legacy_irqs[] = { 14, 15, 11, 10, 8, 12 };
102 #endif
103
ide_generic_check_pci_legacy_iobases(int * primary,int * secondary)104 static void ide_generic_check_pci_legacy_iobases(int *primary, int *secondary)
105 {
106 struct pci_dev *p = NULL;
107 u16 val;
108
109 for_each_pci_dev(p) {
110
111 if (pci_resource_start(p, 0) == 0x1f0)
112 *primary = 1;
113 if (pci_resource_start(p, 2) == 0x170)
114 *secondary = 1;
115
116 /* Cyrix CS55{1,2}0 pre SFF MWDMA ATA on the bridge */
117 if (p->vendor == PCI_VENDOR_ID_CYRIX &&
118 (p->device == PCI_DEVICE_ID_CYRIX_5510 ||
119 p->device == PCI_DEVICE_ID_CYRIX_5520))
120 *primary = *secondary = 1;
121
122 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
123 if (p->vendor == PCI_VENDOR_ID_INTEL &&
124 p->device == PCI_DEVICE_ID_INTEL_82371MX) {
125
126 pci_read_config_word(p, 0x6C, &val);
127 if (val & 0x8000) {
128 /* ATA port enabled */
129 if (val & 0x4000)
130 *secondary = 1;
131 else
132 *primary = 1;
133 }
134 }
135 }
136 }
137
ide_generic_init(void)138 static int __init ide_generic_init(void)
139 {
140 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
141 unsigned long io_addr;
142 int i, rc = 0, primary = 0, secondary = 0;
143
144 ide_generic_check_pci_legacy_iobases(&primary, &secondary);
145
146 if (!probe_mask) {
147 printk(KERN_INFO DRV_NAME ": please use \"probe_mask=0x3f\" "
148 "module parameter for probing all legacy ISA IDE ports\n");
149
150 if (primary == 0)
151 probe_mask |= 0x1;
152
153 if (secondary == 0)
154 probe_mask |= 0x2;
155 } else
156 printk(KERN_INFO DRV_NAME ": enforcing probing of I/O ports "
157 "upon user request\n");
158
159 for (i = 0; i < ARRAY_SIZE(legacy_bases); i++) {
160 io_addr = legacy_bases[i];
161
162 if ((probe_mask & (1 << i)) && io_addr) {
163 if (!request_region(io_addr, 8, DRV_NAME)) {
164 printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX "
165 "not free.\n",
166 DRV_NAME, io_addr, io_addr + 7);
167 continue;
168 }
169
170 if (!request_region(io_addr + 0x206, 1, DRV_NAME)) {
171 printk(KERN_ERR "%s: I/O resource 0x%lX "
172 "not free.\n",
173 DRV_NAME, io_addr + 0x206);
174 release_region(io_addr, 8);
175 continue;
176 }
177
178 memset(&hw, 0, sizeof(hw));
179 ide_std_init_ports(&hw, io_addr, io_addr + 0x206);
180 #ifdef CONFIG_IA64
181 hw.irq = isa_irq_to_vector(legacy_irqs[i]);
182 #else
183 hw.irq = legacy_irqs[i];
184 #endif
185 hw.chipset = ide_generic;
186
187 rc = ide_host_add(NULL, hws, NULL);
188 if (rc) {
189 release_region(io_addr + 0x206, 1);
190 release_region(io_addr, 8);
191 }
192 }
193 }
194
195 if (ide_generic_sysfs_init())
196 printk(KERN_ERR DRV_NAME ": failed to create ide_generic "
197 "class\n");
198
199 return rc;
200 }
201
202 module_init(ide_generic_init);
203
204 MODULE_LICENSE("GPL");
205