1 /*
2 * Q40 I/O port IDE Driver
3 *
4 * (c) Richard Zidlicky
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 *
11 */
12
13 #include <linux/types.h>
14 #include <linux/mm.h>
15 #include <linux/interrupt.h>
16 #include <linux/blkdev.h>
17 #include <linux/ide.h>
18
19 /*
20 * Bases of the IDE interfaces
21 */
22
23 #define Q40IDE_NUM_HWIFS 2
24
25 #define PCIDE_BASE1 0x1f0
26 #define PCIDE_BASE2 0x170
27 #define PCIDE_BASE3 0x1e8
28 #define PCIDE_BASE4 0x168
29 #define PCIDE_BASE5 0x1e0
30 #define PCIDE_BASE6 0x160
31
32 static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
33 PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
34 PCIDE_BASE6 */
35 };
36
q40ide_default_irq(unsigned long base)37 static int q40ide_default_irq(unsigned long base)
38 {
39 switch (base) {
40 case 0x1f0: return 14;
41 case 0x170: return 15;
42 case 0x1e8: return 11;
43 default:
44 return 0;
45 }
46 }
47
48
49 /*
50 * Addresses are pretranslated for Q40 ISA access.
51 */
q40_ide_setup_ports(hw_regs_t * hw,unsigned long base,ide_ack_intr_t * ack_intr,int irq)52 static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
53 ide_ack_intr_t *ack_intr,
54 int irq)
55 {
56 memset(hw, 0, sizeof(hw_regs_t));
57 /* BIG FAT WARNING:
58 assumption: only DATA port is ever used in 16 bit mode */
59 hw->io_ports.data_addr = Q40_ISA_IO_W(base);
60 hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
61 hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
62 hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
63 hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
64 hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
65 hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
66 hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
67 hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
68
69 hw->irq = irq;
70 hw->ack_intr = ack_intr;
71
72 hw->chipset = ide_generic;
73 }
74
q40ide_input_data(ide_drive_t * drive,struct request * rq,void * buf,unsigned int len)75 static void q40ide_input_data(ide_drive_t *drive, struct request *rq,
76 void *buf, unsigned int len)
77 {
78 unsigned long data_addr = drive->hwif->io_ports.data_addr;
79
80 if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
81 return insw(data_addr, buf, (len + 1) / 2);
82
83 insw_swapw(data_addr, buf, (len + 1) / 2);
84 }
85
q40ide_output_data(ide_drive_t * drive,struct request * rq,void * buf,unsigned int len)86 static void q40ide_output_data(ide_drive_t *drive, struct request *rq,
87 void *buf, unsigned int len)
88 {
89 unsigned long data_addr = drive->hwif->io_ports.data_addr;
90
91 if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
92 return outsw(data_addr, buf, (len + 1) / 2);
93
94 outsw_swapw(data_addr, buf, (len + 1) / 2);
95 }
96
97 /* Q40 has a byte-swapped IDE interface */
98 static const struct ide_tp_ops q40ide_tp_ops = {
99 .exec_command = ide_exec_command,
100 .read_status = ide_read_status,
101 .read_altstatus = ide_read_altstatus,
102
103 .set_irq = ide_set_irq,
104
105 .tf_load = ide_tf_load,
106 .tf_read = ide_tf_read,
107
108 .input_data = q40ide_input_data,
109 .output_data = q40ide_output_data,
110 };
111
112 static const struct ide_port_info q40ide_port_info = {
113 .tp_ops = &q40ide_tp_ops,
114 .host_flags = IDE_HFLAG_NO_DMA,
115 };
116
117 /*
118 * the static array is needed to have the name reported in /proc/ioports,
119 * hwif->name unfortunately isn't available yet
120 */
121 static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
122 "ide0", "ide1"
123 };
124
125 /*
126 * Probe for Q40 IDE interfaces
127 */
128
q40ide_init(void)129 static int __init q40ide_init(void)
130 {
131 int i;
132 hw_regs_t hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL, NULL, NULL };
133
134 if (!MACH_IS_Q40)
135 return -ENODEV;
136
137 printk(KERN_INFO "ide: Q40 IDE controller\n");
138
139 for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
140 const char *name = q40_ide_names[i];
141
142 if (!request_region(pcide_bases[i], 8, name)) {
143 printk("could not reserve ports %lx-%lx for %s\n",
144 pcide_bases[i],pcide_bases[i]+8,name);
145 continue;
146 }
147 if (!request_region(pcide_bases[i]+0x206, 1, name)) {
148 printk("could not reserve port %lx for %s\n",
149 pcide_bases[i]+0x206,name);
150 release_region(pcide_bases[i], 8);
151 continue;
152 }
153 q40_ide_setup_ports(&hw[i], pcide_bases[i], NULL,
154 q40ide_default_irq(pcide_bases[i]));
155
156 hws[i] = &hw[i];
157 }
158
159 return ide_host_add(&q40ide_port_info, hws, NULL);
160 }
161
162 module_init(q40ide_init);
163
164 MODULE_LICENSE("GPL");
165