1 /*
2 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
3 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
4 *
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Development of this chipset driver was funded
8 * by the nice folks at National Semiconductor.
9 *
10 * Documentation:
11 * Available from National Semiconductor
12 */
13
14 #include <linux/module.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ide.h>
20 #include <linux/pm.h>
21
22 #include <asm/io.h>
23
24 #define DRV_NAME "sc1200"
25
26 #define SC1200_REV_A 0x00
27 #define SC1200_REV_B1 0x01
28 #define SC1200_REV_B3 0x02
29 #define SC1200_REV_C1 0x03
30 #define SC1200_REV_D1 0x04
31
32 #define PCI_CLK_33 0x00
33 #define PCI_CLK_48 0x01
34 #define PCI_CLK_66 0x02
35 #define PCI_CLK_33A 0x03
36
sc1200_get_pci_clock(void)37 static unsigned short sc1200_get_pci_clock (void)
38 {
39 unsigned char chip_id, silicon_revision;
40 unsigned int pci_clock;
41 /*
42 * Check the silicon revision, as not all versions of the chip
43 * have the register with the fast PCI bus timings.
44 */
45 chip_id = inb (0x903c);
46 silicon_revision = inb (0x903d);
47
48 // Read the fast pci clock frequency
49 if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
50 pci_clock = PCI_CLK_33;
51 } else {
52 // check clock generator configuration (cfcc)
53 // the clock is in bits 8 and 9 of this word
54
55 pci_clock = inw (0x901e);
56 pci_clock >>= 8;
57 pci_clock &= 0x03;
58 if (pci_clock == PCI_CLK_33A)
59 pci_clock = PCI_CLK_33;
60 }
61 return pci_clock;
62 }
63
64 /*
65 * Here are the standard PIO mode 0-4 timings for each "format".
66 * Format-0 uses fast data reg timings, with slower command reg timings.
67 * Format-1 uses fast timings for all registers, but won't work with all drives.
68 */
69 static const unsigned int sc1200_pio_timings[4][5] =
70 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
71 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
72 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
73 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
74
75 /*
76 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
77 */
78 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
79
sc1200_tunepio(ide_drive_t * drive,u8 pio)80 static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
81 {
82 ide_hwif_t *hwif = drive->hwif;
83 struct pci_dev *pdev = to_pci_dev(hwif->dev);
84 unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
85
86 pci_read_config_dword(pdev, basereg + 4, &format);
87 format = (format >> 31) & 1;
88 if (format)
89 format += sc1200_get_pci_clock();
90 pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
91 sc1200_pio_timings[format][pio]);
92 }
93
94 /*
95 * The SC1200 specifies that two drives sharing a cable cannot mix
96 * UDMA/MDMA. It has to be one or the other, for the pair, though
97 * different timings can still be chosen for each drive. We could
98 * set the appropriate timing bits on the fly, but that might be
99 * a bit confusing. So, for now we statically handle this requirement
100 * by looking at our mate drive to see what it is capable of, before
101 * choosing a mode for our own drive.
102 */
sc1200_udma_filter(ide_drive_t * drive)103 static u8 sc1200_udma_filter(ide_drive_t *drive)
104 {
105 ide_hwif_t *hwif = drive->hwif;
106 ide_drive_t *mate = ide_get_pair_dev(drive);
107 u16 *mateid;
108 u8 mask = hwif->ultra_mask;
109
110 if (mate == NULL)
111 goto out;
112 mateid = mate->id;
113
114 if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
115 if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
116 (mateid[ATA_ID_UDMA_MODES] & 7))
117 goto out;
118 if ((mateid[ATA_ID_FIELD_VALID] & 2) &&
119 (mateid[ATA_ID_MWDMA_MODES] & 7))
120 mask = 0;
121 }
122 out:
123 return mask;
124 }
125
sc1200_set_dma_mode(ide_drive_t * drive,const u8 mode)126 static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
127 {
128 ide_hwif_t *hwif = drive->hwif;
129 struct pci_dev *dev = to_pci_dev(hwif->dev);
130 unsigned int reg, timings;
131 unsigned short pci_clock;
132 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
133
134 static const u32 udma_timing[3][3] = {
135 { 0x00921250, 0x00911140, 0x00911030 },
136 { 0x00932470, 0x00922260, 0x00922140 },
137 { 0x009436a1, 0x00933481, 0x00923261 },
138 };
139
140 static const u32 mwdma_timing[3][3] = {
141 { 0x00077771, 0x00012121, 0x00002020 },
142 { 0x000bbbb2, 0x00024241, 0x00013131 },
143 { 0x000ffff3, 0x00035352, 0x00015151 },
144 };
145
146 pci_clock = sc1200_get_pci_clock();
147
148 /*
149 * Note that each DMA mode has several timings associated with it.
150 * The correct timing depends on the fast PCI clock freq.
151 */
152
153 if (mode >= XFER_UDMA_0)
154 timings = udma_timing[pci_clock][mode - XFER_UDMA_0];
155 else
156 timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
157
158 if ((drive->dn & 1) == 0) {
159 pci_read_config_dword(dev, basereg + 4, ®);
160 timings |= reg & 0x80000000; /* preserve PIO format bit */
161 pci_write_config_dword(dev, basereg + 4, timings);
162 } else
163 pci_write_config_dword(dev, basereg + 12, timings);
164 }
165
166 /* Replacement for the standard ide_dma_end action in
167 * dma_proc.
168 *
169 * returns 1 on error, 0 otherwise
170 */
sc1200_dma_end(ide_drive_t * drive)171 static int sc1200_dma_end(ide_drive_t *drive)
172 {
173 ide_hwif_t *hwif = drive->hwif;
174 unsigned long dma_base = hwif->dma_base;
175 u8 dma_stat;
176
177 dma_stat = inb(dma_base+2); /* get DMA status */
178
179 if (!(dma_stat & 4))
180 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
181 dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
182
183 outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
184 outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
185
186 drive->waiting_for_dma = 0;
187 ide_destroy_dmatable(drive); /* purge DMA mappings */
188
189 return (dma_stat & 7) != 4; /* verify good DMA status */
190 }
191
192 /*
193 * sc1200_set_pio_mode() handles setting of PIO modes
194 * for both the chipset and drive.
195 *
196 * All existing BIOSs for this chipset guarantee that all drives
197 * will have valid default PIO timings set up before we get here.
198 */
199
sc1200_set_pio_mode(ide_drive_t * drive,const u8 pio)200 static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
201 {
202 ide_hwif_t *hwif = drive->hwif;
203 int mode = -1;
204
205 /*
206 * bad abuse of ->set_pio_mode interface
207 */
208 switch (pio) {
209 case 200: mode = XFER_UDMA_0; break;
210 case 201: mode = XFER_UDMA_1; break;
211 case 202: mode = XFER_UDMA_2; break;
212 case 100: mode = XFER_MW_DMA_0; break;
213 case 101: mode = XFER_MW_DMA_1; break;
214 case 102: mode = XFER_MW_DMA_2; break;
215 }
216 if (mode != -1) {
217 printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
218 ide_dma_off_quietly(drive);
219 if (ide_set_dma_mode(drive, mode) == 0 &&
220 (drive->dev_flags & IDE_DFLAG_USING_DMA))
221 hwif->dma_ops->dma_host_set(drive, 1);
222 return;
223 }
224
225 sc1200_tunepio(drive, pio);
226 }
227
228 #ifdef CONFIG_PM
229 struct sc1200_saved_state {
230 u32 regs[8];
231 };
232
sc1200_suspend(struct pci_dev * dev,pm_message_t state)233 static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
234 {
235 printk("SC1200: suspend(%u)\n", state.event);
236
237 /*
238 * we only save state when going from full power to less
239 */
240 if (state.event == PM_EVENT_ON) {
241 struct ide_host *host = pci_get_drvdata(dev);
242 struct sc1200_saved_state *ss = host->host_priv;
243 unsigned int r;
244
245 /*
246 * save timing registers
247 * (this may be unnecessary if BIOS also does it)
248 */
249 for (r = 0; r < 8; r++)
250 pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
251 }
252
253 pci_disable_device(dev);
254 pci_set_power_state(dev, pci_choose_state(dev, state));
255 return 0;
256 }
257
sc1200_resume(struct pci_dev * dev)258 static int sc1200_resume (struct pci_dev *dev)
259 {
260 struct ide_host *host = pci_get_drvdata(dev);
261 struct sc1200_saved_state *ss = host->host_priv;
262 unsigned int r;
263 int i;
264
265 i = pci_enable_device(dev);
266 if (i)
267 return i;
268
269 /*
270 * restore timing registers
271 * (this may be unnecessary if BIOS also does it)
272 */
273 for (r = 0; r < 8; r++)
274 pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
275
276 return 0;
277 }
278 #endif
279
280 static const struct ide_port_ops sc1200_port_ops = {
281 .set_pio_mode = sc1200_set_pio_mode,
282 .set_dma_mode = sc1200_set_dma_mode,
283 .udma_filter = sc1200_udma_filter,
284 };
285
286 static const struct ide_dma_ops sc1200_dma_ops = {
287 .dma_host_set = ide_dma_host_set,
288 .dma_setup = ide_dma_setup,
289 .dma_exec_cmd = ide_dma_exec_cmd,
290 .dma_start = ide_dma_start,
291 .dma_end = sc1200_dma_end,
292 .dma_test_irq = ide_dma_test_irq,
293 .dma_lost_irq = ide_dma_lost_irq,
294 .dma_timeout = ide_dma_timeout,
295 .dma_sff_read_status = ide_dma_sff_read_status,
296 };
297
298 static const struct ide_port_info sc1200_chipset __devinitdata = {
299 .name = DRV_NAME,
300 .port_ops = &sc1200_port_ops,
301 .dma_ops = &sc1200_dma_ops,
302 .host_flags = IDE_HFLAG_SERIALIZE |
303 IDE_HFLAG_POST_SET_MODE |
304 IDE_HFLAG_ABUSE_DMA_MODES,
305 .pio_mask = ATA_PIO4,
306 .mwdma_mask = ATA_MWDMA2,
307 .udma_mask = ATA_UDMA2,
308 };
309
sc1200_init_one(struct pci_dev * dev,const struct pci_device_id * id)310 static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
311 {
312 struct sc1200_saved_state *ss = NULL;
313 int rc;
314
315 #ifdef CONFIG_PM
316 ss = kmalloc(sizeof(*ss), GFP_KERNEL);
317 if (ss == NULL)
318 return -ENOMEM;
319 #endif
320 rc = ide_pci_init_one(dev, &sc1200_chipset, ss);
321 if (rc)
322 kfree(ss);
323
324 return rc;
325 }
326
327 static const struct pci_device_id sc1200_pci_tbl[] = {
328 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
329 { 0, },
330 };
331 MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
332
333 static struct pci_driver sc1200_pci_driver = {
334 .name = "SC1200_IDE",
335 .id_table = sc1200_pci_tbl,
336 .probe = sc1200_init_one,
337 .remove = ide_pci_remove,
338 #ifdef CONFIG_PM
339 .suspend = sc1200_suspend,
340 .resume = sc1200_resume,
341 #endif
342 };
343
sc1200_ide_init(void)344 static int __init sc1200_ide_init(void)
345 {
346 return ide_pci_register_driver(&sc1200_pci_driver);
347 }
348
sc1200_ide_exit(void)349 static void __exit sc1200_ide_exit(void)
350 {
351 pci_unregister_driver(&sc1200_pci_driver);
352 }
353
354 module_init(sc1200_ide_init);
355 module_exit(sc1200_ide_exit);
356
357 MODULE_AUTHOR("Mark Lord");
358 MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
359 MODULE_LICENSE("GPL");
360