1 /*
2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat
4 * Copyright (C) 2007-2008 MontaVista Software, Inc.
5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
11 *
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
14 *
15 * Errata and other documentation only available under NDA.
16 *
17 *
18 * FAQ Items:
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5, not UDMA6.
21 *
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang.
24 *
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
27 * if necessary
28 *
29 * The Dell DRAC4 has some interesting features including effectively hot
30 * unplugging/replugging the virtual CD interface when the DRAC is reset.
31 * This often causes drivers/ide/siimage to panic but is ok with the rather
32 * smarter code in libata.
33 *
34 * TODO:
35 * - IORDY fixes
36 * - VDMA support
37 */
38
39 #include <linux/types.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/ide.h>
43 #include <linux/init.h>
44 #include <linux/io.h>
45
46 #define DRV_NAME "siimage"
47
48 /**
49 * pdev_is_sata - check if device is SATA
50 * @pdev: PCI device to check
51 *
52 * Returns true if this is a SATA controller
53 */
54
pdev_is_sata(struct pci_dev * pdev)55 static int pdev_is_sata(struct pci_dev *pdev)
56 {
57 #ifdef CONFIG_BLK_DEV_IDE_SATA
58 switch (pdev->device) {
59 case PCI_DEVICE_ID_SII_3112:
60 case PCI_DEVICE_ID_SII_1210SA:
61 return 1;
62 case PCI_DEVICE_ID_SII_680:
63 return 0;
64 }
65 BUG();
66 #endif
67 return 0;
68 }
69
70 /**
71 * is_sata - check if hwif is SATA
72 * @hwif: interface to check
73 *
74 * Returns true if this is a SATA controller
75 */
76
is_sata(ide_hwif_t * hwif)77 static inline int is_sata(ide_hwif_t *hwif)
78 {
79 return pdev_is_sata(to_pci_dev(hwif->dev));
80 }
81
82 /**
83 * siimage_selreg - return register base
84 * @hwif: interface
85 * @r: config offset
86 *
87 * Turn a config register offset into the right address in either
88 * PCI space or MMIO space to access the control register in question
89 * Thankfully this is a configuration operation, so isn't performance
90 * critical.
91 */
92
siimage_selreg(ide_hwif_t * hwif,int r)93 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
94 {
95 unsigned long base = (unsigned long)hwif->hwif_data;
96
97 base += 0xA0 + r;
98 if (hwif->host_flags & IDE_HFLAG_MMIO)
99 base += hwif->channel << 6;
100 else
101 base += hwif->channel << 4;
102 return base;
103 }
104
105 /**
106 * siimage_seldev - return register base
107 * @hwif: interface
108 * @r: config offset
109 *
110 * Turn a config register offset into the right address in either
111 * PCI space or MMIO space to access the control register in question
112 * including accounting for the unit shift.
113 */
114
siimage_seldev(ide_drive_t * drive,int r)115 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
116 {
117 ide_hwif_t *hwif = drive->hwif;
118 unsigned long base = (unsigned long)hwif->hwif_data;
119 u8 unit = drive->dn & 1;
120
121 base += 0xA0 + r;
122 if (hwif->host_flags & IDE_HFLAG_MMIO)
123 base += hwif->channel << 6;
124 else
125 base += hwif->channel << 4;
126 base |= unit << unit;
127 return base;
128 }
129
sil_ioread8(struct pci_dev * dev,unsigned long addr)130 static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
131 {
132 struct ide_host *host = pci_get_drvdata(dev);
133 u8 tmp = 0;
134
135 if (host->host_priv)
136 tmp = readb((void __iomem *)addr);
137 else
138 pci_read_config_byte(dev, addr, &tmp);
139
140 return tmp;
141 }
142
sil_ioread16(struct pci_dev * dev,unsigned long addr)143 static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
144 {
145 struct ide_host *host = pci_get_drvdata(dev);
146 u16 tmp = 0;
147
148 if (host->host_priv)
149 tmp = readw((void __iomem *)addr);
150 else
151 pci_read_config_word(dev, addr, &tmp);
152
153 return tmp;
154 }
155
sil_iowrite8(struct pci_dev * dev,u8 val,unsigned long addr)156 static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
157 {
158 struct ide_host *host = pci_get_drvdata(dev);
159
160 if (host->host_priv)
161 writeb(val, (void __iomem *)addr);
162 else
163 pci_write_config_byte(dev, addr, val);
164 }
165
sil_iowrite16(struct pci_dev * dev,u16 val,unsigned long addr)166 static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
167 {
168 struct ide_host *host = pci_get_drvdata(dev);
169
170 if (host->host_priv)
171 writew(val, (void __iomem *)addr);
172 else
173 pci_write_config_word(dev, addr, val);
174 }
175
sil_iowrite32(struct pci_dev * dev,u32 val,unsigned long addr)176 static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
177 {
178 struct ide_host *host = pci_get_drvdata(dev);
179
180 if (host->host_priv)
181 writel(val, (void __iomem *)addr);
182 else
183 pci_write_config_dword(dev, addr, val);
184 }
185
186 /**
187 * sil_udma_filter - compute UDMA mask
188 * @drive: IDE device
189 *
190 * Compute the available UDMA speeds for the device on the interface.
191 *
192 * For the CMD680 this depends on the clocking mode (scsc), for the
193 * SI3112 SATA controller life is a bit simpler.
194 */
195
sil_pata_udma_filter(ide_drive_t * drive)196 static u8 sil_pata_udma_filter(ide_drive_t *drive)
197 {
198 ide_hwif_t *hwif = drive->hwif;
199 struct pci_dev *dev = to_pci_dev(hwif->dev);
200 unsigned long base = (unsigned long)hwif->hwif_data;
201 u8 scsc, mask = 0;
202
203 base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A;
204
205 scsc = sil_ioread8(dev, base);
206
207 switch (scsc & 0x30) {
208 case 0x10: /* 133 */
209 mask = ATA_UDMA6;
210 break;
211 case 0x20: /* 2xPCI */
212 mask = ATA_UDMA6;
213 break;
214 case 0x00: /* 100 */
215 mask = ATA_UDMA5;
216 break;
217 default: /* Disabled ? */
218 BUG();
219 }
220
221 return mask;
222 }
223
sil_sata_udma_filter(ide_drive_t * drive)224 static u8 sil_sata_udma_filter(ide_drive_t *drive)
225 {
226 char *m = (char *)&drive->id[ATA_ID_PROD];
227
228 return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
229 }
230
231 /**
232 * sil_set_pio_mode - set host controller for PIO mode
233 * @drive: drive
234 * @pio: PIO mode number
235 *
236 * Load the timing settings for this device mode into the
237 * controller. If we are in PIO mode 3 or 4 turn on IORDY
238 * monitoring (bit 9). The TF timing is bits 31:16
239 */
240
sil_set_pio_mode(ide_drive_t * drive,u8 pio)241 static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
242 {
243 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
244 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
245
246 ide_hwif_t *hwif = drive->hwif;
247 struct pci_dev *dev = to_pci_dev(hwif->dev);
248 ide_drive_t *pair = ide_get_pair_dev(drive);
249 u32 speedt = 0;
250 u16 speedp = 0;
251 unsigned long addr = siimage_seldev(drive, 0x04);
252 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
253 unsigned long base = (unsigned long)hwif->hwif_data;
254 u8 tf_pio = pio;
255 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
256 u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
257 : (mmio ? 0xB4 : 0x80);
258 u8 mode = 0;
259 u8 unit = drive->dn & 1;
260
261 /* trim *taskfile* PIO to the slowest of the master/slave */
262 if (pair) {
263 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
264
265 if (pair_pio < tf_pio)
266 tf_pio = pair_pio;
267 }
268
269 /* cheat for now and use the docs */
270 speedp = data_speed[pio];
271 speedt = tf_speed[tf_pio];
272
273 sil_iowrite16(dev, speedp, addr);
274 sil_iowrite16(dev, speedt, tfaddr);
275
276 /* now set up IORDY */
277 speedp = sil_ioread16(dev, tfaddr - 2);
278 speedp &= ~0x200;
279 if (pio > 2)
280 speedp |= 0x200;
281 sil_iowrite16(dev, speedp, tfaddr - 2);
282
283 mode = sil_ioread8(dev, base + addr_mask);
284 mode &= ~(unit ? 0x30 : 0x03);
285 mode |= unit ? 0x10 : 0x01;
286 sil_iowrite8(dev, mode, base + addr_mask);
287 }
288
289 /**
290 * sil_set_dma_mode - set host controller for DMA mode
291 * @drive: drive
292 * @speed: DMA mode
293 *
294 * Tune the SiI chipset for the desired DMA mode.
295 */
296
sil_set_dma_mode(ide_drive_t * drive,const u8 speed)297 static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
298 {
299 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
300 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
301 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
302
303 ide_hwif_t *hwif = drive->hwif;
304 struct pci_dev *dev = to_pci_dev(hwif->dev);
305 unsigned long base = (unsigned long)hwif->hwif_data;
306 u16 ultra = 0, multi = 0;
307 u8 mode = 0, unit = drive->dn & 1;
308 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
309 u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
310 : (mmio ? 0xB4 : 0x80);
311 unsigned long ma = siimage_seldev(drive, 0x08);
312 unsigned long ua = siimage_seldev(drive, 0x0C);
313
314 scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
315 mode = sil_ioread8 (dev, base + addr_mask);
316 multi = sil_ioread16(dev, ma);
317 ultra = sil_ioread16(dev, ua);
318
319 mode &= ~(unit ? 0x30 : 0x03);
320 ultra &= ~0x3F;
321 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
322
323 scsc = is_sata(hwif) ? 1 : scsc;
324
325 if (speed >= XFER_UDMA_0) {
326 multi = dma[2];
327 ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
328 ultra5[speed - XFER_UDMA_0];
329 mode |= unit ? 0x30 : 0x03;
330 } else {
331 multi = dma[speed - XFER_MW_DMA_0];
332 mode |= unit ? 0x20 : 0x02;
333 }
334
335 sil_iowrite8 (dev, mode, base + addr_mask);
336 sil_iowrite16(dev, multi, ma);
337 sil_iowrite16(dev, ultra, ua);
338 }
339
340 /* returns 1 if dma irq issued, 0 otherwise */
siimage_io_dma_test_irq(ide_drive_t * drive)341 static int siimage_io_dma_test_irq(ide_drive_t *drive)
342 {
343 ide_hwif_t *hwif = drive->hwif;
344 struct pci_dev *dev = to_pci_dev(hwif->dev);
345 u8 dma_altstat = 0;
346 unsigned long addr = siimage_selreg(hwif, 1);
347
348 /* return 1 if INTR asserted */
349 if (inb(hwif->dma_base + ATA_DMA_STATUS) & 4)
350 return 1;
351
352 /* return 1 if Device INTR asserted */
353 pci_read_config_byte(dev, addr, &dma_altstat);
354 if (dma_altstat & 8)
355 return 0; /* return 1; */
356
357 return 0;
358 }
359
360 /**
361 * siimage_mmio_dma_test_irq - check we caused an IRQ
362 * @drive: drive we are testing
363 *
364 * Check if we caused an IDE DMA interrupt. We may also have caused
365 * SATA status interrupts, if so we clean them up and continue.
366 */
367
siimage_mmio_dma_test_irq(ide_drive_t * drive)368 static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
369 {
370 ide_hwif_t *hwif = drive->hwif;
371 unsigned long addr = siimage_selreg(hwif, 0x1);
372 void __iomem *sata_error_addr
373 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
374
375 if (sata_error_addr) {
376 unsigned long base = (unsigned long)hwif->hwif_data;
377 u32 ext_stat = readl((void __iomem *)(base + 0x10));
378 u8 watchdog = 0;
379
380 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
381 u32 sata_error = readl(sata_error_addr);
382
383 writel(sata_error, sata_error_addr);
384 watchdog = (sata_error & 0x00680000) ? 1 : 0;
385 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
386 "watchdog = %d, %s\n",
387 drive->name, sata_error, watchdog, __func__);
388 } else
389 watchdog = (ext_stat & 0x8000) ? 1 : 0;
390
391 ext_stat >>= 16;
392 if (!(ext_stat & 0x0404) && !watchdog)
393 return 0;
394 }
395
396 /* return 1 if INTR asserted */
397 if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4)
398 return 1;
399
400 /* return 1 if Device INTR asserted */
401 if (readb((void __iomem *)addr) & 8)
402 return 0; /* return 1; */
403
404 return 0;
405 }
406
siimage_dma_test_irq(ide_drive_t * drive)407 static int siimage_dma_test_irq(ide_drive_t *drive)
408 {
409 if (drive->hwif->host_flags & IDE_HFLAG_MMIO)
410 return siimage_mmio_dma_test_irq(drive);
411 else
412 return siimage_io_dma_test_irq(drive);
413 }
414
415 /**
416 * sil_sata_reset_poll - wait for SATA reset
417 * @drive: drive we are resetting
418 *
419 * Poll the SATA phy and see whether it has come back from the dead
420 * yet.
421 */
422
sil_sata_reset_poll(ide_drive_t * drive)423 static int sil_sata_reset_poll(ide_drive_t *drive)
424 {
425 ide_hwif_t *hwif = drive->hwif;
426 void __iomem *sata_status_addr
427 = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
428
429 if (sata_status_addr) {
430 /* SATA Status is available only when in MMIO mode */
431 u32 sata_stat = readl(sata_status_addr);
432
433 if ((sata_stat & 0x03) != 0x03) {
434 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
435 hwif->name, sata_stat);
436 return -ENXIO;
437 }
438 }
439
440 return 0;
441 }
442
443 /**
444 * sil_sata_pre_reset - reset hook
445 * @drive: IDE device being reset
446 *
447 * For the SATA devices we need to handle recalibration/geometry
448 * differently
449 */
450
sil_sata_pre_reset(ide_drive_t * drive)451 static void sil_sata_pre_reset(ide_drive_t *drive)
452 {
453 if (drive->media == ide_disk) {
454 drive->special.b.set_geometry = 0;
455 drive->special.b.recalibrate = 0;
456 }
457 }
458
459 /**
460 * init_chipset_siimage - set up an SI device
461 * @dev: PCI device
462 *
463 * Perform the initial PCI set up for this device. Attempt to switch
464 * to 133 MHz clocking if the system isn't already set up to do it.
465 */
466
init_chipset_siimage(struct pci_dev * dev)467 static unsigned int init_chipset_siimage(struct pci_dev *dev)
468 {
469 struct ide_host *host = pci_get_drvdata(dev);
470 void __iomem *ioaddr = host->host_priv;
471 unsigned long base, scsc_addr;
472 u8 rev = dev->revision, tmp;
473
474 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
475
476 if (ioaddr)
477 pci_set_master(dev);
478
479 base = (unsigned long)ioaddr;
480
481 if (ioaddr && pdev_is_sata(dev)) {
482 u32 tmp32, irq_mask;
483
484 /* make sure IDE0/1 interrupts are not masked */
485 irq_mask = (1 << 22) | (1 << 23);
486 tmp32 = readl(ioaddr + 0x48);
487 if (tmp32 & irq_mask) {
488 tmp32 &= ~irq_mask;
489 writel(tmp32, ioaddr + 0x48);
490 readl(ioaddr + 0x48); /* flush */
491 }
492 writel(0, ioaddr + 0x148);
493 writel(0, ioaddr + 0x1C8);
494 }
495
496 sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
497 sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
498
499 scsc_addr = base ? (base + 0x4A) : 0x8A;
500 tmp = sil_ioread8(dev, scsc_addr);
501
502 switch (tmp & 0x30) {
503 case 0x00:
504 /* On 100 MHz clocking, try and switch to 133 MHz */
505 sil_iowrite8(dev, tmp | 0x10, scsc_addr);
506 break;
507 case 0x30:
508 /* Clocking is disabled, attempt to force 133MHz clocking. */
509 sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
510 case 0x10:
511 /* On 133Mhz clocking. */
512 break;
513 case 0x20:
514 /* On PCIx2 clocking. */
515 break;
516 }
517
518 tmp = sil_ioread8(dev, scsc_addr);
519
520 sil_iowrite8 (dev, 0x72, base + 0xA1);
521 sil_iowrite16(dev, 0x328A, base + 0xA2);
522 sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
523 sil_iowrite32(dev, 0x43924392, base + 0xA8);
524 sil_iowrite32(dev, 0x40094009, base + 0xAC);
525 sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
526 sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
527 sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
528 sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
529 sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
530
531 if (base && pdev_is_sata(dev)) {
532 writel(0xFFFF0000, ioaddr + 0x108);
533 writel(0xFFFF0000, ioaddr + 0x188);
534 writel(0x00680000, ioaddr + 0x148);
535 writel(0x00680000, ioaddr + 0x1C8);
536 }
537
538 /* report the clocking mode of the controller */
539 if (!pdev_is_sata(dev)) {
540 static const char *clk_str[] =
541 { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
542
543 tmp >>= 4;
544 printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n",
545 pci_name(dev), clk_str[tmp & 3]);
546 }
547
548 return 0;
549 }
550
551 /**
552 * init_mmio_iops_siimage - set up the iops for MMIO
553 * @hwif: interface to set up
554 *
555 * The basic setup here is fairly simple, we can use standard MMIO
556 * operations. However we do have to set the taskfile register offsets
557 * by hand as there isn't a standard defined layout for them this time.
558 *
559 * The hardware supports buffered taskfiles and also some rather nice
560 * extended PRD tables. For better SI3112 support use the libata driver
561 */
562
init_mmio_iops_siimage(ide_hwif_t * hwif)563 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
564 {
565 struct pci_dev *dev = to_pci_dev(hwif->dev);
566 struct ide_host *host = pci_get_drvdata(dev);
567 void *addr = host->host_priv;
568 u8 ch = hwif->channel;
569 struct ide_io_ports *io_ports = &hwif->io_ports;
570 unsigned long base;
571
572 /*
573 * Fill in the basic hwif bits
574 */
575 hwif->host_flags |= IDE_HFLAG_MMIO;
576
577 hwif->hwif_data = addr;
578
579 /*
580 * Now set up the hw. We have to do this ourselves as the
581 * MMIO layout isn't the same as the standard port based I/O.
582 */
583 memset(io_ports, 0, sizeof(*io_ports));
584
585 base = (unsigned long)addr;
586 if (ch)
587 base += 0xC0;
588 else
589 base += 0x80;
590
591 /*
592 * The buffered task file doesn't have status/control, so we
593 * can't currently use it sanely since we want to use LBA48 mode.
594 */
595 io_ports->data_addr = base;
596 io_ports->error_addr = base + 1;
597 io_ports->nsect_addr = base + 2;
598 io_ports->lbal_addr = base + 3;
599 io_ports->lbam_addr = base + 4;
600 io_ports->lbah_addr = base + 5;
601 io_ports->device_addr = base + 6;
602 io_ports->status_addr = base + 7;
603 io_ports->ctl_addr = base + 10;
604
605 if (pdev_is_sata(dev)) {
606 base = (unsigned long)addr;
607 if (ch)
608 base += 0x80;
609 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
610 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
611 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
612 }
613
614 hwif->irq = dev->irq;
615
616 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
617 }
618
is_dev_seagate_sata(ide_drive_t * drive)619 static int is_dev_seagate_sata(ide_drive_t *drive)
620 {
621 const char *s = (const char *)&drive->id[ATA_ID_PROD];
622 unsigned len = strnlen(s, ATA_ID_PROD_LEN);
623
624 if ((len > 4) && (!memcmp(s, "ST", 2)))
625 if ((!memcmp(s + len - 2, "AS", 2)) ||
626 (!memcmp(s + len - 3, "ASL", 3))) {
627 printk(KERN_INFO "%s: applying pessimistic Seagate "
628 "errata fix\n", drive->name);
629 return 1;
630 }
631
632 return 0;
633 }
634
635 /**
636 * sil_quirkproc - post probe fixups
637 * @drive: drive
638 *
639 * Called after drive probe we use this to decide whether the
640 * Seagate fixup must be applied. This used to be in init_iops but
641 * that can occur before we know what drives are present.
642 */
643
sil_quirkproc(ide_drive_t * drive)644 static void sil_quirkproc(ide_drive_t *drive)
645 {
646 ide_hwif_t *hwif = drive->hwif;
647
648 /* Try and rise the rqsize */
649 if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
650 hwif->rqsize = 128;
651 }
652
653 /**
654 * init_iops_siimage - set up iops
655 * @hwif: interface to set up
656 *
657 * Do the basic setup for the SIIMAGE hardware interface
658 * and then do the MMIO setup if we can. This is the first
659 * look in we get for setting up the hwif so that we
660 * can get the iops right before using them.
661 */
662
init_iops_siimage(ide_hwif_t * hwif)663 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
664 {
665 struct pci_dev *dev = to_pci_dev(hwif->dev);
666 struct ide_host *host = pci_get_drvdata(dev);
667
668 hwif->hwif_data = NULL;
669
670 /* Pessimal until we finish probing */
671 hwif->rqsize = 15;
672
673 if (host->host_priv)
674 init_mmio_iops_siimage(hwif);
675 }
676
677 /**
678 * sil_cable_detect - cable detection
679 * @hwif: interface to check
680 *
681 * Check for the presence of an ATA66 capable cable on the interface.
682 */
683
sil_cable_detect(ide_hwif_t * hwif)684 static u8 sil_cable_detect(ide_hwif_t *hwif)
685 {
686 struct pci_dev *dev = to_pci_dev(hwif->dev);
687 unsigned long addr = siimage_selreg(hwif, 0);
688 u8 ata66 = sil_ioread8(dev, addr);
689
690 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
691 }
692
693 static const struct ide_port_ops sil_pata_port_ops = {
694 .set_pio_mode = sil_set_pio_mode,
695 .set_dma_mode = sil_set_dma_mode,
696 .quirkproc = sil_quirkproc,
697 .udma_filter = sil_pata_udma_filter,
698 .cable_detect = sil_cable_detect,
699 };
700
701 static const struct ide_port_ops sil_sata_port_ops = {
702 .set_pio_mode = sil_set_pio_mode,
703 .set_dma_mode = sil_set_dma_mode,
704 .reset_poll = sil_sata_reset_poll,
705 .pre_reset = sil_sata_pre_reset,
706 .quirkproc = sil_quirkproc,
707 .udma_filter = sil_sata_udma_filter,
708 .cable_detect = sil_cable_detect,
709 };
710
711 static const struct ide_dma_ops sil_dma_ops = {
712 .dma_host_set = ide_dma_host_set,
713 .dma_setup = ide_dma_setup,
714 .dma_exec_cmd = ide_dma_exec_cmd,
715 .dma_start = ide_dma_start,
716 .dma_end = ide_dma_end,
717 .dma_test_irq = siimage_dma_test_irq,
718 .dma_timeout = ide_dma_timeout,
719 .dma_lost_irq = ide_dma_lost_irq,
720 .dma_sff_read_status = ide_dma_sff_read_status,
721 };
722
723 #define DECLARE_SII_DEV(p_ops) \
724 { \
725 .name = DRV_NAME, \
726 .init_chipset = init_chipset_siimage, \
727 .init_iops = init_iops_siimage, \
728 .port_ops = p_ops, \
729 .dma_ops = &sil_dma_ops, \
730 .pio_mask = ATA_PIO4, \
731 .mwdma_mask = ATA_MWDMA2, \
732 .udma_mask = ATA_UDMA6, \
733 }
734
735 static const struct ide_port_info siimage_chipsets[] __devinitdata = {
736 /* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops),
737 /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops)
738 };
739
740 /**
741 * siimage_init_one - PCI layer discovery entry
742 * @dev: PCI device
743 * @id: ident table entry
744 *
745 * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
746 * We then use the IDE PCI generic helper to do most of the work.
747 */
748
siimage_init_one(struct pci_dev * dev,const struct pci_device_id * id)749 static int __devinit siimage_init_one(struct pci_dev *dev,
750 const struct pci_device_id *id)
751 {
752 void __iomem *ioaddr = NULL;
753 resource_size_t bar5 = pci_resource_start(dev, 5);
754 unsigned long barsize = pci_resource_len(dev, 5);
755 int rc;
756 struct ide_port_info d;
757 u8 idx = id->driver_data;
758 u8 BA5_EN;
759
760 d = siimage_chipsets[idx];
761
762 if (idx) {
763 static int first = 1;
764
765 if (first) {
766 printk(KERN_INFO DRV_NAME ": For full SATA support you "
767 "should use the libata sata_sil module.\n");
768 first = 0;
769 }
770
771 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
772 }
773
774 rc = pci_enable_device(dev);
775 if (rc)
776 return rc;
777
778 pci_read_config_byte(dev, 0x8A, &BA5_EN);
779 if ((BA5_EN & 0x01) || bar5) {
780 /*
781 * Drop back to PIO if we can't map the MMIO. Some systems
782 * seem to get terminally confused in the PCI spaces.
783 */
784 if (!request_mem_region(bar5, barsize, d.name)) {
785 printk(KERN_WARNING DRV_NAME " %s: MMIO ports not "
786 "available\n", pci_name(dev));
787 } else {
788 ioaddr = pci_ioremap_bar(dev, 5);
789 if (ioaddr == NULL)
790 release_mem_region(bar5, barsize);
791 }
792 }
793
794 rc = ide_pci_init_one(dev, &d, ioaddr);
795 if (rc) {
796 if (ioaddr) {
797 iounmap(ioaddr);
798 release_mem_region(bar5, barsize);
799 }
800 pci_disable_device(dev);
801 }
802
803 return rc;
804 }
805
siimage_remove(struct pci_dev * dev)806 static void __devexit siimage_remove(struct pci_dev *dev)
807 {
808 struct ide_host *host = pci_get_drvdata(dev);
809 void __iomem *ioaddr = host->host_priv;
810
811 ide_pci_remove(dev);
812
813 if (ioaddr) {
814 resource_size_t bar5 = pci_resource_start(dev, 5);
815 unsigned long barsize = pci_resource_len(dev, 5);
816
817 iounmap(ioaddr);
818 release_mem_region(bar5, barsize);
819 }
820
821 pci_disable_device(dev);
822 }
823
824 static const struct pci_device_id siimage_pci_tbl[] = {
825 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
826 #ifdef CONFIG_BLK_DEV_IDE_SATA
827 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
828 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 },
829 #endif
830 { 0, },
831 };
832 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
833
834 static struct pci_driver siimage_pci_driver = {
835 .name = "SiI_IDE",
836 .id_table = siimage_pci_tbl,
837 .probe = siimage_init_one,
838 .remove = __devexit_p(siimage_remove),
839 .suspend = ide_pci_suspend,
840 .resume = ide_pci_resume,
841 };
842
siimage_ide_init(void)843 static int __init siimage_ide_init(void)
844 {
845 return ide_pci_register_driver(&siimage_pci_driver);
846 }
847
siimage_ide_exit(void)848 static void __exit siimage_ide_exit(void)
849 {
850 pci_unregister_driver(&siimage_pci_driver);
851 }
852
853 module_init(siimage_ide_init);
854 module_exit(siimage_ide_exit);
855
856 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
857 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
858 MODULE_LICENSE("GPL");
859