1 /*
2 * Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
3 *
4 * Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
20 */
21
22 /* In that file, frequencies are expressed in kiloHertz to avoid 32 bits overflows */
23
24 #include <linux/module.h>
25 #include <linux/delay.h>
26 #include <linux/dvb/frontend.h>
27 #include <linux/i2c.h>
28
29 #include "dvb_frontend.h"
30
31 #include "mt2060.h"
32 #include "mt2060_priv.h"
33
34 static int debug;
35 module_param(debug, int, 0644);
36 MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
37
38 #define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "MT2060: " args); printk("\n"); }} while (0)
39
40 // Reads a single register
mt2060_readreg(struct mt2060_priv * priv,u8 reg,u8 * val)41 static int mt2060_readreg(struct mt2060_priv *priv, u8 reg, u8 *val)
42 {
43 struct i2c_msg msg[2] = {
44 { .addr = priv->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 },
45 { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val, .len = 1 },
46 };
47
48 if (i2c_transfer(priv->i2c, msg, 2) != 2) {
49 printk(KERN_WARNING "mt2060 I2C read failed\n");
50 return -EREMOTEIO;
51 }
52 return 0;
53 }
54
55 // Writes a single register
mt2060_writereg(struct mt2060_priv * priv,u8 reg,u8 val)56 static int mt2060_writereg(struct mt2060_priv *priv, u8 reg, u8 val)
57 {
58 u8 buf[2] = { reg, val };
59 struct i2c_msg msg = {
60 .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2
61 };
62
63 if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
64 printk(KERN_WARNING "mt2060 I2C write failed\n");
65 return -EREMOTEIO;
66 }
67 return 0;
68 }
69
70 // Writes a set of consecutive registers
mt2060_writeregs(struct mt2060_priv * priv,u8 * buf,u8 len)71 static int mt2060_writeregs(struct mt2060_priv *priv,u8 *buf, u8 len)
72 {
73 struct i2c_msg msg = {
74 .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = len
75 };
76 if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
77 printk(KERN_WARNING "mt2060 I2C write failed (len=%i)\n",(int)len);
78 return -EREMOTEIO;
79 }
80 return 0;
81 }
82
83 // Initialisation sequences
84 // LNABAND=3, NUM1=0x3C, DIV1=0x74, NUM2=0x1080, DIV2=0x49
85 static u8 mt2060_config1[] = {
86 REG_LO1C1,
87 0x3F, 0x74, 0x00, 0x08, 0x93
88 };
89
90 // FMCG=2, GP2=0, GP1=0
91 static u8 mt2060_config2[] = {
92 REG_MISC_CTRL,
93 0x20, 0x1E, 0x30, 0xff, 0x80, 0xff, 0x00, 0x2c, 0x42
94 };
95
96 // VGAG=3, V1CSE=1
97
98 #ifdef MT2060_SPURCHECK
99 /* The function below calculates the frequency offset between the output frequency if2
100 and the closer cross modulation subcarrier between lo1 and lo2 up to the tenth harmonic */
mt2060_spurcalc(u32 lo1,u32 lo2,u32 if2)101 static int mt2060_spurcalc(u32 lo1,u32 lo2,u32 if2)
102 {
103 int I,J;
104 int dia,diamin,diff;
105 diamin=1000000;
106 for (I = 1; I < 10; I++) {
107 J = ((2*I*lo1)/lo2+1)/2;
108 diff = I*(int)lo1-J*(int)lo2;
109 if (diff < 0) diff=-diff;
110 dia = (diff-(int)if2);
111 if (dia < 0) dia=-dia;
112 if (diamin > dia) diamin=dia;
113 }
114 return diamin;
115 }
116
117 #define BANDWIDTH 4000 // kHz
118
119 /* Calculates the frequency offset to add to avoid spurs. Returns 0 if no offset is needed */
mt2060_spurcheck(u32 lo1,u32 lo2,u32 if2)120 static int mt2060_spurcheck(u32 lo1,u32 lo2,u32 if2)
121 {
122 u32 Spur,Sp1,Sp2;
123 int I,J;
124 I=0;
125 J=1000;
126
127 Spur=mt2060_spurcalc(lo1,lo2,if2);
128 if (Spur < BANDWIDTH) {
129 /* Potential spurs detected */
130 dprintk("Spurs before : f_lo1: %d f_lo2: %d (kHz)",
131 (int)lo1,(int)lo2);
132 I=1000;
133 Sp1 = mt2060_spurcalc(lo1+I,lo2+I,if2);
134 Sp2 = mt2060_spurcalc(lo1-I,lo2-I,if2);
135
136 if (Sp1 < Sp2) {
137 J=-J; I=-I; Spur=Sp2;
138 } else
139 Spur=Sp1;
140
141 while (Spur < BANDWIDTH) {
142 I += J;
143 Spur = mt2060_spurcalc(lo1+I,lo2+I,if2);
144 }
145 dprintk("Spurs after : f_lo1: %d f_lo2: %d (kHz)",
146 (int)(lo1+I),(int)(lo2+I));
147 }
148 return I;
149 }
150 #endif
151
152 #define IF2 36150 // IF2 frequency = 36.150 MHz
153 #define FREF 16000 // Quartz oscillator 16 MHz
154
mt2060_set_params(struct dvb_frontend * fe,struct dvb_frontend_parameters * params)155 static int mt2060_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
156 {
157 struct mt2060_priv *priv;
158 int ret=0;
159 int i=0;
160 u32 freq;
161 u8 lnaband;
162 u32 f_lo1,f_lo2;
163 u32 div1,num1,div2,num2;
164 u8 b[8];
165 u32 if1;
166
167 priv = fe->tuner_priv;
168
169 if1 = priv->if1_freq;
170 b[0] = REG_LO1B1;
171 b[1] = 0xFF;
172
173 if (fe->ops.i2c_gate_ctrl)
174 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
175
176 mt2060_writeregs(priv,b,2);
177
178 freq = params->frequency / 1000; // Hz -> kHz
179 priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0;
180
181 f_lo1 = freq + if1 * 1000;
182 f_lo1 = (f_lo1 / 250) * 250;
183 f_lo2 = f_lo1 - freq - IF2;
184 // From the Comtech datasheet, the step used is 50kHz. The tuner chip could be more precise
185 f_lo2 = ((f_lo2 + 25) / 50) * 50;
186 priv->frequency = (f_lo1 - f_lo2 - IF2) * 1000,
187
188 #ifdef MT2060_SPURCHECK
189 // LO-related spurs detection and correction
190 num1 = mt2060_spurcheck(f_lo1,f_lo2,IF2);
191 f_lo1 += num1;
192 f_lo2 += num1;
193 #endif
194 //Frequency LO1 = 16MHz * (DIV1 + NUM1/64 )
195 num1 = f_lo1 / (FREF / 64);
196 div1 = num1 / 64;
197 num1 &= 0x3f;
198
199 // Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 )
200 num2 = f_lo2 * 64 / (FREF / 128);
201 div2 = num2 / 8192;
202 num2 &= 0x1fff;
203
204 if (freq <= 95000) lnaband = 0xB0; else
205 if (freq <= 180000) lnaband = 0xA0; else
206 if (freq <= 260000) lnaband = 0x90; else
207 if (freq <= 335000) lnaband = 0x80; else
208 if (freq <= 425000) lnaband = 0x70; else
209 if (freq <= 480000) lnaband = 0x60; else
210 if (freq <= 570000) lnaband = 0x50; else
211 if (freq <= 645000) lnaband = 0x40; else
212 if (freq <= 730000) lnaband = 0x30; else
213 if (freq <= 810000) lnaband = 0x20; else lnaband = 0x10;
214
215 b[0] = REG_LO1C1;
216 b[1] = lnaband | ((num1 >>2) & 0x0F);
217 b[2] = div1;
218 b[3] = (num2 & 0x0F) | ((num1 & 3) << 4);
219 b[4] = num2 >> 4;
220 b[5] = ((num2 >>12) & 1) | (div2 << 1);
221
222 dprintk("IF1: %dMHz",(int)if1);
223 dprintk("PLL freq=%dkHz f_lo1=%dkHz f_lo2=%dkHz",(int)freq,(int)f_lo1,(int)f_lo2);
224 dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2);
225 dprintk("PLL [1..5]: %2x %2x %2x %2x %2x",(int)b[1],(int)b[2],(int)b[3],(int)b[4],(int)b[5]);
226
227 mt2060_writeregs(priv,b,6);
228
229 //Waits for pll lock or timeout
230 i = 0;
231 do {
232 mt2060_readreg(priv,REG_LO_STATUS,b);
233 if ((b[0] & 0x88)==0x88)
234 break;
235 msleep(4);
236 i++;
237 } while (i<10);
238
239 if (fe->ops.i2c_gate_ctrl)
240 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
241
242 return ret;
243 }
244
mt2060_calibrate(struct mt2060_priv * priv)245 static void mt2060_calibrate(struct mt2060_priv *priv)
246 {
247 u8 b = 0;
248 int i = 0;
249
250 if (mt2060_writeregs(priv,mt2060_config1,sizeof(mt2060_config1)))
251 return;
252 if (mt2060_writeregs(priv,mt2060_config2,sizeof(mt2060_config2)))
253 return;
254
255 /* initialize the clock output */
256 mt2060_writereg(priv, REG_VGAG, (priv->cfg->clock_out << 6) | 0x30);
257
258 do {
259 b |= (1 << 6); // FM1SS;
260 mt2060_writereg(priv, REG_LO2C1,b);
261 msleep(20);
262
263 if (i == 0) {
264 b |= (1 << 7); // FM1CA;
265 mt2060_writereg(priv, REG_LO2C1,b);
266 b &= ~(1 << 7); // FM1CA;
267 msleep(20);
268 }
269
270 b &= ~(1 << 6); // FM1SS
271 mt2060_writereg(priv, REG_LO2C1,b);
272
273 msleep(20);
274 i++;
275 } while (i < 9);
276
277 i = 0;
278 while (i++ < 10 && mt2060_readreg(priv, REG_MISC_STAT, &b) == 0 && (b & (1 << 6)) == 0)
279 msleep(20);
280
281 if (i < 10) {
282 mt2060_readreg(priv, REG_FM_FREQ, &priv->fmfreq); // now find out, what is fmreq used for :)
283 dprintk("calibration was successful: %d", (int)priv->fmfreq);
284 } else
285 dprintk("FMCAL timed out");
286 }
287
mt2060_get_frequency(struct dvb_frontend * fe,u32 * frequency)288 static int mt2060_get_frequency(struct dvb_frontend *fe, u32 *frequency)
289 {
290 struct mt2060_priv *priv = fe->tuner_priv;
291 *frequency = priv->frequency;
292 return 0;
293 }
294
mt2060_get_bandwidth(struct dvb_frontend * fe,u32 * bandwidth)295 static int mt2060_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
296 {
297 struct mt2060_priv *priv = fe->tuner_priv;
298 *bandwidth = priv->bandwidth;
299 return 0;
300 }
301
mt2060_init(struct dvb_frontend * fe)302 static int mt2060_init(struct dvb_frontend *fe)
303 {
304 struct mt2060_priv *priv = fe->tuner_priv;
305 int ret;
306
307 if (fe->ops.i2c_gate_ctrl)
308 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
309
310 ret = mt2060_writereg(priv, REG_VGAG,
311 (priv->cfg->clock_out << 6) | 0x33);
312
313 if (fe->ops.i2c_gate_ctrl)
314 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
315
316 return ret;
317 }
318
mt2060_sleep(struct dvb_frontend * fe)319 static int mt2060_sleep(struct dvb_frontend *fe)
320 {
321 struct mt2060_priv *priv = fe->tuner_priv;
322 int ret;
323
324 if (fe->ops.i2c_gate_ctrl)
325 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
326
327 ret = mt2060_writereg(priv, REG_VGAG,
328 (priv->cfg->clock_out << 6) | 0x30);
329
330 if (fe->ops.i2c_gate_ctrl)
331 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
332
333 return ret;
334 }
335
mt2060_release(struct dvb_frontend * fe)336 static int mt2060_release(struct dvb_frontend *fe)
337 {
338 kfree(fe->tuner_priv);
339 fe->tuner_priv = NULL;
340 return 0;
341 }
342
343 static const struct dvb_tuner_ops mt2060_tuner_ops = {
344 .info = {
345 .name = "Microtune MT2060",
346 .frequency_min = 48000000,
347 .frequency_max = 860000000,
348 .frequency_step = 50000,
349 },
350
351 .release = mt2060_release,
352
353 .init = mt2060_init,
354 .sleep = mt2060_sleep,
355
356 .set_params = mt2060_set_params,
357 .get_frequency = mt2060_get_frequency,
358 .get_bandwidth = mt2060_get_bandwidth
359 };
360
361 /* This functions tries to identify a MT2060 tuner by reading the PART/REV register. This is hasty. */
mt2060_attach(struct dvb_frontend * fe,struct i2c_adapter * i2c,struct mt2060_config * cfg,u16 if1)362 struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1)
363 {
364 struct mt2060_priv *priv = NULL;
365 u8 id = 0;
366
367 priv = kzalloc(sizeof(struct mt2060_priv), GFP_KERNEL);
368 if (priv == NULL)
369 return NULL;
370
371 priv->cfg = cfg;
372 priv->i2c = i2c;
373 priv->if1_freq = if1;
374
375 if (fe->ops.i2c_gate_ctrl)
376 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
377
378 if (mt2060_readreg(priv,REG_PART_REV,&id) != 0) {
379 kfree(priv);
380 return NULL;
381 }
382
383 if (id != PART_REV) {
384 kfree(priv);
385 return NULL;
386 }
387 printk(KERN_INFO "MT2060: successfully identified (IF1 = %d)\n", if1);
388 memcpy(&fe->ops.tuner_ops, &mt2060_tuner_ops, sizeof(struct dvb_tuner_ops));
389
390 fe->tuner_priv = priv;
391
392 mt2060_calibrate(priv);
393
394 if (fe->ops.i2c_gate_ctrl)
395 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
396
397 return fe;
398 }
399 EXPORT_SYMBOL(mt2060_attach);
400
401 MODULE_AUTHOR("Olivier DANET");
402 MODULE_DESCRIPTION("Microtune MT2060 silicon tuner driver");
403 MODULE_LICENSE("GPL");
404