1 /*
2 * cx18 ADEC firmware functions
3 *
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
5 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA.
21 */
22
23 #include "cx18-driver.h"
24 #include "cx18-io.h"
25 #include <linux/firmware.h>
26
27 #define CX18_AUDIO_ENABLE 0xc72014
28 #define FWFILE "v4l-cx23418-dig.fw"
29
cx18_av_loadfw(struct cx18 * cx)30 int cx18_av_loadfw(struct cx18 *cx)
31 {
32 const struct firmware *fw = NULL;
33 u32 size;
34 u32 v;
35 const u8 *ptr;
36 int i;
37 int retries1 = 0;
38
39 if (request_firmware(&fw, FWFILE, &cx->dev->dev) != 0) {
40 CX18_ERR("unable to open firmware %s\n", FWFILE);
41 return -EINVAL;
42 }
43
44 /* The firmware load often has byte errors, so allow for several
45 retries, both at byte level and at the firmware load level. */
46 while (retries1 < 5) {
47 cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000,
48 0x00008430, 0xffffffff); /* cx25843 */
49 cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff);
50
51 /* Reset the Mako core, Register is alias of CXADEC_CHIP_CTRL */
52 cx18_av_write4_expect(cx, 0x8100, 0x00010000,
53 0x00008430, 0xffffffff); /* cx25843 */
54
55 /* Put the 8051 in reset and enable firmware upload */
56 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
57
58 ptr = fw->data;
59 size = fw->size;
60
61 for (i = 0; i < size; i++) {
62 u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
63 u32 value = 0;
64 int retries2;
65 int unrec_err = 0;
66
67 for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES;
68 retries2++) {
69 cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
70 dl_control);
71 udelay(10);
72 value = cx18_av_read4(cx, CXADEC_DL_CTL);
73 if (value == dl_control)
74 break;
75 /* Check if we can correct the byte by changing
76 the address. We can only write the lower
77 address byte of the address. */
78 if ((value & 0x3F00) != (dl_control & 0x3F00)) {
79 unrec_err = 1;
80 break;
81 }
82 }
83 if (unrec_err || retries2 >= CX18_MAX_MMIO_WR_RETRIES)
84 break;
85 }
86 if (i == size)
87 break;
88 retries1++;
89 }
90 if (retries1 >= 5) {
91 CX18_ERR("unable to load firmware %s\n", FWFILE);
92 release_firmware(fw);
93 return -EIO;
94 }
95
96 cx18_av_write4_expect(cx, CXADEC_DL_CTL,
97 0x13000000 | fw->size, 0x13000000, 0x13000000);
98
99 /* Output to the 416 */
100 cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000);
101
102 /* Audio input control 1 set to Sony mode */
103 /* Audio output input 2 is 0 for slave operation input */
104 /* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
105 /* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
106 after WS transition for first bit of audio word. */
107 cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0);
108
109 /* Audio output control 1 is set to Sony mode */
110 /* Audio output control 2 is set to 1 for master mode */
111 /* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
112 /* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
113 after WS transition for first bit of audio word. */
114 /* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT
115 are generated) */
116 cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
117
118 /* set alt I2s master clock to /16 and enable alt divider i2s
119 passthrough */
120 cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5000B687);
121
122 cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
123 0x3F00FFFF);
124 /* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */
125
126 /* Set bit 0 in register 0x9CC to signify that this is MiniMe. */
127 /* Register 0x09CC is defined by the Merlin firmware, and doesn't
128 have a name in the spec. */
129 cx18_av_write4(cx, 0x09CC, 1);
130
131 v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
132 /* If bit 11 is 1, clear bit 10 */
133 if (v & 0x800)
134 cx18_write_reg(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE);
135
136 /* Enable WW auto audio standard detection */
137 v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
138 v |= 0xFF; /* Auto by default */
139 v |= 0x400; /* Stereo by default */
140 v |= 0x14000000;
141 cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF);
142
143 release_firmware(fw);
144
145 CX18_INFO("loaded %s firmware (%d bytes)\n", FWFILE, size);
146 return 0;
147 }
148