1 /*
2 * drivers/mtd/nand/au1550nd.c
3 *
4 * Copyright (C) 2004 Embedded Edge, LLC
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/slab.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/partitions.h>
19 #include <asm/io.h>
20
21 #include <asm/mach-au1x00/au1xxx.h>
22
23 /*
24 * MTD structure for NAND controller
25 */
26 static struct mtd_info *au1550_mtd = NULL;
27 static void __iomem *p_nand;
28 static int nand_width = 1; /* default x8 */
29 static void (*au1550_write_byte)(struct mtd_info *, u_char);
30
31 /*
32 * Define partitions for flash device
33 */
34 static const struct mtd_partition partition_info[] = {
35 {
36 .name = "NAND FS 0",
37 .offset = 0,
38 .size = 8 * 1024 * 1024},
39 {
40 .name = "NAND FS 1",
41 .offset = MTDPART_OFS_APPEND,
42 .size = MTDPART_SIZ_FULL}
43 };
44
45 /**
46 * au_read_byte - read one byte from the chip
47 * @mtd: MTD device structure
48 *
49 * read function for 8bit buswith
50 */
au_read_byte(struct mtd_info * mtd)51 static u_char au_read_byte(struct mtd_info *mtd)
52 {
53 struct nand_chip *this = mtd->priv;
54 u_char ret = readb(this->IO_ADDR_R);
55 au_sync();
56 return ret;
57 }
58
59 /**
60 * au_write_byte - write one byte to the chip
61 * @mtd: MTD device structure
62 * @byte: pointer to data byte to write
63 *
64 * write function for 8it buswith
65 */
au_write_byte(struct mtd_info * mtd,u_char byte)66 static void au_write_byte(struct mtd_info *mtd, u_char byte)
67 {
68 struct nand_chip *this = mtd->priv;
69 writeb(byte, this->IO_ADDR_W);
70 au_sync();
71 }
72
73 /**
74 * au_read_byte16 - read one byte endianess aware from the chip
75 * @mtd: MTD device structure
76 *
77 * read function for 16bit buswith with
78 * endianess conversion
79 */
au_read_byte16(struct mtd_info * mtd)80 static u_char au_read_byte16(struct mtd_info *mtd)
81 {
82 struct nand_chip *this = mtd->priv;
83 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
84 au_sync();
85 return ret;
86 }
87
88 /**
89 * au_write_byte16 - write one byte endianess aware to the chip
90 * @mtd: MTD device structure
91 * @byte: pointer to data byte to write
92 *
93 * write function for 16bit buswith with
94 * endianess conversion
95 */
au_write_byte16(struct mtd_info * mtd,u_char byte)96 static void au_write_byte16(struct mtd_info *mtd, u_char byte)
97 {
98 struct nand_chip *this = mtd->priv;
99 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
100 au_sync();
101 }
102
103 /**
104 * au_read_word - read one word from the chip
105 * @mtd: MTD device structure
106 *
107 * read function for 16bit buswith without
108 * endianess conversion
109 */
au_read_word(struct mtd_info * mtd)110 static u16 au_read_word(struct mtd_info *mtd)
111 {
112 struct nand_chip *this = mtd->priv;
113 u16 ret = readw(this->IO_ADDR_R);
114 au_sync();
115 return ret;
116 }
117
118 /**
119 * au_write_buf - write buffer to chip
120 * @mtd: MTD device structure
121 * @buf: data buffer
122 * @len: number of bytes to write
123 *
124 * write function for 8bit buswith
125 */
au_write_buf(struct mtd_info * mtd,const u_char * buf,int len)126 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
127 {
128 int i;
129 struct nand_chip *this = mtd->priv;
130
131 for (i = 0; i < len; i++) {
132 writeb(buf[i], this->IO_ADDR_W);
133 au_sync();
134 }
135 }
136
137 /**
138 * au_read_buf - read chip data into buffer
139 * @mtd: MTD device structure
140 * @buf: buffer to store date
141 * @len: number of bytes to read
142 *
143 * read function for 8bit buswith
144 */
au_read_buf(struct mtd_info * mtd,u_char * buf,int len)145 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
146 {
147 int i;
148 struct nand_chip *this = mtd->priv;
149
150 for (i = 0; i < len; i++) {
151 buf[i] = readb(this->IO_ADDR_R);
152 au_sync();
153 }
154 }
155
156 /**
157 * au_verify_buf - Verify chip data against buffer
158 * @mtd: MTD device structure
159 * @buf: buffer containing the data to compare
160 * @len: number of bytes to compare
161 *
162 * verify function for 8bit buswith
163 */
au_verify_buf(struct mtd_info * mtd,const u_char * buf,int len)164 static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
165 {
166 int i;
167 struct nand_chip *this = mtd->priv;
168
169 for (i = 0; i < len; i++) {
170 if (buf[i] != readb(this->IO_ADDR_R))
171 return -EFAULT;
172 au_sync();
173 }
174
175 return 0;
176 }
177
178 /**
179 * au_write_buf16 - write buffer to chip
180 * @mtd: MTD device structure
181 * @buf: data buffer
182 * @len: number of bytes to write
183 *
184 * write function for 16bit buswith
185 */
au_write_buf16(struct mtd_info * mtd,const u_char * buf,int len)186 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
187 {
188 int i;
189 struct nand_chip *this = mtd->priv;
190 u16 *p = (u16 *) buf;
191 len >>= 1;
192
193 for (i = 0; i < len; i++) {
194 writew(p[i], this->IO_ADDR_W);
195 au_sync();
196 }
197
198 }
199
200 /**
201 * au_read_buf16 - read chip data into buffer
202 * @mtd: MTD device structure
203 * @buf: buffer to store date
204 * @len: number of bytes to read
205 *
206 * read function for 16bit buswith
207 */
au_read_buf16(struct mtd_info * mtd,u_char * buf,int len)208 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
209 {
210 int i;
211 struct nand_chip *this = mtd->priv;
212 u16 *p = (u16 *) buf;
213 len >>= 1;
214
215 for (i = 0; i < len; i++) {
216 p[i] = readw(this->IO_ADDR_R);
217 au_sync();
218 }
219 }
220
221 /**
222 * au_verify_buf16 - Verify chip data against buffer
223 * @mtd: MTD device structure
224 * @buf: buffer containing the data to compare
225 * @len: number of bytes to compare
226 *
227 * verify function for 16bit buswith
228 */
au_verify_buf16(struct mtd_info * mtd,const u_char * buf,int len)229 static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
230 {
231 int i;
232 struct nand_chip *this = mtd->priv;
233 u16 *p = (u16 *) buf;
234 len >>= 1;
235
236 for (i = 0; i < len; i++) {
237 if (p[i] != readw(this->IO_ADDR_R))
238 return -EFAULT;
239 au_sync();
240 }
241 return 0;
242 }
243
244 /* Select the chip by setting nCE to low */
245 #define NAND_CTL_SETNCE 1
246 /* Deselect the chip by setting nCE to high */
247 #define NAND_CTL_CLRNCE 2
248 /* Select the command latch by setting CLE to high */
249 #define NAND_CTL_SETCLE 3
250 /* Deselect the command latch by setting CLE to low */
251 #define NAND_CTL_CLRCLE 4
252 /* Select the address latch by setting ALE to high */
253 #define NAND_CTL_SETALE 5
254 /* Deselect the address latch by setting ALE to low */
255 #define NAND_CTL_CLRALE 6
256
au1550_hwcontrol(struct mtd_info * mtd,int cmd)257 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
258 {
259 register struct nand_chip *this = mtd->priv;
260
261 switch (cmd) {
262
263 case NAND_CTL_SETCLE:
264 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
265 break;
266
267 case NAND_CTL_CLRCLE:
268 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
269 break;
270
271 case NAND_CTL_SETALE:
272 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
273 break;
274
275 case NAND_CTL_CLRALE:
276 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
277 /* FIXME: Nobody knows why this is necessary,
278 * but it works only that way */
279 udelay(1);
280 break;
281
282 case NAND_CTL_SETNCE:
283 /* assert (force assert) chip enable */
284 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
285 break;
286
287 case NAND_CTL_CLRNCE:
288 /* deassert chip enable */
289 au_writel(0, MEM_STNDCTL);
290 break;
291 }
292
293 this->IO_ADDR_R = this->IO_ADDR_W;
294
295 /* Drain the writebuffer */
296 au_sync();
297 }
298
au1550_device_ready(struct mtd_info * mtd)299 int au1550_device_ready(struct mtd_info *mtd)
300 {
301 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
302 au_sync();
303 return ret;
304 }
305
306 /**
307 * au1550_select_chip - control -CE line
308 * Forbid driving -CE manually permitting the NAND controller to do this.
309 * Keeping -CE asserted during the whole sector reads interferes with the
310 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
311 * We only have to hold -CE low for the NAND read commands since the flash
312 * chip needs it to be asserted during chip not ready time but the NAND
313 * controller keeps it released.
314 *
315 * @mtd: MTD device structure
316 * @chip: chipnumber to select, -1 for deselect
317 */
au1550_select_chip(struct mtd_info * mtd,int chip)318 static void au1550_select_chip(struct mtd_info *mtd, int chip)
319 {
320 }
321
322 /**
323 * au1550_command - Send command to NAND device
324 * @mtd: MTD device structure
325 * @command: the command to be sent
326 * @column: the column address for this command, -1 if none
327 * @page_addr: the page address for this command, -1 if none
328 */
au1550_command(struct mtd_info * mtd,unsigned command,int column,int page_addr)329 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
330 {
331 register struct nand_chip *this = mtd->priv;
332 int ce_override = 0, i;
333 ulong flags;
334
335 /* Begin command latch cycle */
336 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
337 /*
338 * Write out the command to the device.
339 */
340 if (command == NAND_CMD_SEQIN) {
341 int readcmd;
342
343 if (column >= mtd->writesize) {
344 /* OOB area */
345 column -= mtd->writesize;
346 readcmd = NAND_CMD_READOOB;
347 } else if (column < 256) {
348 /* First 256 bytes --> READ0 */
349 readcmd = NAND_CMD_READ0;
350 } else {
351 column -= 256;
352 readcmd = NAND_CMD_READ1;
353 }
354 au1550_write_byte(mtd, readcmd);
355 }
356 au1550_write_byte(mtd, command);
357
358 /* Set ALE and clear CLE to start address cycle */
359 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
360
361 if (column != -1 || page_addr != -1) {
362 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
363
364 /* Serially input address */
365 if (column != -1) {
366 /* Adjust columns for 16 bit buswidth */
367 if (this->options & NAND_BUSWIDTH_16)
368 column >>= 1;
369 au1550_write_byte(mtd, column);
370 }
371 if (page_addr != -1) {
372 au1550_write_byte(mtd, (u8)(page_addr & 0xff));
373
374 if (command == NAND_CMD_READ0 ||
375 command == NAND_CMD_READ1 ||
376 command == NAND_CMD_READOOB) {
377 /*
378 * NAND controller will release -CE after
379 * the last address byte is written, so we'll
380 * have to forcibly assert it. No interrupts
381 * are allowed while we do this as we don't
382 * want the NOR flash or PCMCIA drivers to
383 * steal our precious bytes of data...
384 */
385 ce_override = 1;
386 local_irq_save(flags);
387 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
388 }
389
390 au1550_write_byte(mtd, (u8)(page_addr >> 8));
391
392 /* One more address cycle for devices > 32MiB */
393 if (this->chipsize > (32 << 20))
394 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
395 }
396 /* Latch in address */
397 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
398 }
399
400 /*
401 * Program and erase have their own busy handlers.
402 * Status and sequential in need no delay.
403 */
404 switch (command) {
405
406 case NAND_CMD_PAGEPROG:
407 case NAND_CMD_ERASE1:
408 case NAND_CMD_ERASE2:
409 case NAND_CMD_SEQIN:
410 case NAND_CMD_STATUS:
411 return;
412
413 case NAND_CMD_RESET:
414 break;
415
416 case NAND_CMD_READ0:
417 case NAND_CMD_READ1:
418 case NAND_CMD_READOOB:
419 /* Check if we're really driving -CE low (just in case) */
420 if (unlikely(!ce_override))
421 break;
422
423 /* Apply a short delay always to ensure that we do wait tWB. */
424 ndelay(100);
425 /* Wait for a chip to become ready... */
426 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
427 udelay(1);
428
429 /* Release -CE and re-enable interrupts. */
430 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
431 local_irq_restore(flags);
432 return;
433 }
434 /* Apply this short delay always to ensure that we do wait tWB. */
435 ndelay(100);
436
437 while(!this->dev_ready(mtd));
438 }
439
440
441 /*
442 * Main initialization routine
443 */
au1xxx_nand_init(void)444 static int __init au1xxx_nand_init(void)
445 {
446 struct nand_chip *this;
447 u16 boot_swapboot = 0; /* default value */
448 int retval;
449 u32 mem_staddr;
450 u32 nand_phys;
451
452 /* Allocate memory for MTD device structure and private data */
453 au1550_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
454 if (!au1550_mtd) {
455 printk("Unable to allocate NAND MTD dev structure.\n");
456 return -ENOMEM;
457 }
458
459 /* Get pointer to private data */
460 this = (struct nand_chip *)(&au1550_mtd[1]);
461
462 /* Initialize structures */
463 memset(au1550_mtd, 0, sizeof(struct mtd_info));
464 memset(this, 0, sizeof(struct nand_chip));
465
466 /* Link the private data with the MTD structure */
467 au1550_mtd->priv = this;
468 au1550_mtd->owner = THIS_MODULE;
469
470
471 /* MEM_STNDCTL: disable ints, disable nand boot */
472 au_writel(0, MEM_STNDCTL);
473
474 #ifdef CONFIG_MIPS_PB1550
475 /* set gpio206 high */
476 au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
477
478 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1);
479 switch (boot_swapboot) {
480 case 0:
481 case 2:
482 case 8:
483 case 0xC:
484 case 0xD:
485 /* x16 NAND Flash */
486 nand_width = 0;
487 break;
488 case 1:
489 case 9:
490 case 3:
491 case 0xE:
492 case 0xF:
493 /* x8 NAND Flash */
494 nand_width = 1;
495 break;
496 default:
497 printk("Pb1550 NAND: bad boot:swap\n");
498 retval = -EINVAL;
499 goto outmem;
500 }
501 #endif
502
503 /* Configure chip-select; normally done by boot code, e.g. YAMON */
504 #ifdef NAND_STCFG
505 if (NAND_CS == 0) {
506 au_writel(NAND_STCFG, MEM_STCFG0);
507 au_writel(NAND_STTIME, MEM_STTIME0);
508 au_writel(NAND_STADDR, MEM_STADDR0);
509 }
510 if (NAND_CS == 1) {
511 au_writel(NAND_STCFG, MEM_STCFG1);
512 au_writel(NAND_STTIME, MEM_STTIME1);
513 au_writel(NAND_STADDR, MEM_STADDR1);
514 }
515 if (NAND_CS == 2) {
516 au_writel(NAND_STCFG, MEM_STCFG2);
517 au_writel(NAND_STTIME, MEM_STTIME2);
518 au_writel(NAND_STADDR, MEM_STADDR2);
519 }
520 if (NAND_CS == 3) {
521 au_writel(NAND_STCFG, MEM_STCFG3);
522 au_writel(NAND_STTIME, MEM_STTIME3);
523 au_writel(NAND_STADDR, MEM_STADDR3);
524 }
525 #endif
526
527 /* Locate NAND chip-select in order to determine NAND phys address */
528 mem_staddr = 0x00000000;
529 if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
530 mem_staddr = au_readl(MEM_STADDR0);
531 else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
532 mem_staddr = au_readl(MEM_STADDR1);
533 else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
534 mem_staddr = au_readl(MEM_STADDR2);
535 else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
536 mem_staddr = au_readl(MEM_STADDR3);
537
538 if (mem_staddr == 0x00000000) {
539 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
540 kfree(au1550_mtd);
541 return 1;
542 }
543 nand_phys = (mem_staddr << 4) & 0xFFFC0000;
544
545 p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
546
547 /* make controller and MTD agree */
548 if (NAND_CS == 0)
549 nand_width = au_readl(MEM_STCFG0) & (1 << 22);
550 if (NAND_CS == 1)
551 nand_width = au_readl(MEM_STCFG1) & (1 << 22);
552 if (NAND_CS == 2)
553 nand_width = au_readl(MEM_STCFG2) & (1 << 22);
554 if (NAND_CS == 3)
555 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
556
557 /* Set address of hardware control function */
558 this->dev_ready = au1550_device_ready;
559 this->select_chip = au1550_select_chip;
560 this->cmdfunc = au1550_command;
561
562 /* 30 us command delay time */
563 this->chip_delay = 30;
564 this->ecc.mode = NAND_ECC_SOFT;
565
566 this->options = NAND_NO_AUTOINCR;
567
568 if (!nand_width)
569 this->options |= NAND_BUSWIDTH_16;
570
571 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
572 au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
573 this->read_word = au_read_word;
574 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
575 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
576 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
577
578 /* Scan to find existence of the device */
579 if (nand_scan(au1550_mtd, 1)) {
580 retval = -ENXIO;
581 goto outio;
582 }
583
584 /* Register the partitions */
585 add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info));
586
587 return 0;
588
589 outio:
590 iounmap((void *)p_nand);
591
592 outmem:
593 kfree(au1550_mtd);
594 return retval;
595 }
596
597 module_init(au1xxx_nand_init);
598
599 /*
600 * Clean up routine
601 */
au1550_cleanup(void)602 static void __exit au1550_cleanup(void)
603 {
604 /* Release resources, unregister device */
605 nand_release(au1550_mtd);
606
607 /* Free the MTD device structure */
608 kfree(au1550_mtd);
609
610 /* Unmap */
611 iounmap((void *)p_nand);
612 }
613
614 module_exit(au1550_cleanup);
615
616 MODULE_LICENSE("GPL");
617 MODULE_AUTHOR("Embedded Edge, LLC");
618 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
619