1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
7 *
8 * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle
9 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
10 *
11 * References:
12 * o IOC3 ASIC specification 4.51, 1996-04-18
13 * o IEEE 802.3 specification, 2000 edition
14 * o DP38840A Specification, National Semiconductor, March 1997
15 *
16 * To do:
17 *
18 * o Handle allocation failures in ioc3_alloc_skb() more gracefully.
19 * o Handle allocation failures in ioc3_init_rings().
20 * o Use prefetching for large packets. What is a good lower limit for
21 * prefetching?
22 * o We're probably allocating a bit too much memory.
23 * o Use hardware checksums.
24 * o Convert to using a IOC3 meta driver.
25 * o Which PHYs might possibly be attached to the IOC3 in real live,
26 * which workarounds are required for them? Do we ever have Lucent's?
27 * o For the 2.5 branch kill the mii-tool ioctls.
28 */
29
30 #define IOC3_NAME "ioc3-eth"
31 #define IOC3_VERSION "2.6.3-4"
32
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/kernel.h>
36 #include <linux/mm.h>
37 #include <linux/errno.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/crc32.h>
41 #include <linux/mii.h>
42 #include <linux/in.h>
43 #include <linux/ip.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/dma-mapping.h>
47
48 #ifdef CONFIG_SERIAL_8250
49 #include <linux/serial_core.h>
50 #include <linux/serial_8250.h>
51 #include <linux/serial_reg.h>
52 #endif
53
54 #include <linux/netdevice.h>
55 #include <linux/etherdevice.h>
56 #include <linux/ethtool.h>
57 #include <linux/skbuff.h>
58 #include <net/ip.h>
59
60 #include <asm/byteorder.h>
61 #include <asm/io.h>
62 #include <asm/pgtable.h>
63 #include <asm/uaccess.h>
64 #include <asm/sn/types.h>
65 #include <asm/sn/ioc3.h>
66 #include <asm/pci/bridge.h>
67
68 /*
69 * 64 RX buffers. This is tunable in the range of 16 <= x < 512. The
70 * value must be a power of two.
71 */
72 #define RX_BUFFS 64
73
74 #define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21)
75 #define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) | (21<<ETCSR_IPGR1_SHIFT) | 21)
76
77 /* Private per NIC data of the driver. */
78 struct ioc3_private {
79 struct ioc3 *regs;
80 unsigned long *rxr; /* pointer to receiver ring */
81 struct ioc3_etxd *txr;
82 struct sk_buff *rx_skbs[512];
83 struct sk_buff *tx_skbs[128];
84 struct net_device_stats stats;
85 int rx_ci; /* RX consumer index */
86 int rx_pi; /* RX producer index */
87 int tx_ci; /* TX consumer index */
88 int tx_pi; /* TX producer index */
89 int txqlen;
90 u32 emcr, ehar_h, ehar_l;
91 spinlock_t ioc3_lock;
92 struct mii_if_info mii;
93 unsigned long flags;
94 #define IOC3_FLAG_RX_CHECKSUMS 1
95
96 struct pci_dev *pdev;
97
98 /* Members used by autonegotiation */
99 struct timer_list ioc3_timer;
100 };
101
priv_netdev(struct ioc3_private * dev)102 static inline struct net_device *priv_netdev(struct ioc3_private *dev)
103 {
104 return (void *)dev - ((sizeof(struct net_device) + 31) & ~31);
105 }
106
107 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
108 static void ioc3_set_multicast_list(struct net_device *dev);
109 static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
110 static void ioc3_timeout(struct net_device *dev);
111 static inline unsigned int ioc3_hash(const unsigned char *addr);
112 static inline void ioc3_stop(struct ioc3_private *ip);
113 static void ioc3_init(struct net_device *dev);
114
115 static const char ioc3_str[] = "IOC3 Ethernet";
116 static const struct ethtool_ops ioc3_ethtool_ops;
117
118 /* We use this to acquire receive skb's that we can DMA directly into. */
119
120 #define IOC3_CACHELINE 128UL
121
aligned_rx_skb_addr(unsigned long addr)122 static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
123 {
124 return (~addr + 1) & (IOC3_CACHELINE - 1UL);
125 }
126
ioc3_alloc_skb(unsigned long length,unsigned int gfp_mask)127 static inline struct sk_buff * ioc3_alloc_skb(unsigned long length,
128 unsigned int gfp_mask)
129 {
130 struct sk_buff *skb;
131
132 skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);
133 if (likely(skb)) {
134 int offset = aligned_rx_skb_addr((unsigned long) skb->data);
135 if (offset)
136 skb_reserve(skb, offset);
137 }
138
139 return skb;
140 }
141
ioc3_map(void * ptr,unsigned long vdev)142 static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
143 {
144 #ifdef CONFIG_SGI_IP27
145 vdev <<= 57; /* Shift to PCI64_ATTR_VIRTUAL */
146
147 return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
148 ((unsigned long)ptr & TO_PHYS_MASK);
149 #else
150 return virt_to_bus(ptr);
151 #endif
152 }
153
154 /* BEWARE: The IOC3 documentation documents the size of rx buffers as
155 1644 while it's actually 1664. This one was nasty to track down ... */
156 #define RX_OFFSET 10
157 #define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
158
159 /* DMA barrier to separate cached and uncached accesses. */
160 #define BARRIER() \
161 __asm__("sync" ::: "memory")
162
163
164 #define IOC3_SIZE 0x100000
165
166 /*
167 * IOC3 is a big endian device
168 *
169 * Unorthodox but makes the users of these macros more readable - the pointer
170 * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3
171 * in the environment.
172 */
173 #define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
174 #define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
175 #define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
176 #define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
177 #define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
178 #define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
179 #define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
180 #define ioc3_r_eier() be32_to_cpu(ioc3->eier)
181 #define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
182 #define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
183 #define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
184 #define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
185 #define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
186 #define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
187 #define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
188 #define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
189 #define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
190 #define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
191 #define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
192 #define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
193 #define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
194 #define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
195 #define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
196 #define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
197 #define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
198 #define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
199 #define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
200 #define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
201 #define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
202 #define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
203 #define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
204 #define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
205 #define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
206 #define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
207 #define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
208 #define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
209 #define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
210 #define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
211 #define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
212 #define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
213 #define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
214 #define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
215 #define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
216 #define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
217 #define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
218 #define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
219 #define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
220 #define ioc3_r_micr() be32_to_cpu(ioc3->micr)
221 #define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
222 #define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
223 #define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
224 #define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
225 #define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
226
mcr_pack(u32 pulse,u32 sample)227 static inline u32 mcr_pack(u32 pulse, u32 sample)
228 {
229 return (pulse << 10) | (sample << 2);
230 }
231
nic_wait(struct ioc3 * ioc3)232 static int nic_wait(struct ioc3 *ioc3)
233 {
234 u32 mcr;
235
236 do {
237 mcr = ioc3_r_mcr();
238 } while (!(mcr & 2));
239
240 return mcr & 1;
241 }
242
nic_reset(struct ioc3 * ioc3)243 static int nic_reset(struct ioc3 *ioc3)
244 {
245 int presence;
246
247 ioc3_w_mcr(mcr_pack(500, 65));
248 presence = nic_wait(ioc3);
249
250 ioc3_w_mcr(mcr_pack(0, 500));
251 nic_wait(ioc3);
252
253 return presence;
254 }
255
nic_read_bit(struct ioc3 * ioc3)256 static inline int nic_read_bit(struct ioc3 *ioc3)
257 {
258 int result;
259
260 ioc3_w_mcr(mcr_pack(6, 13));
261 result = nic_wait(ioc3);
262 ioc3_w_mcr(mcr_pack(0, 100));
263 nic_wait(ioc3);
264
265 return result;
266 }
267
nic_write_bit(struct ioc3 * ioc3,int bit)268 static inline void nic_write_bit(struct ioc3 *ioc3, int bit)
269 {
270 if (bit)
271 ioc3_w_mcr(mcr_pack(6, 110));
272 else
273 ioc3_w_mcr(mcr_pack(80, 30));
274
275 nic_wait(ioc3);
276 }
277
278 /*
279 * Read a byte from an iButton device
280 */
nic_read_byte(struct ioc3 * ioc3)281 static u32 nic_read_byte(struct ioc3 *ioc3)
282 {
283 u32 result = 0;
284 int i;
285
286 for (i = 0; i < 8; i++)
287 result = (result >> 1) | (nic_read_bit(ioc3) << 7);
288
289 return result;
290 }
291
292 /*
293 * Write a byte to an iButton device
294 */
nic_write_byte(struct ioc3 * ioc3,int byte)295 static void nic_write_byte(struct ioc3 *ioc3, int byte)
296 {
297 int i, bit;
298
299 for (i = 8; i; i--) {
300 bit = byte & 1;
301 byte >>= 1;
302
303 nic_write_bit(ioc3, bit);
304 }
305 }
306
nic_find(struct ioc3 * ioc3,int * last)307 static u64 nic_find(struct ioc3 *ioc3, int *last)
308 {
309 int a, b, index, disc;
310 u64 address = 0;
311
312 nic_reset(ioc3);
313 /* Search ROM. */
314 nic_write_byte(ioc3, 0xf0);
315
316 /* Algorithm from ``Book of iButton Standards''. */
317 for (index = 0, disc = 0; index < 64; index++) {
318 a = nic_read_bit(ioc3);
319 b = nic_read_bit(ioc3);
320
321 if (a && b) {
322 printk("NIC search failed (not fatal).\n");
323 *last = 0;
324 return 0;
325 }
326
327 if (!a && !b) {
328 if (index == *last) {
329 address |= 1UL << index;
330 } else if (index > *last) {
331 address &= ~(1UL << index);
332 disc = index;
333 } else if ((address & (1UL << index)) == 0)
334 disc = index;
335 nic_write_bit(ioc3, address & (1UL << index));
336 continue;
337 } else {
338 if (a)
339 address |= 1UL << index;
340 else
341 address &= ~(1UL << index);
342 nic_write_bit(ioc3, a);
343 continue;
344 }
345 }
346
347 *last = disc;
348
349 return address;
350 }
351
nic_init(struct ioc3 * ioc3)352 static int nic_init(struct ioc3 *ioc3)
353 {
354 const char *unknown = "unknown";
355 const char *type = unknown;
356 u8 crc;
357 u8 serial[6];
358 int save = 0, i;
359
360 while (1) {
361 u64 reg;
362 reg = nic_find(ioc3, &save);
363
364 switch (reg & 0xff) {
365 case 0x91:
366 type = "DS1981U";
367 break;
368 default:
369 if (save == 0) {
370 /* Let the caller try again. */
371 return -1;
372 }
373 continue;
374 }
375
376 nic_reset(ioc3);
377
378 /* Match ROM. */
379 nic_write_byte(ioc3, 0x55);
380 for (i = 0; i < 8; i++)
381 nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
382
383 reg >>= 8; /* Shift out type. */
384 for (i = 0; i < 6; i++) {
385 serial[i] = reg & 0xff;
386 reg >>= 8;
387 }
388 crc = reg & 0xff;
389 break;
390 }
391
392 printk("Found %s NIC", type);
393 if (type != unknown)
394 printk (" registration number %pM, CRC %02x", serial, crc);
395 printk(".\n");
396
397 return 0;
398 }
399
400 /*
401 * Read the NIC (Number-In-a-Can) device used to store the MAC address on
402 * SN0 / SN00 nodeboards and PCI cards.
403 */
ioc3_get_eaddr_nic(struct ioc3_private * ip)404 static void ioc3_get_eaddr_nic(struct ioc3_private *ip)
405 {
406 struct ioc3 *ioc3 = ip->regs;
407 u8 nic[14];
408 int tries = 2; /* There may be some problem with the battery? */
409 int i;
410
411 ioc3_w_gpcr_s(1 << 21);
412
413 while (tries--) {
414 if (!nic_init(ioc3))
415 break;
416 udelay(500);
417 }
418
419 if (tries < 0) {
420 printk("Failed to read MAC address\n");
421 return;
422 }
423
424 /* Read Memory. */
425 nic_write_byte(ioc3, 0xf0);
426 nic_write_byte(ioc3, 0x00);
427 nic_write_byte(ioc3, 0x00);
428
429 for (i = 13; i >= 0; i--)
430 nic[i] = nic_read_byte(ioc3);
431
432 for (i = 2; i < 8; i++)
433 priv_netdev(ip)->dev_addr[i - 2] = nic[i];
434 }
435
436 /*
437 * Ok, this is hosed by design. It's necessary to know what machine the
438 * NIC is in in order to know how to read the NIC address. We also have
439 * to know if it's a PCI card or a NIC in on the node board ...
440 */
ioc3_get_eaddr(struct ioc3_private * ip)441 static void ioc3_get_eaddr(struct ioc3_private *ip)
442 {
443 ioc3_get_eaddr_nic(ip);
444
445 printk("Ethernet address is %pM.\n", priv_netdev(ip)->dev_addr);
446 }
447
__ioc3_set_mac_address(struct net_device * dev)448 static void __ioc3_set_mac_address(struct net_device *dev)
449 {
450 struct ioc3_private *ip = netdev_priv(dev);
451 struct ioc3 *ioc3 = ip->regs;
452
453 ioc3_w_emar_h((dev->dev_addr[5] << 8) | dev->dev_addr[4]);
454 ioc3_w_emar_l((dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) |
455 (dev->dev_addr[1] << 8) | dev->dev_addr[0]);
456 }
457
ioc3_set_mac_address(struct net_device * dev,void * addr)458 static int ioc3_set_mac_address(struct net_device *dev, void *addr)
459 {
460 struct ioc3_private *ip = netdev_priv(dev);
461 struct sockaddr *sa = addr;
462
463 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
464
465 spin_lock_irq(&ip->ioc3_lock);
466 __ioc3_set_mac_address(dev);
467 spin_unlock_irq(&ip->ioc3_lock);
468
469 return 0;
470 }
471
472 /*
473 * Caller must hold the ioc3_lock ever for MII readers. This is also
474 * used to protect the transmitter side but it's low contention.
475 */
ioc3_mdio_read(struct net_device * dev,int phy,int reg)476 static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
477 {
478 struct ioc3_private *ip = netdev_priv(dev);
479 struct ioc3 *ioc3 = ip->regs;
480
481 while (ioc3_r_micr() & MICR_BUSY);
482 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG);
483 while (ioc3_r_micr() & MICR_BUSY);
484
485 return ioc3_r_midr_r() & MIDR_DATA_MASK;
486 }
487
ioc3_mdio_write(struct net_device * dev,int phy,int reg,int data)488 static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
489 {
490 struct ioc3_private *ip = netdev_priv(dev);
491 struct ioc3 *ioc3 = ip->regs;
492
493 while (ioc3_r_micr() & MICR_BUSY);
494 ioc3_w_midr_w(data);
495 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg);
496 while (ioc3_r_micr() & MICR_BUSY);
497 }
498
499 static int ioc3_mii_init(struct ioc3_private *ip);
500
ioc3_get_stats(struct net_device * dev)501 static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
502 {
503 struct ioc3_private *ip = netdev_priv(dev);
504 struct ioc3 *ioc3 = ip->regs;
505
506 ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK);
507 return &ip->stats;
508 }
509
ioc3_tcpudp_checksum(struct sk_buff * skb,uint32_t hwsum,int len)510 static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)
511 {
512 struct ethhdr *eh = eth_hdr(skb);
513 uint32_t csum, ehsum;
514 unsigned int proto;
515 struct iphdr *ih;
516 uint16_t *ew;
517 unsigned char *cp;
518
519 /*
520 * Did hardware handle the checksum at all? The cases we can handle
521 * are:
522 *
523 * - TCP and UDP checksums of IPv4 only.
524 * - IPv6 would be doable but we keep that for later ...
525 * - Only unfragmented packets. Did somebody already tell you
526 * fragmentation is evil?
527 * - don't care about packet size. Worst case when processing a
528 * malformed packet we'll try to access the packet at ip header +
529 * 64 bytes which is still inside the skb. Even in the unlikely
530 * case where the checksum is right the higher layers will still
531 * drop the packet as appropriate.
532 */
533 if (eh->h_proto != ntohs(ETH_P_IP))
534 return;
535
536 ih = (struct iphdr *) ((char *)eh + ETH_HLEN);
537 if (ih->frag_off & htons(IP_MF | IP_OFFSET))
538 return;
539
540 proto = ih->protocol;
541 if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
542 return;
543
544 /* Same as tx - compute csum of pseudo header */
545 csum = hwsum +
546 (ih->tot_len - (ih->ihl << 2)) +
547 htons((uint16_t)ih->protocol) +
548 (ih->saddr >> 16) + (ih->saddr & 0xffff) +
549 (ih->daddr >> 16) + (ih->daddr & 0xffff);
550
551 /* Sum up ethernet dest addr, src addr and protocol */
552 ew = (uint16_t *) eh;
553 ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
554
555 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
556 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
557
558 csum += 0xffff ^ ehsum;
559
560 /* In the next step we also subtract the 1's complement
561 checksum of the trailing ethernet CRC. */
562 cp = (char *)eh + len; /* points at trailing CRC */
563 if (len & 1) {
564 csum += 0xffff ^ (uint16_t) ((cp[1] << 8) | cp[0]);
565 csum += 0xffff ^ (uint16_t) ((cp[3] << 8) | cp[2]);
566 } else {
567 csum += 0xffff ^ (uint16_t) ((cp[0] << 8) | cp[1]);
568 csum += 0xffff ^ (uint16_t) ((cp[2] << 8) | cp[3]);
569 }
570
571 csum = (csum & 0xffff) + (csum >> 16);
572 csum = (csum & 0xffff) + (csum >> 16);
573
574 if (csum == 0xffff)
575 skb->ip_summed = CHECKSUM_UNNECESSARY;
576 }
577
ioc3_rx(struct ioc3_private * ip)578 static inline void ioc3_rx(struct ioc3_private *ip)
579 {
580 struct sk_buff *skb, *new_skb;
581 struct ioc3 *ioc3 = ip->regs;
582 int rx_entry, n_entry, len;
583 struct ioc3_erxbuf *rxb;
584 unsigned long *rxr;
585 u32 w0, err;
586
587 rxr = (unsigned long *) ip->rxr; /* Ring base */
588 rx_entry = ip->rx_ci; /* RX consume index */
589 n_entry = ip->rx_pi;
590
591 skb = ip->rx_skbs[rx_entry];
592 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
593 w0 = be32_to_cpu(rxb->w0);
594
595 while (w0 & ERXBUF_V) {
596 err = be32_to_cpu(rxb->err); /* It's valid ... */
597 if (err & ERXBUF_GOODPKT) {
598 len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
599 skb_trim(skb, len);
600 skb->protocol = eth_type_trans(skb, priv_netdev(ip));
601
602 new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
603 if (!new_skb) {
604 /* Ouch, drop packet and just recycle packet
605 to keep the ring filled. */
606 ip->stats.rx_dropped++;
607 new_skb = skb;
608 goto next;
609 }
610
611 if (likely(ip->flags & IOC3_FLAG_RX_CHECKSUMS))
612 ioc3_tcpudp_checksum(skb,
613 w0 & ERXBUF_IPCKSUM_MASK, len);
614
615 netif_rx(skb);
616
617 ip->rx_skbs[rx_entry] = NULL; /* Poison */
618
619 /* Because we reserve afterwards. */
620 skb_put(new_skb, (1664 + RX_OFFSET));
621 rxb = (struct ioc3_erxbuf *) new_skb->data;
622 skb_reserve(new_skb, RX_OFFSET);
623
624 ip->stats.rx_packets++; /* Statistics */
625 ip->stats.rx_bytes += len;
626 } else {
627 /* The frame is invalid and the skb never
628 reached the network layer so we can just
629 recycle it. */
630 new_skb = skb;
631 ip->stats.rx_errors++;
632 }
633 if (err & ERXBUF_CRCERR) /* Statistics */
634 ip->stats.rx_crc_errors++;
635 if (err & ERXBUF_FRAMERR)
636 ip->stats.rx_frame_errors++;
637 next:
638 ip->rx_skbs[n_entry] = new_skb;
639 rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1));
640 rxb->w0 = 0; /* Clear valid flag */
641 n_entry = (n_entry + 1) & 511; /* Update erpir */
642
643 /* Now go on to the next ring entry. */
644 rx_entry = (rx_entry + 1) & 511;
645 skb = ip->rx_skbs[rx_entry];
646 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
647 w0 = be32_to_cpu(rxb->w0);
648 }
649 ioc3_w_erpir((n_entry << 3) | ERPIR_ARM);
650 ip->rx_pi = n_entry;
651 ip->rx_ci = rx_entry;
652 }
653
ioc3_tx(struct ioc3_private * ip)654 static inline void ioc3_tx(struct ioc3_private *ip)
655 {
656 unsigned long packets, bytes;
657 struct ioc3 *ioc3 = ip->regs;
658 int tx_entry, o_entry;
659 struct sk_buff *skb;
660 u32 etcir;
661
662 spin_lock(&ip->ioc3_lock);
663 etcir = ioc3_r_etcir();
664
665 tx_entry = (etcir >> 7) & 127;
666 o_entry = ip->tx_ci;
667 packets = 0;
668 bytes = 0;
669
670 while (o_entry != tx_entry) {
671 packets++;
672 skb = ip->tx_skbs[o_entry];
673 bytes += skb->len;
674 dev_kfree_skb_irq(skb);
675 ip->tx_skbs[o_entry] = NULL;
676
677 o_entry = (o_entry + 1) & 127; /* Next */
678
679 etcir = ioc3_r_etcir(); /* More pkts sent? */
680 tx_entry = (etcir >> 7) & 127;
681 }
682
683 ip->stats.tx_packets += packets;
684 ip->stats.tx_bytes += bytes;
685 ip->txqlen -= packets;
686
687 if (ip->txqlen < 128)
688 netif_wake_queue(priv_netdev(ip));
689
690 ip->tx_ci = o_entry;
691 spin_unlock(&ip->ioc3_lock);
692 }
693
694 /*
695 * Deal with fatal IOC3 errors. This condition might be caused by a hard or
696 * software problems, so we should try to recover
697 * more gracefully if this ever happens. In theory we might be flooded
698 * with such error interrupts if something really goes wrong, so we might
699 * also consider to take the interface down.
700 */
ioc3_error(struct ioc3_private * ip,u32 eisr)701 static void ioc3_error(struct ioc3_private *ip, u32 eisr)
702 {
703 struct net_device *dev = priv_netdev(ip);
704 unsigned char *iface = dev->name;
705
706 spin_lock(&ip->ioc3_lock);
707
708 if (eisr & EISR_RXOFLO)
709 printk(KERN_ERR "%s: RX overflow.\n", iface);
710 if (eisr & EISR_RXBUFOFLO)
711 printk(KERN_ERR "%s: RX buffer overflow.\n", iface);
712 if (eisr & EISR_RXMEMERR)
713 printk(KERN_ERR "%s: RX PCI error.\n", iface);
714 if (eisr & EISR_RXPARERR)
715 printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);
716 if (eisr & EISR_TXBUFUFLO)
717 printk(KERN_ERR "%s: TX buffer underflow.\n", iface);
718 if (eisr & EISR_TXMEMERR)
719 printk(KERN_ERR "%s: TX PCI error.\n", iface);
720
721 ioc3_stop(ip);
722 ioc3_init(dev);
723 ioc3_mii_init(ip);
724
725 netif_wake_queue(dev);
726
727 spin_unlock(&ip->ioc3_lock);
728 }
729
730 /* The interrupt handler does all of the Rx thread work and cleans up
731 after the Tx thread. */
ioc3_interrupt(int irq,void * _dev)732 static irqreturn_t ioc3_interrupt(int irq, void *_dev)
733 {
734 struct net_device *dev = (struct net_device *)_dev;
735 struct ioc3_private *ip = netdev_priv(dev);
736 struct ioc3 *ioc3 = ip->regs;
737 const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
738 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
739 EISR_TXEXPLICIT | EISR_TXMEMERR;
740 u32 eisr;
741
742 eisr = ioc3_r_eisr() & enabled;
743
744 ioc3_w_eisr(eisr);
745 (void) ioc3_r_eisr(); /* Flush */
746
747 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
748 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
749 ioc3_error(ip, eisr);
750 if (eisr & EISR_RXTIMERINT)
751 ioc3_rx(ip);
752 if (eisr & EISR_TXEXPLICIT)
753 ioc3_tx(ip);
754
755 return IRQ_HANDLED;
756 }
757
ioc3_setup_duplex(struct ioc3_private * ip)758 static inline void ioc3_setup_duplex(struct ioc3_private *ip)
759 {
760 struct ioc3 *ioc3 = ip->regs;
761
762 if (ip->mii.full_duplex) {
763 ioc3_w_etcsr(ETCSR_FD);
764 ip->emcr |= EMCR_DUPLEX;
765 } else {
766 ioc3_w_etcsr(ETCSR_HD);
767 ip->emcr &= ~EMCR_DUPLEX;
768 }
769 ioc3_w_emcr(ip->emcr);
770 }
771
ioc3_timer(unsigned long data)772 static void ioc3_timer(unsigned long data)
773 {
774 struct ioc3_private *ip = (struct ioc3_private *) data;
775
776 /* Print the link status if it has changed */
777 mii_check_media(&ip->mii, 1, 0);
778 ioc3_setup_duplex(ip);
779
780 ip->ioc3_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2s */
781 add_timer(&ip->ioc3_timer);
782 }
783
784 /*
785 * Try to find a PHY. There is no apparent relation between the MII addresses
786 * in the SGI documentation and what we find in reality, so we simply probe
787 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
788 * onboard IOC3s has the special oddity that probing doesn't seem to find it
789 * yet the interface seems to work fine, so if probing fails we for now will
790 * simply default to PHY 31 instead of bailing out.
791 */
ioc3_mii_init(struct ioc3_private * ip)792 static int ioc3_mii_init(struct ioc3_private *ip)
793 {
794 struct net_device *dev = priv_netdev(ip);
795 int i, found = 0, res = 0;
796 int ioc3_phy_workaround = 1;
797 u16 word;
798
799 for (i = 0; i < 32; i++) {
800 word = ioc3_mdio_read(dev, i, MII_PHYSID1);
801
802 if (word != 0xffff && word != 0x0000) {
803 found = 1;
804 break; /* Found a PHY */
805 }
806 }
807
808 if (!found) {
809 if (ioc3_phy_workaround)
810 i = 31;
811 else {
812 ip->mii.phy_id = -1;
813 res = -ENODEV;
814 goto out;
815 }
816 }
817
818 ip->mii.phy_id = i;
819
820 out:
821 return res;
822 }
823
ioc3_mii_start(struct ioc3_private * ip)824 static void ioc3_mii_start(struct ioc3_private *ip)
825 {
826 ip->ioc3_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
827 ip->ioc3_timer.data = (unsigned long) ip;
828 ip->ioc3_timer.function = &ioc3_timer;
829 add_timer(&ip->ioc3_timer);
830 }
831
ioc3_clean_rx_ring(struct ioc3_private * ip)832 static inline void ioc3_clean_rx_ring(struct ioc3_private *ip)
833 {
834 struct sk_buff *skb;
835 int i;
836
837 for (i = ip->rx_ci; i & 15; i++) {
838 ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci];
839 ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++];
840 }
841 ip->rx_pi &= 511;
842 ip->rx_ci &= 511;
843
844 for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) {
845 struct ioc3_erxbuf *rxb;
846 skb = ip->rx_skbs[i];
847 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
848 rxb->w0 = 0;
849 }
850 }
851
ioc3_clean_tx_ring(struct ioc3_private * ip)852 static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
853 {
854 struct sk_buff *skb;
855 int i;
856
857 for (i=0; i < 128; i++) {
858 skb = ip->tx_skbs[i];
859 if (skb) {
860 ip->tx_skbs[i] = NULL;
861 dev_kfree_skb_any(skb);
862 }
863 ip->txr[i].cmd = 0;
864 }
865 ip->tx_pi = 0;
866 ip->tx_ci = 0;
867 }
868
ioc3_free_rings(struct ioc3_private * ip)869 static void ioc3_free_rings(struct ioc3_private *ip)
870 {
871 struct sk_buff *skb;
872 int rx_entry, n_entry;
873
874 if (ip->txr) {
875 ioc3_clean_tx_ring(ip);
876 free_pages((unsigned long)ip->txr, 2);
877 ip->txr = NULL;
878 }
879
880 if (ip->rxr) {
881 n_entry = ip->rx_ci;
882 rx_entry = ip->rx_pi;
883
884 while (n_entry != rx_entry) {
885 skb = ip->rx_skbs[n_entry];
886 if (skb)
887 dev_kfree_skb_any(skb);
888
889 n_entry = (n_entry + 1) & 511;
890 }
891 free_page((unsigned long)ip->rxr);
892 ip->rxr = NULL;
893 }
894 }
895
ioc3_alloc_rings(struct net_device * dev)896 static void ioc3_alloc_rings(struct net_device *dev)
897 {
898 struct ioc3_private *ip = netdev_priv(dev);
899 struct ioc3_erxbuf *rxb;
900 unsigned long *rxr;
901 int i;
902
903 if (ip->rxr == NULL) {
904 /* Allocate and initialize rx ring. 4kb = 512 entries */
905 ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC);
906 rxr = (unsigned long *) ip->rxr;
907 if (!rxr)
908 printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");
909
910 /* Now the rx buffers. The RX ring may be larger but
911 we only allocate 16 buffers for now. Need to tune
912 this for performance and memory later. */
913 for (i = 0; i < RX_BUFFS; i++) {
914 struct sk_buff *skb;
915
916 skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
917 if (!skb) {
918 show_free_areas();
919 continue;
920 }
921
922 ip->rx_skbs[i] = skb;
923
924 /* Because we reserve afterwards. */
925 skb_put(skb, (1664 + RX_OFFSET));
926 rxb = (struct ioc3_erxbuf *) skb->data;
927 rxr[i] = cpu_to_be64(ioc3_map(rxb, 1));
928 skb_reserve(skb, RX_OFFSET);
929 }
930 ip->rx_ci = 0;
931 ip->rx_pi = RX_BUFFS;
932 }
933
934 if (ip->txr == NULL) {
935 /* Allocate and initialize tx rings. 16kb = 128 bufs. */
936 ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);
937 if (!ip->txr)
938 printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");
939 ip->tx_pi = 0;
940 ip->tx_ci = 0;
941 }
942 }
943
ioc3_init_rings(struct net_device * dev)944 static void ioc3_init_rings(struct net_device *dev)
945 {
946 struct ioc3_private *ip = netdev_priv(dev);
947 struct ioc3 *ioc3 = ip->regs;
948 unsigned long ring;
949
950 ioc3_free_rings(ip);
951 ioc3_alloc_rings(dev);
952
953 ioc3_clean_rx_ring(ip);
954 ioc3_clean_tx_ring(ip);
955
956 /* Now the rx ring base, consume & produce registers. */
957 ring = ioc3_map(ip->rxr, 0);
958 ioc3_w_erbr_h(ring >> 32);
959 ioc3_w_erbr_l(ring & 0xffffffff);
960 ioc3_w_ercir(ip->rx_ci << 3);
961 ioc3_w_erpir((ip->rx_pi << 3) | ERPIR_ARM);
962
963 ring = ioc3_map(ip->txr, 0);
964
965 ip->txqlen = 0; /* nothing queued */
966
967 /* Now the tx ring base, consume & produce registers. */
968 ioc3_w_etbr_h(ring >> 32);
969 ioc3_w_etbr_l(ring & 0xffffffff);
970 ioc3_w_etpir(ip->tx_pi << 7);
971 ioc3_w_etcir(ip->tx_ci << 7);
972 (void) ioc3_r_etcir(); /* Flush */
973 }
974
ioc3_ssram_disc(struct ioc3_private * ip)975 static inline void ioc3_ssram_disc(struct ioc3_private *ip)
976 {
977 struct ioc3 *ioc3 = ip->regs;
978 volatile u32 *ssram0 = &ioc3->ssram[0x0000];
979 volatile u32 *ssram1 = &ioc3->ssram[0x4000];
980 unsigned int pattern = 0x5555;
981
982 /* Assume the larger size SSRAM and enable parity checking */
983 ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ | EMCR_RAMPAR));
984
985 *ssram0 = pattern;
986 *ssram1 = ~pattern & IOC3_SSRAM_DM;
987
988 if ((*ssram0 & IOC3_SSRAM_DM) != pattern ||
989 (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
990 /* set ssram size to 64 KB */
991 ip->emcr = EMCR_RAMPAR;
992 ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ);
993 } else
994 ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR;
995 }
996
ioc3_init(struct net_device * dev)997 static void ioc3_init(struct net_device *dev)
998 {
999 struct ioc3_private *ip = netdev_priv(dev);
1000 struct ioc3 *ioc3 = ip->regs;
1001
1002 del_timer_sync(&ip->ioc3_timer); /* Kill if running */
1003
1004 ioc3_w_emcr(EMCR_RST); /* Reset */
1005 (void) ioc3_r_emcr(); /* Flush WB */
1006 udelay(4); /* Give it time ... */
1007 ioc3_w_emcr(0);
1008 (void) ioc3_r_emcr();
1009
1010 /* Misc registers */
1011 #ifdef CONFIG_SGI_IP27
1012 ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */
1013 #else
1014 ioc3_w_erbar(0); /* Let PCI API get it right */
1015 #endif
1016 (void) ioc3_r_etcdc(); /* Clear on read */
1017 ioc3_w_ercsr(15); /* RX low watermark */
1018 ioc3_w_ertr(0); /* Interrupt immediately */
1019 __ioc3_set_mac_address(dev);
1020 ioc3_w_ehar_h(ip->ehar_h);
1021 ioc3_w_ehar_l(ip->ehar_l);
1022 ioc3_w_ersr(42); /* XXX should be random */
1023
1024 ioc3_init_rings(dev);
1025
1026 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
1027 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
1028 ioc3_w_emcr(ip->emcr);
1029 ioc3_w_eier(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
1030 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
1031 EISR_TXEXPLICIT | EISR_TXMEMERR);
1032 (void) ioc3_r_eier();
1033 }
1034
ioc3_stop(struct ioc3_private * ip)1035 static inline void ioc3_stop(struct ioc3_private *ip)
1036 {
1037 struct ioc3 *ioc3 = ip->regs;
1038
1039 ioc3_w_emcr(0); /* Shutup */
1040 ioc3_w_eier(0); /* Disable interrupts */
1041 (void) ioc3_r_eier(); /* Flush */
1042 }
1043
ioc3_open(struct net_device * dev)1044 static int ioc3_open(struct net_device *dev)
1045 {
1046 struct ioc3_private *ip = netdev_priv(dev);
1047
1048 if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {
1049 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
1050
1051 return -EAGAIN;
1052 }
1053
1054 ip->ehar_h = 0;
1055 ip->ehar_l = 0;
1056 ioc3_init(dev);
1057 ioc3_mii_start(ip);
1058
1059 netif_start_queue(dev);
1060 return 0;
1061 }
1062
ioc3_close(struct net_device * dev)1063 static int ioc3_close(struct net_device *dev)
1064 {
1065 struct ioc3_private *ip = netdev_priv(dev);
1066
1067 del_timer_sync(&ip->ioc3_timer);
1068
1069 netif_stop_queue(dev);
1070
1071 ioc3_stop(ip);
1072 free_irq(dev->irq, dev);
1073
1074 ioc3_free_rings(ip);
1075 return 0;
1076 }
1077
1078 /*
1079 * MENET cards have four IOC3 chips, which are attached to two sets of
1080 * PCI slot resources each: the primary connections are on slots
1081 * 0..3 and the secondaries are on 4..7
1082 *
1083 * All four ethernets are brought out to connectors; six serial ports
1084 * (a pair from each of the first three IOC3s) are brought out to
1085 * MiniDINs; all other subdevices are left swinging in the wind, leave
1086 * them disabled.
1087 */
1088
ioc3_adjacent_is_ioc3(struct pci_dev * pdev,int slot)1089 static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot)
1090 {
1091 struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(slot, 0));
1092 int ret = 0;
1093
1094 if (dev) {
1095 if (dev->vendor == PCI_VENDOR_ID_SGI &&
1096 dev->device == PCI_DEVICE_ID_SGI_IOC3)
1097 ret = 1;
1098 pci_dev_put(dev);
1099 }
1100
1101 return ret;
1102 }
1103
ioc3_is_menet(struct pci_dev * pdev)1104 static int ioc3_is_menet(struct pci_dev *pdev)
1105 {
1106 return pdev->bus->parent == NULL &&
1107 ioc3_adjacent_is_ioc3(pdev, 0) &&
1108 ioc3_adjacent_is_ioc3(pdev, 1) &&
1109 ioc3_adjacent_is_ioc3(pdev, 2);
1110 }
1111
1112 #ifdef CONFIG_SERIAL_8250
1113 /*
1114 * Note about serial ports and consoles:
1115 * For console output, everyone uses the IOC3 UARTA (offset 0x178)
1116 * connected to the master node (look in ip27_setup_console() and
1117 * ip27prom_console_write()).
1118 *
1119 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
1120 * addresses on a partitioned machine. Since we currently use the ioc3
1121 * serial ports, we use dynamic serial port discovery that the serial.c
1122 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
1123 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
1124 * than UARTB's, although UARTA on o200s has traditionally been known as
1125 * port 0. So, we just use one serial port from each ioc3 (since the
1126 * serial driver adds addresses to get to higher ports).
1127 *
1128 * The first one to do a register_console becomes the preferred console
1129 * (if there is no kernel command line console= directive). /dev/console
1130 * (ie 5, 1) is then "aliased" into the device number returned by the
1131 * "device" routine referred to in this console structure
1132 * (ip27prom_console_dev).
1133 *
1134 * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
1135 * around ioc3 oddities in this respect.
1136 *
1137 * The IOC3 serials use a 22MHz clock rate with an additional divider which
1138 * can be programmed in the SCR register if the DLAB bit is set.
1139 *
1140 * Register to interrupt zero because we share the interrupt with
1141 * the serial driver which we don't properly support yet.
1142 *
1143 * Can't use UPF_IOREMAP as the whole of IOC3 resources have already been
1144 * registered.
1145 */
ioc3_8250_register(struct ioc3_uartregs __iomem * uart)1146 static void __devinit ioc3_8250_register(struct ioc3_uartregs __iomem *uart)
1147 {
1148 #define COSMISC_CONSTANT 6
1149
1150 struct uart_port port = {
1151 .irq = 0,
1152 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
1153 .iotype = UPIO_MEM,
1154 .regshift = 0,
1155 .uartclk = (22000000 << 1) / COSMISC_CONSTANT,
1156
1157 .membase = (unsigned char __iomem *) uart,
1158 .mapbase = (unsigned long) uart,
1159 };
1160 unsigned char lcr;
1161
1162 lcr = uart->iu_lcr;
1163 uart->iu_lcr = lcr | UART_LCR_DLAB;
1164 uart->iu_scr = COSMISC_CONSTANT,
1165 uart->iu_lcr = lcr;
1166 uart->iu_lcr;
1167 serial8250_register_port(&port);
1168 }
1169
ioc3_serial_probe(struct pci_dev * pdev,struct ioc3 * ioc3)1170 static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
1171 {
1172 /*
1173 * We need to recognice and treat the fourth MENET serial as it
1174 * does not have an SuperIO chip attached to it, therefore attempting
1175 * to access it will result in bus errors. We call something an
1176 * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
1177 * in it. This is paranoid but we want to avoid blowing up on a
1178 * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
1179 * not paranoid enough ...
1180 */
1181 if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
1182 return;
1183
1184 /*
1185 * Switch IOC3 to PIO mode. It probably already was but let's be
1186 * paranoid
1187 */
1188 ioc3->gpcr_s = GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL;
1189 ioc3->gpcr_s;
1190 ioc3->gppr_6 = 0;
1191 ioc3->gppr_6;
1192 ioc3->gppr_7 = 0;
1193 ioc3->gppr_7;
1194 ioc3->sscr_a = ioc3->sscr_a & ~SSCR_DMA_EN;
1195 ioc3->sscr_a;
1196 ioc3->sscr_b = ioc3->sscr_b & ~SSCR_DMA_EN;
1197 ioc3->sscr_b;
1198 /* Disable all SA/B interrupts except for SA/B_INT in SIO_IEC. */
1199 ioc3->sio_iec &= ~ (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL |
1200 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER |
1201 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS |
1202 SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR);
1203 ioc3->sio_iec |= SIO_IR_SA_INT;
1204 ioc3->sscr_a = 0;
1205 ioc3->sio_iec &= ~ (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL |
1206 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER |
1207 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS |
1208 SIO_IR_SB_TX_EXPLICIT | SIO_IR_SB_MEMERR);
1209 ioc3->sio_iec |= SIO_IR_SB_INT;
1210 ioc3->sscr_b = 0;
1211
1212 ioc3_8250_register(&ioc3->sregs.uarta);
1213 ioc3_8250_register(&ioc3->sregs.uartb);
1214 }
1215 #endif
1216
ioc3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1217 static int __devinit ioc3_probe(struct pci_dev *pdev,
1218 const struct pci_device_id *ent)
1219 {
1220 unsigned int sw_physid1, sw_physid2;
1221 struct net_device *dev = NULL;
1222 struct ioc3_private *ip;
1223 struct ioc3 *ioc3;
1224 unsigned long ioc3_base, ioc3_size;
1225 u32 vendor, model, rev;
1226 int err, pci_using_dac;
1227
1228 /* Configure DMA attributes. */
1229 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1230 if (!err) {
1231 pci_using_dac = 1;
1232 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1233 if (err < 0) {
1234 printk(KERN_ERR "%s: Unable to obtain 64 bit DMA "
1235 "for consistent allocations\n", pci_name(pdev));
1236 goto out;
1237 }
1238 } else {
1239 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1240 if (err) {
1241 printk(KERN_ERR "%s: No usable DMA configuration, "
1242 "aborting.\n", pci_name(pdev));
1243 goto out;
1244 }
1245 pci_using_dac = 0;
1246 }
1247
1248 if (pci_enable_device(pdev))
1249 return -ENODEV;
1250
1251 dev = alloc_etherdev(sizeof(struct ioc3_private));
1252 if (!dev) {
1253 err = -ENOMEM;
1254 goto out_disable;
1255 }
1256
1257 if (pci_using_dac)
1258 dev->features |= NETIF_F_HIGHDMA;
1259
1260 err = pci_request_regions(pdev, "ioc3");
1261 if (err)
1262 goto out_free;
1263
1264 SET_NETDEV_DEV(dev, &pdev->dev);
1265
1266 ip = netdev_priv(dev);
1267
1268 dev->irq = pdev->irq;
1269
1270 ioc3_base = pci_resource_start(pdev, 0);
1271 ioc3_size = pci_resource_len(pdev, 0);
1272 ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
1273 if (!ioc3) {
1274 printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n",
1275 pci_name(pdev));
1276 err = -ENOMEM;
1277 goto out_res;
1278 }
1279 ip->regs = ioc3;
1280
1281 #ifdef CONFIG_SERIAL_8250
1282 ioc3_serial_probe(pdev, ioc3);
1283 #endif
1284
1285 spin_lock_init(&ip->ioc3_lock);
1286 init_timer(&ip->ioc3_timer);
1287
1288 ioc3_stop(ip);
1289 ioc3_init(dev);
1290
1291 ip->pdev = pdev;
1292
1293 ip->mii.phy_id_mask = 0x1f;
1294 ip->mii.reg_num_mask = 0x1f;
1295 ip->mii.dev = dev;
1296 ip->mii.mdio_read = ioc3_mdio_read;
1297 ip->mii.mdio_write = ioc3_mdio_write;
1298
1299 ioc3_mii_init(ip);
1300
1301 if (ip->mii.phy_id == -1) {
1302 printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1303 pci_name(pdev));
1304 err = -ENODEV;
1305 goto out_stop;
1306 }
1307
1308 ioc3_mii_start(ip);
1309 ioc3_ssram_disc(ip);
1310 ioc3_get_eaddr(ip);
1311
1312 /* The IOC3-specific entries in the device structure. */
1313 dev->open = ioc3_open;
1314 dev->hard_start_xmit = ioc3_start_xmit;
1315 dev->tx_timeout = ioc3_timeout;
1316 dev->watchdog_timeo = 5 * HZ;
1317 dev->stop = ioc3_close;
1318 dev->get_stats = ioc3_get_stats;
1319 dev->do_ioctl = ioc3_ioctl;
1320 dev->set_multicast_list = ioc3_set_multicast_list;
1321 dev->set_mac_address = ioc3_set_mac_address;
1322 dev->ethtool_ops = &ioc3_ethtool_ops;
1323 dev->features = NETIF_F_IP_CSUM;
1324
1325 sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
1326 sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
1327
1328 err = register_netdev(dev);
1329 if (err)
1330 goto out_stop;
1331
1332 mii_check_media(&ip->mii, 1, 1);
1333 ioc3_setup_duplex(ip);
1334
1335 vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
1336 model = (sw_physid2 >> 4) & 0x3f;
1337 rev = sw_physid2 & 0xf;
1338 printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, "
1339 "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev);
1340 printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,
1341 ip->emcr & EMCR_BUFSIZ ? 128 : 64);
1342
1343 return 0;
1344
1345 out_stop:
1346 ioc3_stop(ip);
1347 del_timer_sync(&ip->ioc3_timer);
1348 ioc3_free_rings(ip);
1349 out_res:
1350 pci_release_regions(pdev);
1351 out_free:
1352 free_netdev(dev);
1353 out_disable:
1354 /*
1355 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1356 * such a weird device ...
1357 */
1358 out:
1359 return err;
1360 }
1361
ioc3_remove_one(struct pci_dev * pdev)1362 static void __devexit ioc3_remove_one (struct pci_dev *pdev)
1363 {
1364 struct net_device *dev = pci_get_drvdata(pdev);
1365 struct ioc3_private *ip = netdev_priv(dev);
1366 struct ioc3 *ioc3 = ip->regs;
1367
1368 unregister_netdev(dev);
1369 del_timer_sync(&ip->ioc3_timer);
1370
1371 iounmap(ioc3);
1372 pci_release_regions(pdev);
1373 free_netdev(dev);
1374 /*
1375 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1376 * such a weird device ...
1377 */
1378 }
1379
1380 static struct pci_device_id ioc3_pci_tbl[] = {
1381 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
1382 { 0 }
1383 };
1384 MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
1385
1386 static struct pci_driver ioc3_driver = {
1387 .name = "ioc3-eth",
1388 .id_table = ioc3_pci_tbl,
1389 .probe = ioc3_probe,
1390 .remove = __devexit_p(ioc3_remove_one),
1391 };
1392
ioc3_init_module(void)1393 static int __init ioc3_init_module(void)
1394 {
1395 return pci_register_driver(&ioc3_driver);
1396 }
1397
ioc3_cleanup_module(void)1398 static void __exit ioc3_cleanup_module(void)
1399 {
1400 pci_unregister_driver(&ioc3_driver);
1401 }
1402
ioc3_start_xmit(struct sk_buff * skb,struct net_device * dev)1403 static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1404 {
1405 unsigned long data;
1406 struct ioc3_private *ip = netdev_priv(dev);
1407 struct ioc3 *ioc3 = ip->regs;
1408 unsigned int len;
1409 struct ioc3_etxd *desc;
1410 uint32_t w0 = 0;
1411 int produce;
1412
1413 /*
1414 * IOC3 has a fairly simple minded checksumming hardware which simply
1415 * adds up the 1's complement checksum for the entire packet and
1416 * inserts it at an offset which can be specified in the descriptor
1417 * into the transmit packet. This means we have to compensate for the
1418 * MAC header which should not be summed and the TCP/UDP pseudo headers
1419 * manually.
1420 */
1421 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1422 const struct iphdr *ih = ip_hdr(skb);
1423 const int proto = ntohs(ih->protocol);
1424 unsigned int csoff;
1425 uint32_t csum, ehsum;
1426 uint16_t *eh;
1427
1428 /* The MAC header. skb->mac seem the logic approach
1429 to find the MAC header - except it's a NULL pointer ... */
1430 eh = (uint16_t *) skb->data;
1431
1432 /* Sum up dest addr, src addr and protocol */
1433 ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
1434
1435 /* Fold ehsum. can't use csum_fold which negates also ... */
1436 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1437 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1438
1439 /* Skip IP header; it's sum is always zero and was
1440 already filled in by ip_output.c */
1441 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
1442 ih->tot_len - (ih->ihl << 2),
1443 proto, 0xffff ^ ehsum);
1444
1445 csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
1446 csum = (csum & 0xffff) + (csum >> 16);
1447
1448 csoff = ETH_HLEN + (ih->ihl << 2);
1449 if (proto == IPPROTO_UDP) {
1450 csoff += offsetof(struct udphdr, check);
1451 udp_hdr(skb)->check = csum;
1452 }
1453 if (proto == IPPROTO_TCP) {
1454 csoff += offsetof(struct tcphdr, check);
1455 tcp_hdr(skb)->check = csum;
1456 }
1457
1458 w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
1459 }
1460
1461 spin_lock_irq(&ip->ioc3_lock);
1462
1463 data = (unsigned long) skb->data;
1464 len = skb->len;
1465
1466 produce = ip->tx_pi;
1467 desc = &ip->txr[produce];
1468
1469 if (len <= 104) {
1470 /* Short packet, let's copy it directly into the ring. */
1471 skb_copy_from_linear_data(skb, desc->data, skb->len);
1472 if (len < ETH_ZLEN) {
1473 /* Very short packet, pad with zeros at the end. */
1474 memset(desc->data + len, 0, ETH_ZLEN - len);
1475 len = ETH_ZLEN;
1476 }
1477 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
1478 desc->bufcnt = cpu_to_be32(len);
1479 } else if ((data ^ (data + len - 1)) & 0x4000) {
1480 unsigned long b2 = (data | 0x3fffUL) + 1UL;
1481 unsigned long s1 = b2 - data;
1482 unsigned long s2 = data + len - b2;
1483
1484 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
1485 ETXD_B1V | ETXD_B2V | w0);
1486 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
1487 (s2 << ETXD_B2CNT_SHIFT));
1488 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1489 desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1));
1490 } else {
1491 /* Normal sized packet that doesn't cross a page boundary. */
1492 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
1493 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
1494 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1495 }
1496
1497 BARRIER();
1498
1499 dev->trans_start = jiffies;
1500 ip->tx_skbs[produce] = skb; /* Remember skb */
1501 produce = (produce + 1) & 127;
1502 ip->tx_pi = produce;
1503 ioc3_w_etpir(produce << 7); /* Fire ... */
1504
1505 ip->txqlen++;
1506
1507 if (ip->txqlen >= 127)
1508 netif_stop_queue(dev);
1509
1510 spin_unlock_irq(&ip->ioc3_lock);
1511
1512 return 0;
1513 }
1514
ioc3_timeout(struct net_device * dev)1515 static void ioc3_timeout(struct net_device *dev)
1516 {
1517 struct ioc3_private *ip = netdev_priv(dev);
1518
1519 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
1520
1521 spin_lock_irq(&ip->ioc3_lock);
1522
1523 ioc3_stop(ip);
1524 ioc3_init(dev);
1525 ioc3_mii_init(ip);
1526 ioc3_mii_start(ip);
1527
1528 spin_unlock_irq(&ip->ioc3_lock);
1529
1530 netif_wake_queue(dev);
1531 }
1532
1533 /*
1534 * Given a multicast ethernet address, this routine calculates the
1535 * address's bit index in the logical address filter mask
1536 */
1537
ioc3_hash(const unsigned char * addr)1538 static inline unsigned int ioc3_hash(const unsigned char *addr)
1539 {
1540 unsigned int temp = 0;
1541 u32 crc;
1542 int bits;
1543
1544 crc = ether_crc_le(ETH_ALEN, addr);
1545
1546 crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
1547 for (bits = 6; --bits >= 0; ) {
1548 temp <<= 1;
1549 temp |= (crc & 0x1);
1550 crc >>= 1;
1551 }
1552
1553 return temp;
1554 }
1555
ioc3_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1556 static void ioc3_get_drvinfo (struct net_device *dev,
1557 struct ethtool_drvinfo *info)
1558 {
1559 struct ioc3_private *ip = netdev_priv(dev);
1560
1561 strcpy (info->driver, IOC3_NAME);
1562 strcpy (info->version, IOC3_VERSION);
1563 strcpy (info->bus_info, pci_name(ip->pdev));
1564 }
1565
ioc3_get_settings(struct net_device * dev,struct ethtool_cmd * cmd)1566 static int ioc3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1567 {
1568 struct ioc3_private *ip = netdev_priv(dev);
1569 int rc;
1570
1571 spin_lock_irq(&ip->ioc3_lock);
1572 rc = mii_ethtool_gset(&ip->mii, cmd);
1573 spin_unlock_irq(&ip->ioc3_lock);
1574
1575 return rc;
1576 }
1577
ioc3_set_settings(struct net_device * dev,struct ethtool_cmd * cmd)1578 static int ioc3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1579 {
1580 struct ioc3_private *ip = netdev_priv(dev);
1581 int rc;
1582
1583 spin_lock_irq(&ip->ioc3_lock);
1584 rc = mii_ethtool_sset(&ip->mii, cmd);
1585 spin_unlock_irq(&ip->ioc3_lock);
1586
1587 return rc;
1588 }
1589
ioc3_nway_reset(struct net_device * dev)1590 static int ioc3_nway_reset(struct net_device *dev)
1591 {
1592 struct ioc3_private *ip = netdev_priv(dev);
1593 int rc;
1594
1595 spin_lock_irq(&ip->ioc3_lock);
1596 rc = mii_nway_restart(&ip->mii);
1597 spin_unlock_irq(&ip->ioc3_lock);
1598
1599 return rc;
1600 }
1601
ioc3_get_link(struct net_device * dev)1602 static u32 ioc3_get_link(struct net_device *dev)
1603 {
1604 struct ioc3_private *ip = netdev_priv(dev);
1605 int rc;
1606
1607 spin_lock_irq(&ip->ioc3_lock);
1608 rc = mii_link_ok(&ip->mii);
1609 spin_unlock_irq(&ip->ioc3_lock);
1610
1611 return rc;
1612 }
1613
ioc3_get_rx_csum(struct net_device * dev)1614 static u32 ioc3_get_rx_csum(struct net_device *dev)
1615 {
1616 struct ioc3_private *ip = netdev_priv(dev);
1617
1618 return ip->flags & IOC3_FLAG_RX_CHECKSUMS;
1619 }
1620
ioc3_set_rx_csum(struct net_device * dev,u32 data)1621 static int ioc3_set_rx_csum(struct net_device *dev, u32 data)
1622 {
1623 struct ioc3_private *ip = netdev_priv(dev);
1624
1625 spin_lock_bh(&ip->ioc3_lock);
1626 if (data)
1627 ip->flags |= IOC3_FLAG_RX_CHECKSUMS;
1628 else
1629 ip->flags &= ~IOC3_FLAG_RX_CHECKSUMS;
1630 spin_unlock_bh(&ip->ioc3_lock);
1631
1632 return 0;
1633 }
1634
1635 static const struct ethtool_ops ioc3_ethtool_ops = {
1636 .get_drvinfo = ioc3_get_drvinfo,
1637 .get_settings = ioc3_get_settings,
1638 .set_settings = ioc3_set_settings,
1639 .nway_reset = ioc3_nway_reset,
1640 .get_link = ioc3_get_link,
1641 .get_rx_csum = ioc3_get_rx_csum,
1642 .set_rx_csum = ioc3_set_rx_csum,
1643 .get_tx_csum = ethtool_op_get_tx_csum,
1644 .set_tx_csum = ethtool_op_set_tx_csum
1645 };
1646
ioc3_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1647 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1648 {
1649 struct ioc3_private *ip = netdev_priv(dev);
1650 int rc;
1651
1652 spin_lock_irq(&ip->ioc3_lock);
1653 rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
1654 spin_unlock_irq(&ip->ioc3_lock);
1655
1656 return rc;
1657 }
1658
ioc3_set_multicast_list(struct net_device * dev)1659 static void ioc3_set_multicast_list(struct net_device *dev)
1660 {
1661 struct dev_mc_list *dmi = dev->mc_list;
1662 struct ioc3_private *ip = netdev_priv(dev);
1663 struct ioc3 *ioc3 = ip->regs;
1664 u64 ehar = 0;
1665 int i;
1666
1667 netif_stop_queue(dev); /* Lock out others. */
1668
1669 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1670 ip->emcr |= EMCR_PROMISC;
1671 ioc3_w_emcr(ip->emcr);
1672 (void) ioc3_r_emcr();
1673 } else {
1674 ip->emcr &= ~EMCR_PROMISC;
1675 ioc3_w_emcr(ip->emcr); /* Clear promiscuous. */
1676 (void) ioc3_r_emcr();
1677
1678 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1679 /* Too many for hashing to make sense or we want all
1680 multicast packets anyway, so skip computing all the
1681 hashes and just accept all packets. */
1682 ip->ehar_h = 0xffffffff;
1683 ip->ehar_l = 0xffffffff;
1684 } else {
1685 for (i = 0; i < dev->mc_count; i++) {
1686 char *addr = dmi->dmi_addr;
1687 dmi = dmi->next;
1688
1689 if (!(*addr & 1))
1690 continue;
1691
1692 ehar |= (1UL << ioc3_hash(addr));
1693 }
1694 ip->ehar_h = ehar >> 32;
1695 ip->ehar_l = ehar & 0xffffffff;
1696 }
1697 ioc3_w_ehar_h(ip->ehar_h);
1698 ioc3_w_ehar_l(ip->ehar_l);
1699 }
1700
1701 netif_wake_queue(dev); /* Let us get going again. */
1702 }
1703
1704 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1705 MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1706 MODULE_LICENSE("GPL");
1707
1708 module_init(ioc3_init_module);
1709 module_exit(ioc3_cleanup_module);
1710