1 /*
2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/init.h>
35 #include <linux/interrupt.h>
36 #include <linux/mm.h>
37 #include <linux/dma-mapping.h>
38
39 #include <linux/mlx4/cmd.h>
40
41 #include "mlx4.h"
42 #include "fw.h"
43
44 enum {
45 MLX4_NUM_ASYNC_EQE = 0x100,
46 MLX4_NUM_SPARE_EQE = 0x80,
47 MLX4_EQ_ENTRY_SIZE = 0x20
48 };
49
50 /*
51 * Must be packed because start is 64 bits but only aligned to 32 bits.
52 */
53 struct mlx4_eq_context {
54 __be32 flags;
55 u16 reserved1[3];
56 __be16 page_offset;
57 u8 log_eq_size;
58 u8 reserved2[4];
59 u8 eq_period;
60 u8 reserved3;
61 u8 eq_max_count;
62 u8 reserved4[3];
63 u8 intr;
64 u8 log_page_size;
65 u8 reserved5[2];
66 u8 mtt_base_addr_h;
67 __be32 mtt_base_addr_l;
68 u32 reserved6[2];
69 __be32 consumer_index;
70 __be32 producer_index;
71 u32 reserved7[4];
72 };
73
74 #define MLX4_EQ_STATUS_OK ( 0 << 28)
75 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
76 #define MLX4_EQ_OWNER_SW ( 0 << 24)
77 #define MLX4_EQ_OWNER_HW ( 1 << 24)
78 #define MLX4_EQ_FLAG_EC ( 1 << 18)
79 #define MLX4_EQ_FLAG_OI ( 1 << 17)
80 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
81 #define MLX4_EQ_STATE_FIRED (10 << 8)
82 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
83
84 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
85 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
86 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
87 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
88 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
89 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
90 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
91 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
92 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
93 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
94 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
95 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
96 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
97 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
98 (1ull << MLX4_EVENT_TYPE_CMD))
99
100 struct mlx4_eqe {
101 u8 reserved1;
102 u8 type;
103 u8 reserved2;
104 u8 subtype;
105 union {
106 u32 raw[6];
107 struct {
108 __be32 cqn;
109 } __attribute__((packed)) comp;
110 struct {
111 u16 reserved1;
112 __be16 token;
113 u32 reserved2;
114 u8 reserved3[3];
115 u8 status;
116 __be64 out_param;
117 } __attribute__((packed)) cmd;
118 struct {
119 __be32 qpn;
120 } __attribute__((packed)) qp;
121 struct {
122 __be32 srqn;
123 } __attribute__((packed)) srq;
124 struct {
125 __be32 cqn;
126 u32 reserved1;
127 u8 reserved2[3];
128 u8 syndrome;
129 } __attribute__((packed)) cq_err;
130 struct {
131 u32 reserved1[2];
132 __be32 port;
133 } __attribute__((packed)) port_change;
134 } event;
135 u8 reserved3[3];
136 u8 owner;
137 } __attribute__((packed));
138
eq_set_ci(struct mlx4_eq * eq,int req_not)139 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
140 {
141 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
142 req_not << 31),
143 eq->doorbell);
144 /* We still want ordering, just not swabbing, so add a barrier */
145 mb();
146 }
147
get_eqe(struct mlx4_eq * eq,u32 entry)148 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry)
149 {
150 unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
151 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
152 }
153
next_eqe_sw(struct mlx4_eq * eq)154 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq)
155 {
156 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
157 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
158 }
159
mlx4_eq_int(struct mlx4_dev * dev,struct mlx4_eq * eq)160 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
161 {
162 struct mlx4_eqe *eqe;
163 int cqn;
164 int eqes_found = 0;
165 int set_ci = 0;
166
167 while ((eqe = next_eqe_sw(eq))) {
168 /*
169 * Make sure we read EQ entry contents after we've
170 * checked the ownership bit.
171 */
172 rmb();
173
174 switch (eqe->type) {
175 case MLX4_EVENT_TYPE_COMP:
176 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
177 mlx4_cq_completion(dev, cqn);
178 break;
179
180 case MLX4_EVENT_TYPE_PATH_MIG:
181 case MLX4_EVENT_TYPE_COMM_EST:
182 case MLX4_EVENT_TYPE_SQ_DRAINED:
183 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
184 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
185 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
186 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
187 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
188 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
189 eqe->type);
190 break;
191
192 case MLX4_EVENT_TYPE_SRQ_LIMIT:
193 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
194 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
195 eqe->type);
196 break;
197
198 case MLX4_EVENT_TYPE_CMD:
199 mlx4_cmd_event(dev,
200 be16_to_cpu(eqe->event.cmd.token),
201 eqe->event.cmd.status,
202 be64_to_cpu(eqe->event.cmd.out_param));
203 break;
204
205 case MLX4_EVENT_TYPE_PORT_CHANGE:
206 mlx4_dispatch_event(dev,
207 eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_ACTIVE ?
208 MLX4_DEV_EVENT_PORT_UP :
209 MLX4_DEV_EVENT_PORT_DOWN,
210 be32_to_cpu(eqe->event.port_change.port) >> 28);
211 break;
212
213 case MLX4_EVENT_TYPE_CQ_ERROR:
214 mlx4_warn(dev, "CQ %s on CQN %06x\n",
215 eqe->event.cq_err.syndrome == 1 ?
216 "overrun" : "access violation",
217 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
218 mlx4_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
219 eqe->type);
220 break;
221
222 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
223 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
224 break;
225
226 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
227 case MLX4_EVENT_TYPE_ECC_DETECT:
228 default:
229 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u\n",
230 eqe->type, eqe->subtype, eq->eqn, eq->cons_index);
231 break;
232 };
233
234 ++eq->cons_index;
235 eqes_found = 1;
236 ++set_ci;
237
238 /*
239 * The HCA will think the queue has overflowed if we
240 * don't tell it we've been processing events. We
241 * create our EQs with MLX4_NUM_SPARE_EQE extra
242 * entries, so we must update our consumer index at
243 * least that often.
244 */
245 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
246 eq_set_ci(eq, 0);
247 set_ci = 0;
248 }
249 }
250
251 eq_set_ci(eq, 1);
252
253 return eqes_found;
254 }
255
mlx4_interrupt(int irq,void * dev_ptr)256 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
257 {
258 struct mlx4_dev *dev = dev_ptr;
259 struct mlx4_priv *priv = mlx4_priv(dev);
260 int work = 0;
261 int i;
262
263 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
264
265 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
266 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
267
268 return IRQ_RETVAL(work);
269 }
270
mlx4_msi_x_interrupt(int irq,void * eq_ptr)271 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
272 {
273 struct mlx4_eq *eq = eq_ptr;
274 struct mlx4_dev *dev = eq->dev;
275
276 mlx4_eq_int(dev, eq);
277
278 /* MSI-X vectors always belong to us */
279 return IRQ_HANDLED;
280 }
281
mlx4_MAP_EQ(struct mlx4_dev * dev,u64 event_mask,int unmap,int eq_num)282 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
283 int eq_num)
284 {
285 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
286 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B);
287 }
288
mlx4_SW2HW_EQ(struct mlx4_dev * dev,struct mlx4_cmd_mailbox * mailbox,int eq_num)289 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
290 int eq_num)
291 {
292 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, MLX4_CMD_SW2HW_EQ,
293 MLX4_CMD_TIME_CLASS_A);
294 }
295
mlx4_HW2SW_EQ(struct mlx4_dev * dev,struct mlx4_cmd_mailbox * mailbox,int eq_num)296 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
297 int eq_num)
298 {
299 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 0, MLX4_CMD_HW2SW_EQ,
300 MLX4_CMD_TIME_CLASS_A);
301 }
302
mlx4_num_eq_uar(struct mlx4_dev * dev)303 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
304 {
305 /*
306 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
307 * we need to map, take the difference of highest index and
308 * the lowest index we'll use and add 1.
309 */
310 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 -
311 dev->caps.reserved_eqs / 4 + 1;
312 }
313
mlx4_get_eq_uar(struct mlx4_dev * dev,struct mlx4_eq * eq)314 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
315 {
316 struct mlx4_priv *priv = mlx4_priv(dev);
317 int index;
318
319 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
320
321 if (!priv->eq_table.uar_map[index]) {
322 priv->eq_table.uar_map[index] =
323 ioremap(pci_resource_start(dev->pdev, 2) +
324 ((eq->eqn / 4) << PAGE_SHIFT),
325 PAGE_SIZE);
326 if (!priv->eq_table.uar_map[index]) {
327 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
328 eq->eqn);
329 return NULL;
330 }
331 }
332
333 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
334 }
335
mlx4_create_eq(struct mlx4_dev * dev,int nent,u8 intr,struct mlx4_eq * eq)336 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
337 u8 intr, struct mlx4_eq *eq)
338 {
339 struct mlx4_priv *priv = mlx4_priv(dev);
340 struct mlx4_cmd_mailbox *mailbox;
341 struct mlx4_eq_context *eq_context;
342 int npages;
343 u64 *dma_list = NULL;
344 dma_addr_t t;
345 u64 mtt_addr;
346 int err = -ENOMEM;
347 int i;
348
349 eq->dev = dev;
350 eq->nent = roundup_pow_of_two(max(nent, 2));
351 npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;
352
353 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
354 GFP_KERNEL);
355 if (!eq->page_list)
356 goto err_out;
357
358 for (i = 0; i < npages; ++i)
359 eq->page_list[i].buf = NULL;
360
361 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
362 if (!dma_list)
363 goto err_out_free;
364
365 mailbox = mlx4_alloc_cmd_mailbox(dev);
366 if (IS_ERR(mailbox))
367 goto err_out_free;
368 eq_context = mailbox->buf;
369
370 for (i = 0; i < npages; ++i) {
371 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
372 PAGE_SIZE, &t, GFP_KERNEL);
373 if (!eq->page_list[i].buf)
374 goto err_out_free_pages;
375
376 dma_list[i] = t;
377 eq->page_list[i].map = t;
378
379 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
380 }
381
382 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
383 if (eq->eqn == -1)
384 goto err_out_free_pages;
385
386 eq->doorbell = mlx4_get_eq_uar(dev, eq);
387 if (!eq->doorbell) {
388 err = -ENOMEM;
389 goto err_out_free_eq;
390 }
391
392 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
393 if (err)
394 goto err_out_free_eq;
395
396 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
397 if (err)
398 goto err_out_free_mtt;
399
400 memset(eq_context, 0, sizeof *eq_context);
401 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
402 MLX4_EQ_STATE_ARMED);
403 eq_context->log_eq_size = ilog2(eq->nent);
404 eq_context->intr = intr;
405 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
406
407 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
408 eq_context->mtt_base_addr_h = mtt_addr >> 32;
409 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
410
411 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
412 if (err) {
413 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
414 goto err_out_free_mtt;
415 }
416
417 kfree(dma_list);
418 mlx4_free_cmd_mailbox(dev, mailbox);
419
420 eq->cons_index = 0;
421
422 return err;
423
424 err_out_free_mtt:
425 mlx4_mtt_cleanup(dev, &eq->mtt);
426
427 err_out_free_eq:
428 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
429
430 err_out_free_pages:
431 for (i = 0; i < npages; ++i)
432 if (eq->page_list[i].buf)
433 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
434 eq->page_list[i].buf,
435 eq->page_list[i].map);
436
437 mlx4_free_cmd_mailbox(dev, mailbox);
438
439 err_out_free:
440 kfree(eq->page_list);
441 kfree(dma_list);
442
443 err_out:
444 return err;
445 }
446
mlx4_free_eq(struct mlx4_dev * dev,struct mlx4_eq * eq)447 static void mlx4_free_eq(struct mlx4_dev *dev,
448 struct mlx4_eq *eq)
449 {
450 struct mlx4_priv *priv = mlx4_priv(dev);
451 struct mlx4_cmd_mailbox *mailbox;
452 int err;
453 int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
454 int i;
455
456 mailbox = mlx4_alloc_cmd_mailbox(dev);
457 if (IS_ERR(mailbox))
458 return;
459
460 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
461 if (err)
462 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
463
464 if (0) {
465 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
466 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
467 if (i % 4 == 0)
468 printk("[%02x] ", i * 4);
469 printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
470 if ((i + 1) % 4 == 0)
471 printk("\n");
472 }
473 }
474
475 mlx4_mtt_cleanup(dev, &eq->mtt);
476 for (i = 0; i < npages; ++i)
477 pci_free_consistent(dev->pdev, PAGE_SIZE,
478 eq->page_list[i].buf,
479 eq->page_list[i].map);
480
481 kfree(eq->page_list);
482 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
483 mlx4_free_cmd_mailbox(dev, mailbox);
484 }
485
mlx4_free_irqs(struct mlx4_dev * dev)486 static void mlx4_free_irqs(struct mlx4_dev *dev)
487 {
488 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
489 int i;
490
491 if (eq_table->have_irq)
492 free_irq(dev->pdev->irq, dev);
493 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
494 if (eq_table->eq[i].have_irq)
495 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
496
497 kfree(eq_table->irq_names);
498 }
499
mlx4_map_clr_int(struct mlx4_dev * dev)500 static int mlx4_map_clr_int(struct mlx4_dev *dev)
501 {
502 struct mlx4_priv *priv = mlx4_priv(dev);
503
504 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
505 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
506 if (!priv->clr_base) {
507 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
508 return -ENOMEM;
509 }
510
511 return 0;
512 }
513
mlx4_unmap_clr_int(struct mlx4_dev * dev)514 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
515 {
516 struct mlx4_priv *priv = mlx4_priv(dev);
517
518 iounmap(priv->clr_base);
519 }
520
mlx4_map_eq_icm(struct mlx4_dev * dev,u64 icm_virt)521 int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt)
522 {
523 struct mlx4_priv *priv = mlx4_priv(dev);
524 int ret;
525
526 /*
527 * We assume that mapping one page is enough for the whole EQ
528 * context table. This is fine with all current HCAs, because
529 * we only use 32 EQs and each EQ uses 64 bytes of context
530 * memory, or 1 KB total.
531 */
532 priv->eq_table.icm_virt = icm_virt;
533 priv->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
534 if (!priv->eq_table.icm_page)
535 return -ENOMEM;
536 priv->eq_table.icm_dma = pci_map_page(dev->pdev, priv->eq_table.icm_page, 0,
537 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
538 if (pci_dma_mapping_error(dev->pdev, priv->eq_table.icm_dma)) {
539 __free_page(priv->eq_table.icm_page);
540 return -ENOMEM;
541 }
542
543 ret = mlx4_MAP_ICM_page(dev, priv->eq_table.icm_dma, icm_virt);
544 if (ret) {
545 pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE,
546 PCI_DMA_BIDIRECTIONAL);
547 __free_page(priv->eq_table.icm_page);
548 }
549
550 return ret;
551 }
552
mlx4_unmap_eq_icm(struct mlx4_dev * dev)553 void mlx4_unmap_eq_icm(struct mlx4_dev *dev)
554 {
555 struct mlx4_priv *priv = mlx4_priv(dev);
556
557 mlx4_UNMAP_ICM(dev, priv->eq_table.icm_virt, 1);
558 pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE,
559 PCI_DMA_BIDIRECTIONAL);
560 __free_page(priv->eq_table.icm_page);
561 }
562
mlx4_alloc_eq_table(struct mlx4_dev * dev)563 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
564 {
565 struct mlx4_priv *priv = mlx4_priv(dev);
566
567 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
568 sizeof *priv->eq_table.eq, GFP_KERNEL);
569 if (!priv->eq_table.eq)
570 return -ENOMEM;
571
572 return 0;
573 }
574
mlx4_free_eq_table(struct mlx4_dev * dev)575 void mlx4_free_eq_table(struct mlx4_dev *dev)
576 {
577 kfree(mlx4_priv(dev)->eq_table.eq);
578 }
579
mlx4_init_eq_table(struct mlx4_dev * dev)580 int mlx4_init_eq_table(struct mlx4_dev *dev)
581 {
582 struct mlx4_priv *priv = mlx4_priv(dev);
583 int err;
584 int i;
585
586 priv->eq_table.uar_map = kcalloc(sizeof *priv->eq_table.uar_map,
587 mlx4_num_eq_uar(dev), GFP_KERNEL);
588 if (!priv->eq_table.uar_map) {
589 err = -ENOMEM;
590 goto err_out_free;
591 }
592
593 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
594 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
595 if (err)
596 goto err_out_free;
597
598 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
599 priv->eq_table.uar_map[i] = NULL;
600
601 err = mlx4_map_clr_int(dev);
602 if (err)
603 goto err_out_bitmap;
604
605 priv->eq_table.clr_mask =
606 swab32(1 << (priv->eq_table.inta_pin & 31));
607 priv->eq_table.clr_int = priv->clr_base +
608 (priv->eq_table.inta_pin < 32 ? 4 : 0);
609
610 priv->eq_table.irq_names = kmalloc(16 * dev->caps.num_comp_vectors, GFP_KERNEL);
611 if (!priv->eq_table.irq_names) {
612 err = -ENOMEM;
613 goto err_out_bitmap;
614 }
615
616 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
617 err = mlx4_create_eq(dev, dev->caps.num_cqs + MLX4_NUM_SPARE_EQE,
618 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
619 &priv->eq_table.eq[i]);
620 if (err)
621 goto err_out_unmap;
622 }
623
624 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
625 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
626 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
627 if (err)
628 goto err_out_comp;
629
630 if (dev->flags & MLX4_FLAG_MSI_X) {
631 static const char async_eq_name[] = "mlx4-async";
632 const char *eq_name;
633
634 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
635 if (i < dev->caps.num_comp_vectors) {
636 snprintf(priv->eq_table.irq_names + i * 16, 16,
637 "mlx4-comp-%d", i);
638 eq_name = priv->eq_table.irq_names + i * 16;
639 } else
640 eq_name = async_eq_name;
641
642 err = request_irq(priv->eq_table.eq[i].irq,
643 mlx4_msi_x_interrupt, 0, eq_name,
644 priv->eq_table.eq + i);
645 if (err)
646 goto err_out_async;
647
648 priv->eq_table.eq[i].have_irq = 1;
649 }
650 } else {
651 err = request_irq(dev->pdev->irq, mlx4_interrupt,
652 IRQF_SHARED, DRV_NAME, dev);
653 if (err)
654 goto err_out_async;
655
656 priv->eq_table.have_irq = 1;
657 }
658
659 err = mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
660 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
661 if (err)
662 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
663 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
664
665 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
666 eq_set_ci(&priv->eq_table.eq[i], 1);
667
668 return 0;
669
670 err_out_async:
671 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
672
673 err_out_comp:
674 i = dev->caps.num_comp_vectors - 1;
675
676 err_out_unmap:
677 while (i >= 0) {
678 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
679 --i;
680 }
681 mlx4_unmap_clr_int(dev);
682 mlx4_free_irqs(dev);
683
684 err_out_bitmap:
685 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
686
687 err_out_free:
688 kfree(priv->eq_table.uar_map);
689
690 return err;
691 }
692
mlx4_cleanup_eq_table(struct mlx4_dev * dev)693 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
694 {
695 struct mlx4_priv *priv = mlx4_priv(dev);
696 int i;
697
698 mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 1,
699 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
700
701 mlx4_free_irqs(dev);
702
703 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
704 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
705
706 mlx4_unmap_clr_int(dev);
707
708 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
709 if (priv->eq_table.uar_map[i])
710 iounmap(priv->eq_table.uar_map[i]);
711
712 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
713
714 kfree(priv->eq_table.uar_map);
715 }
716