1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36
37 #include <linux/compiler.h>
38 #include <linux/list.h>
39 #include <linux/mutex.h>
40 #include <linux/netdevice.h>
41 #include <linux/inet_lro.h>
42
43 #include <linux/mlx4/device.h>
44 #include <linux/mlx4/qp.h>
45 #include <linux/mlx4/cq.h>
46 #include <linux/mlx4/srq.h>
47 #include <linux/mlx4/doorbell.h>
48
49 #include "en_port.h"
50
51 #define DRV_NAME "mlx4_en"
52 #define DRV_VERSION "1.4.0"
53 #define DRV_RELDATE "Sep 2008"
54
55
56 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
57
58 #define mlx4_dbg(mlevel, priv, format, arg...) \
59 if (NETIF_MSG_##mlevel & priv->msg_enable) \
60 printk(KERN_DEBUG "%s %s: " format , DRV_NAME ,\
61 (dev_name(&priv->mdev->pdev->dev)) , ## arg)
62
63 #define mlx4_err(mdev, format, arg...) \
64 printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
65 (dev_name(&mdev->pdev->dev)) , ## arg)
66 #define mlx4_info(mdev, format, arg...) \
67 printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
68 (dev_name(&mdev->pdev->dev)) , ## arg)
69 #define mlx4_warn(mdev, format, arg...) \
70 printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
71 (dev_name(&mdev->pdev->dev)) , ## arg)
72
73 /*
74 * Device constants
75 */
76
77
78 #define MLX4_EN_PAGE_SHIFT 12
79 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
80 #define MAX_TX_RINGS 16
81 #define MAX_RX_RINGS 16
82 #define MAX_RSS_MAP_SIZE 64
83 #define RSS_FACTOR 2
84 #define TXBB_SIZE 64
85 #define HEADROOM (2048 / TXBB_SIZE + 1)
86 #define MAX_LSO_HDR_SIZE 92
87 #define STAMP_STRIDE 64
88 #define STAMP_DWORDS (STAMP_STRIDE / 4)
89 #define STAMP_SHIFT 31
90 #define STAMP_VAL 0x7fffffff
91 #define STATS_DELAY (HZ / 4)
92
93 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
94 #define MAX_DESC_SIZE 512
95 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
96
97 /*
98 * OS related constants and tunables
99 */
100
101 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
102
103 #define MLX4_EN_ALLOC_ORDER 2
104 #define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
105
106 #define MLX4_EN_MAX_LRO_DESCRIPTORS 32
107
108 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
109 * and 4K allocations) */
110 enum {
111 FRAG_SZ0 = 512 - NET_IP_ALIGN,
112 FRAG_SZ1 = 1024,
113 FRAG_SZ2 = 4096,
114 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
115 };
116 #define MLX4_EN_MAX_RX_FRAGS 4
117
118 /* Maximum ring sizes */
119 #define MLX4_EN_MAX_TX_SIZE 8192
120 #define MLX4_EN_MAX_RX_SIZE 8192
121
122 /* Minimum ring size for our page-allocation sceme to work */
123 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
124 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
125
126 #define MLX4_EN_TX_RING_NUM 9
127 #define MLX4_EN_DEF_TX_RING_SIZE 1024
128 #define MLX4_EN_DEF_RX_RING_SIZE 1024
129
130 /* Target number of bytes to coalesce with interrupt moderation */
131 #define MLX4_EN_RX_COAL_TARGET 0x20000
132 #define MLX4_EN_RX_COAL_TIME 0x10
133
134 #define MLX4_EN_TX_COAL_PKTS 5
135 #define MLX4_EN_TX_COAL_TIME 0x80
136
137 #define MLX4_EN_RX_RATE_LOW 400000
138 #define MLX4_EN_RX_COAL_TIME_LOW 0
139 #define MLX4_EN_RX_RATE_HIGH 450000
140 #define MLX4_EN_RX_COAL_TIME_HIGH 128
141 #define MLX4_EN_RX_SIZE_THRESH 1024
142 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
143 #define MLX4_EN_SAMPLE_INTERVAL 0
144
145 #define MLX4_EN_AUTO_CONF 0xffff
146
147 #define MLX4_EN_DEF_RX_PAUSE 1
148 #define MLX4_EN_DEF_TX_PAUSE 1
149
150 /* Interval between sucessive polls in the Tx routine when polling is used
151 instead of interrupts (in per-core Tx rings) - should be power of 2 */
152 #define MLX4_EN_TX_POLL_MODER 16
153 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
154
155 #define ETH_LLC_SNAP_SIZE 8
156
157 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
158 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
159
160 #define MLX4_EN_MIN_MTU 46
161 #define ETH_BCAST 0xffffffffffffULL
162
163 #ifdef MLX4_EN_PERF_STAT
164 /* Number of samples to 'average' */
165 #define AVG_SIZE 128
166 #define AVG_FACTOR 1024
167 #define NUM_PERF_STATS NUM_PERF_COUNTERS
168
169 #define INC_PERF_COUNTER(cnt) (++(cnt))
170 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
171 #define AVG_PERF_COUNTER(cnt, sample) \
172 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
173 #define GET_PERF_COUNTER(cnt) (cnt)
174 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
175
176 #else
177
178 #define NUM_PERF_STATS 0
179 #define INC_PERF_COUNTER(cnt) do {} while (0)
180 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
181 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
182 #define GET_PERF_COUNTER(cnt) (0)
183 #define GET_AVG_PERF_COUNTER(cnt) (0)
184 #endif /* MLX4_EN_PERF_STAT */
185
186 /*
187 * Configurables
188 */
189
190 enum cq_type {
191 RX = 0,
192 TX = 1,
193 };
194
195
196 /*
197 * Useful macros
198 */
199 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
200 #define XNOR(x, y) (!(x) == !(y))
201 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
202
203
204 struct mlx4_en_tx_info {
205 struct sk_buff *skb;
206 u32 nr_txbb;
207 u8 linear;
208 u8 data_offset;
209 u8 inl;
210 };
211
212
213 #define MLX4_EN_BIT_DESC_OWN 0x80000000
214 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
215 #define MLX4_EN_MEMTYPE_PAD 0x100
216 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
217
218
219 struct mlx4_en_tx_desc {
220 struct mlx4_wqe_ctrl_seg ctrl;
221 union {
222 struct mlx4_wqe_data_seg data; /* at least one data segment */
223 struct mlx4_wqe_lso_seg lso;
224 struct mlx4_wqe_inline_seg inl;
225 };
226 };
227
228 #define MLX4_EN_USE_SRQ 0x01000000
229
230 struct mlx4_en_rx_alloc {
231 struct page *page;
232 u16 offset;
233 };
234
235 struct mlx4_en_tx_ring {
236 struct mlx4_hwq_resources wqres;
237 u32 size ; /* number of TXBBs */
238 u32 size_mask;
239 u16 stride;
240 u16 cqn; /* index of port CQ associated with this ring */
241 u32 prod;
242 u32 cons;
243 u32 buf_size;
244 u32 doorbell_qpn;
245 void *buf;
246 u16 poll_cnt;
247 int blocked;
248 struct mlx4_en_tx_info *tx_info;
249 u8 *bounce_buf;
250 u32 last_nr_txbb;
251 struct mlx4_qp qp;
252 struct mlx4_qp_context context;
253 int qpn;
254 enum mlx4_qp_state qp_state;
255 struct mlx4_srq dummy;
256 unsigned long bytes;
257 unsigned long packets;
258 spinlock_t comp_lock;
259 };
260
261 struct mlx4_en_rx_desc {
262 struct mlx4_wqe_srq_next_seg next;
263 /* actual number of entries depends on rx ring stride */
264 struct mlx4_wqe_data_seg data[0];
265 };
266
267 struct mlx4_en_rx_ring {
268 struct mlx4_srq srq;
269 struct mlx4_hwq_resources wqres;
270 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
271 struct net_lro_mgr lro;
272 u32 size ; /* number of Rx descs*/
273 u32 actual_size;
274 u32 size_mask;
275 u16 stride;
276 u16 log_stride;
277 u16 cqn; /* index of port CQ associated with this ring */
278 u32 prod;
279 u32 cons;
280 u32 buf_size;
281 int need_refill;
282 int full;
283 void *buf;
284 void *rx_info;
285 unsigned long bytes;
286 unsigned long packets;
287 };
288
289
mlx4_en_can_lro(__be16 status)290 static inline int mlx4_en_can_lro(__be16 status)
291 {
292 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
293 MLX4_CQE_STATUS_IPV4F |
294 MLX4_CQE_STATUS_IPV6 |
295 MLX4_CQE_STATUS_IPV4OPT |
296 MLX4_CQE_STATUS_TCP |
297 MLX4_CQE_STATUS_UDP |
298 MLX4_CQE_STATUS_IPOK)) ==
299 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
300 MLX4_CQE_STATUS_IPOK |
301 MLX4_CQE_STATUS_TCP);
302 }
303
304 struct mlx4_en_cq {
305 struct mlx4_cq mcq;
306 struct mlx4_hwq_resources wqres;
307 int ring;
308 spinlock_t lock;
309 struct net_device *dev;
310 struct napi_struct napi;
311 /* Per-core Tx cq processing support */
312 struct timer_list timer;
313 int size;
314 int buf_size;
315 unsigned vector;
316 enum cq_type is_tx;
317 u16 moder_time;
318 u16 moder_cnt;
319 struct mlx4_cqe *buf;
320 #define MLX4_EN_OPCODE_ERROR 0x1e
321 };
322
323 struct mlx4_en_port_profile {
324 u32 flags;
325 u32 tx_ring_num;
326 u32 rx_ring_num;
327 u32 tx_ring_size;
328 u32 rx_ring_size;
329 u8 rx_pause;
330 u8 rx_ppp;
331 u8 tx_pause;
332 u8 tx_ppp;
333 };
334
335 struct mlx4_en_profile {
336 int rss_xor;
337 int num_lro;
338 u8 rss_mask;
339 u32 active_ports;
340 u32 small_pkt_int;
341 u8 no_reset;
342 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
343 };
344
345 struct mlx4_en_dev {
346 struct mlx4_dev *dev;
347 struct pci_dev *pdev;
348 struct mutex state_lock;
349 struct net_device *pndev[MLX4_MAX_PORTS + 1];
350 u32 port_cnt;
351 bool device_up;
352 struct mlx4_en_profile profile;
353 u32 LSO_support;
354 struct workqueue_struct *workqueue;
355 struct device *dma_device;
356 void __iomem *uar_map;
357 struct mlx4_uar priv_uar;
358 struct mlx4_mr mr;
359 u32 priv_pdn;
360 spinlock_t uar_lock;
361 };
362
363
364 struct mlx4_en_rss_map {
365 int size;
366 int base_qpn;
367 u16 map[MAX_RSS_MAP_SIZE];
368 struct mlx4_qp qps[MAX_RSS_MAP_SIZE];
369 enum mlx4_qp_state state[MAX_RSS_MAP_SIZE];
370 struct mlx4_qp indir_qp;
371 enum mlx4_qp_state indir_state;
372 };
373
374 struct mlx4_en_rss_context {
375 __be32 base_qpn;
376 __be32 default_qpn;
377 u16 reserved;
378 u8 hash_fn;
379 u8 flags;
380 __be32 rss_key[10];
381 };
382
383 struct mlx4_en_pkt_stats {
384 unsigned long broadcast;
385 unsigned long rx_prio[8];
386 unsigned long tx_prio[8];
387 #define NUM_PKT_STATS 17
388 };
389
390 struct mlx4_en_port_stats {
391 unsigned long lro_aggregated;
392 unsigned long lro_flushed;
393 unsigned long lro_no_desc;
394 unsigned long tso_packets;
395 unsigned long queue_stopped;
396 unsigned long wake_queue;
397 unsigned long tx_timeout;
398 unsigned long rx_alloc_failed;
399 unsigned long rx_chksum_good;
400 unsigned long rx_chksum_none;
401 unsigned long tx_chksum_offload;
402 #define NUM_PORT_STATS 11
403 };
404
405 struct mlx4_en_perf_stats {
406 u32 tx_poll;
407 u64 tx_pktsz_avg;
408 u32 inflight_avg;
409 u16 tx_coal_avg;
410 u16 rx_coal_avg;
411 u32 napi_quota;
412 #define NUM_PERF_COUNTERS 6
413 };
414
415 struct mlx4_en_frag_info {
416 u16 frag_size;
417 u16 frag_prefix_size;
418 u16 frag_stride;
419 u16 frag_align;
420 u16 last_offset;
421
422 };
423
424 struct mlx4_en_priv {
425 struct mlx4_en_dev *mdev;
426 struct mlx4_en_port_profile *prof;
427 struct net_device *dev;
428 struct vlan_group *vlgrp;
429 struct net_device_stats stats;
430 struct net_device_stats ret_stats;
431 spinlock_t stats_lock;
432
433 unsigned long last_moder_packets;
434 unsigned long last_moder_tx_packets;
435 unsigned long last_moder_bytes;
436 unsigned long last_moder_jiffies;
437 int last_moder_time;
438 u16 rx_usecs;
439 u16 rx_frames;
440 u16 tx_usecs;
441 u16 tx_frames;
442 u32 pkt_rate_low;
443 u16 rx_usecs_low;
444 u32 pkt_rate_high;
445 u16 rx_usecs_high;
446 u16 sample_interval;
447 u16 adaptive_rx_coal;
448 u32 msg_enable;
449
450 struct mlx4_hwq_resources res;
451 int link_state;
452 int last_link_state;
453 bool port_up;
454 int port;
455 int registered;
456 int allocated;
457 int stride;
458 int rx_csum;
459 u64 mac;
460 int mac_index;
461 unsigned max_mtu;
462 int base_qpn;
463
464 struct mlx4_en_rss_map rss_map;
465 u16 tx_prio_map[8];
466 u32 flags;
467 #define MLX4_EN_FLAG_PROMISC 0x1
468 u32 tx_ring_num;
469 u32 rx_ring_num;
470 u32 rx_skb_size;
471 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
472 u16 num_frags;
473 u16 log_rx_info;
474
475 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
476 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
477 struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
478 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
479 struct work_struct mcast_task;
480 struct work_struct mac_task;
481 struct delayed_work refill_task;
482 struct work_struct watchdog_task;
483 struct work_struct linkstate_task;
484 struct delayed_work stats_task;
485 struct mlx4_en_perf_stats pstats;
486 struct mlx4_en_pkt_stats pkstats;
487 struct mlx4_en_port_stats port_stats;
488 struct dev_mc_list *mc_list;
489 struct mlx4_en_stat_out_mbox hw_stats;
490 };
491
492
493 void mlx4_en_destroy_netdev(struct net_device *dev);
494 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
495 struct mlx4_en_port_profile *prof);
496
497 int mlx4_en_start_port(struct net_device *dev);
498 void mlx4_en_stop_port(struct net_device *dev);
499
500 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
501 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
502
503 int mlx4_en_get_profile(struct mlx4_en_dev *mdev);
504
505 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
506 int entries, int ring, enum cq_type mode);
507 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
508 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
509 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
510 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
511 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
512
513 void mlx4_en_poll_tx_cq(unsigned long data);
514 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
515 int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
516
517 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
518 u32 size, u16 stride);
519 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
520 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
521 struct mlx4_en_tx_ring *ring,
522 int cq, int srqn);
523 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
524 struct mlx4_en_tx_ring *ring);
525
526 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
527 struct mlx4_en_rx_ring *ring,
528 u32 size, u16 stride);
529 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
530 struct mlx4_en_rx_ring *ring);
531 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
532 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
533 struct mlx4_en_rx_ring *ring);
534 int mlx4_en_process_rx_cq(struct net_device *dev,
535 struct mlx4_en_cq *cq,
536 int budget);
537 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
538 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
539 int is_tx, int rss, int qpn, int cqn, int srqn,
540 struct mlx4_qp_context *context);
541 int mlx4_en_map_buffer(struct mlx4_buf *buf);
542 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
543
544 void mlx4_en_calc_rx_buf(struct net_device *dev);
545 void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
546 struct mlx4_en_rss_map *rss_map,
547 int num_entries, int num_rings);
548 void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num);
549 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
550 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
551 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
552 void mlx4_en_rx_refill(struct work_struct *work);
553 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
554
555 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
556 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
557 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
558 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
559 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
560 u8 promisc);
561
562 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
563
564 /*
565 * Globals
566 */
567 extern const struct ethtool_ops mlx4_en_ethtool_ops;
568 #endif
569