1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
37
38
39 #include <net/ip.h>
40
41 #define MASK(n) ((1ULL<<(n))-1)
42 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44 #define MS_WIN(addr) (addr & 0x0ffc0000)
45
46 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
47
48 #define CRB_BLK(off) ((off >> 20) & 0x3f)
49 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50 #define CRB_WINDOW_2M (0x130060)
51 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52 #define CRB_INDIRECT_2M (0x1e0000UL)
53
54 #define CRB_WIN_LOCK_TIMEOUT 100000000
55 static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
181 {{{0} } }, /* 35: */
182 {{{0} } }, /* 36: */
183 {{{0} } }, /* 37: */
184 {{{0} } }, /* 38: */
185 {{{0} } }, /* 39: */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
198 {{{0} } }, /* 52: */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
210 };
211
212 /*
213 * top 12 bits of crb internal address (hub, agent)
214 */
215 static unsigned crb_hub_agt[64] =
216 {
217 0,
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
221 0,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
244 0,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
249 0,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
252 0,
253 0,
254 0,
255 0,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
278 0,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
280 0,
281 };
282
283 /* PCI Windowing for DDR regions. */
284
285 #define ADDR_IN_RANGE(addr, low, high) \
286 (((addr) <= (high)) && ((addr) >= (low)))
287
288 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
289
290 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
291 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
292 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
293 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
294
295 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
296
netxen_nic_set_mac(struct net_device * netdev,void * p)297 int netxen_nic_set_mac(struct net_device *netdev, void *p)
298 {
299 struct netxen_adapter *adapter = netdev_priv(netdev);
300 struct sockaddr *addr = p;
301
302 if (netif_running(netdev))
303 return -EBUSY;
304
305 if (!is_valid_ether_addr(addr->sa_data))
306 return -EADDRNOTAVAIL;
307
308 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
309
310 /* For P3, MAC addr is not set in NIU */
311 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
312 if (adapter->macaddr_set)
313 adapter->macaddr_set(adapter, addr->sa_data);
314
315 return 0;
316 }
317
318 #define NETXEN_UNICAST_ADDR(port, index) \
319 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
320 #define NETXEN_MCAST_ADDR(port, index) \
321 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
322 #define MAC_HI(addr) \
323 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
324 #define MAC_LO(addr) \
325 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
326
327 static int
netxen_nic_enable_mcast_filter(struct netxen_adapter * adapter)328 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
329 {
330 u32 val = 0;
331 u16 port = adapter->physical_port;
332 u8 *addr = adapter->netdev->dev_addr;
333
334 if (adapter->mc_enabled)
335 return 0;
336
337 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
338 val |= (1UL << (28+port));
339 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
340
341 /* add broadcast addr to filter */
342 val = 0xffffff;
343 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
344 netxen_crb_writelit_adapter(adapter,
345 NETXEN_UNICAST_ADDR(port, 0)+4, val);
346
347 /* add station addr to filter */
348 val = MAC_HI(addr);
349 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
350 val = MAC_LO(addr);
351 netxen_crb_writelit_adapter(adapter,
352 NETXEN_UNICAST_ADDR(port, 1)+4, val);
353
354 adapter->mc_enabled = 1;
355 return 0;
356 }
357
358 static int
netxen_nic_disable_mcast_filter(struct netxen_adapter * adapter)359 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
360 {
361 u32 val = 0;
362 u16 port = adapter->physical_port;
363 u8 *addr = adapter->netdev->dev_addr;
364
365 if (!adapter->mc_enabled)
366 return 0;
367
368 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
369 val &= ~(1UL << (28+port));
370 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
371
372 val = MAC_HI(addr);
373 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
374 val = MAC_LO(addr);
375 netxen_crb_writelit_adapter(adapter,
376 NETXEN_UNICAST_ADDR(port, 0)+4, val);
377
378 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
379 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
380
381 adapter->mc_enabled = 0;
382 return 0;
383 }
384
385 static int
netxen_nic_set_mcast_addr(struct netxen_adapter * adapter,int index,u8 * addr)386 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
387 int index, u8 *addr)
388 {
389 u32 hi = 0, lo = 0;
390 u16 port = adapter->physical_port;
391
392 lo = MAC_LO(addr);
393 hi = MAC_HI(addr);
394
395 netxen_crb_writelit_adapter(adapter,
396 NETXEN_MCAST_ADDR(port, index), hi);
397 netxen_crb_writelit_adapter(adapter,
398 NETXEN_MCAST_ADDR(port, index)+4, lo);
399
400 return 0;
401 }
402
netxen_p2_nic_set_multi(struct net_device * netdev)403 void netxen_p2_nic_set_multi(struct net_device *netdev)
404 {
405 struct netxen_adapter *adapter = netdev_priv(netdev);
406 struct dev_mc_list *mc_ptr;
407 u8 null_addr[6];
408 int index = 0;
409
410 memset(null_addr, 0, 6);
411
412 if (netdev->flags & IFF_PROMISC) {
413
414 adapter->set_promisc(adapter,
415 NETXEN_NIU_PROMISC_MODE);
416
417 /* Full promiscuous mode */
418 netxen_nic_disable_mcast_filter(adapter);
419
420 return;
421 }
422
423 if (netdev->mc_count == 0) {
424 adapter->set_promisc(adapter,
425 NETXEN_NIU_NON_PROMISC_MODE);
426 netxen_nic_disable_mcast_filter(adapter);
427 return;
428 }
429
430 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
431 if (netdev->flags & IFF_ALLMULTI ||
432 netdev->mc_count > adapter->max_mc_count) {
433 netxen_nic_disable_mcast_filter(adapter);
434 return;
435 }
436
437 netxen_nic_enable_mcast_filter(adapter);
438
439 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
440 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
441
442 if (index != netdev->mc_count)
443 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
444 netxen_nic_driver_name, netdev->name);
445
446 /* Clear out remaining addresses */
447 for (; index < adapter->max_mc_count; index++)
448 netxen_nic_set_mcast_addr(adapter, index, null_addr);
449 }
450
nx_p3_nic_add_mac(struct netxen_adapter * adapter,u8 * addr,nx_mac_list_t ** add_list,nx_mac_list_t ** del_list)451 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
452 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
453 {
454 nx_mac_list_t *cur, *prev;
455
456 /* if in del_list, move it to adapter->mac_list */
457 for (cur = *del_list, prev = NULL; cur;) {
458 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
459 if (prev == NULL)
460 *del_list = cur->next;
461 else
462 prev->next = cur->next;
463 cur->next = adapter->mac_list;
464 adapter->mac_list = cur;
465 return 0;
466 }
467 prev = cur;
468 cur = cur->next;
469 }
470
471 /* make sure to add each mac address only once */
472 for (cur = adapter->mac_list; cur; cur = cur->next) {
473 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
474 return 0;
475 }
476 /* not in del_list, create new entry and add to add_list */
477 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
478 if (cur == NULL) {
479 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
480 "not work properly from now.\n", __func__);
481 return -1;
482 }
483
484 memcpy(cur->mac_addr, addr, ETH_ALEN);
485 cur->next = *add_list;
486 *add_list = cur;
487 return 0;
488 }
489
490 static int
netxen_send_cmd_descs(struct netxen_adapter * adapter,struct cmd_desc_type0 * cmd_desc_arr,int nr_elements)491 netxen_send_cmd_descs(struct netxen_adapter *adapter,
492 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
493 {
494 uint32_t i, producer;
495 struct netxen_cmd_buffer *pbuf;
496 struct cmd_desc_type0 *cmd_desc;
497
498 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
499 printk(KERN_WARNING "%s: Too many command descriptors in a "
500 "request\n", __func__);
501 return -EINVAL;
502 }
503
504 i = 0;
505
506 netif_tx_lock_bh(adapter->netdev);
507
508 producer = adapter->cmd_producer;
509 do {
510 cmd_desc = &cmd_desc_arr[i];
511
512 pbuf = &adapter->cmd_buf_arr[producer];
513 pbuf->skb = NULL;
514 pbuf->frag_count = 0;
515
516 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
517 memcpy(&adapter->ahw.cmd_desc_head[producer],
518 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
519
520 producer = get_next_index(producer,
521 adapter->max_tx_desc_count);
522 i++;
523
524 } while (i != nr_elements);
525
526 adapter->cmd_producer = producer;
527
528 /* write producer index to start the xmit */
529
530 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
531
532 netif_tx_unlock_bh(adapter->netdev);
533
534 return 0;
535 }
536
nx_p3_sre_macaddr_change(struct net_device * dev,u8 * addr,unsigned op)537 static int nx_p3_sre_macaddr_change(struct net_device *dev,
538 u8 *addr, unsigned op)
539 {
540 struct netxen_adapter *adapter = netdev_priv(dev);
541 nx_nic_req_t req;
542 nx_mac_req_t *mac_req;
543 u64 word;
544 int rv;
545
546 memset(&req, 0, sizeof(nx_nic_req_t));
547 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
548
549 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
550 req.req_hdr = cpu_to_le64(word);
551
552 mac_req = (nx_mac_req_t *)&req.words[0];
553 mac_req->op = op;
554 memcpy(mac_req->mac_addr, addr, 6);
555
556 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
557 if (rv != 0) {
558 printk(KERN_ERR "ERROR. Could not send mac update\n");
559 return rv;
560 }
561
562 return 0;
563 }
564
netxen_p3_nic_set_multi(struct net_device * netdev)565 void netxen_p3_nic_set_multi(struct net_device *netdev)
566 {
567 struct netxen_adapter *adapter = netdev_priv(netdev);
568 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
569 struct dev_mc_list *mc_ptr;
570 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
571 u32 mode = VPORT_MISS_MODE_DROP;
572
573 del_list = adapter->mac_list;
574 adapter->mac_list = NULL;
575
576 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
577 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
578
579 if (netdev->flags & IFF_PROMISC) {
580 mode = VPORT_MISS_MODE_ACCEPT_ALL;
581 goto send_fw_cmd;
582 }
583
584 if ((netdev->flags & IFF_ALLMULTI) ||
585 (netdev->mc_count > adapter->max_mc_count)) {
586 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
587 goto send_fw_cmd;
588 }
589
590 if (netdev->mc_count > 0) {
591 for (mc_ptr = netdev->mc_list; mc_ptr;
592 mc_ptr = mc_ptr->next) {
593 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
594 &add_list, &del_list);
595 }
596 }
597
598 send_fw_cmd:
599 adapter->set_promisc(adapter, mode);
600 for (cur = del_list; cur;) {
601 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
602 next = cur->next;
603 kfree(cur);
604 cur = next;
605 }
606 for (cur = add_list; cur;) {
607 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
608 next = cur->next;
609 cur->next = adapter->mac_list;
610 adapter->mac_list = cur;
611 cur = next;
612 }
613 }
614
netxen_p3_nic_set_promisc(struct netxen_adapter * adapter,u32 mode)615 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
616 {
617 nx_nic_req_t req;
618 u64 word;
619
620 memset(&req, 0, sizeof(nx_nic_req_t));
621
622 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
623
624 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
625 ((u64)adapter->portnum << 16);
626 req.req_hdr = cpu_to_le64(word);
627
628 req.words[0] = cpu_to_le64(mode);
629
630 return netxen_send_cmd_descs(adapter,
631 (struct cmd_desc_type0 *)&req, 1);
632 }
633
netxen_p3_free_mac_list(struct netxen_adapter * adapter)634 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
635 {
636 nx_mac_list_t *cur, *next;
637
638 cur = adapter->mac_list;
639
640 while (cur) {
641 next = cur->next;
642 kfree(cur);
643 cur = next;
644 }
645 }
646
647 #define NETXEN_CONFIG_INTR_COALESCE 3
648
649 /*
650 * Send the interrupt coalescing parameter set by ethtool to the card.
651 */
netxen_config_intr_coalesce(struct netxen_adapter * adapter)652 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
653 {
654 nx_nic_req_t req;
655 u64 word;
656 int rv;
657
658 memset(&req, 0, sizeof(nx_nic_req_t));
659
660 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
661
662 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
663 req.req_hdr = cpu_to_le64(word);
664
665 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
666
667 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
668 if (rv != 0) {
669 printk(KERN_ERR "ERROR. Could not send "
670 "interrupt coalescing parameters\n");
671 }
672
673 return rv;
674 }
675
676 /*
677 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
678 * @returns 0 on success, negative on failure
679 */
680
681 #define MTU_FUDGE_FACTOR 100
682
netxen_nic_change_mtu(struct net_device * netdev,int mtu)683 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
684 {
685 struct netxen_adapter *adapter = netdev_priv(netdev);
686 int max_mtu;
687 int rc = 0;
688
689 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
690 max_mtu = P3_MAX_MTU;
691 else
692 max_mtu = P2_MAX_MTU;
693
694 if (mtu > max_mtu) {
695 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
696 netdev->name, max_mtu);
697 return -EINVAL;
698 }
699
700 if (adapter->set_mtu)
701 rc = adapter->set_mtu(adapter, mtu);
702
703 if (!rc)
704 netdev->mtu = mtu;
705
706 return rc;
707 }
708
netxen_get_flash_block(struct netxen_adapter * adapter,int base,int size,__le32 * buf)709 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
710 int size, __le32 * buf)
711 {
712 int i, addr;
713 __le32 *ptr32;
714 u32 v;
715
716 addr = base;
717 ptr32 = buf;
718 for (i = 0; i < size / sizeof(u32); i++) {
719 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
720 return -1;
721 *ptr32 = cpu_to_le32(v);
722 ptr32++;
723 addr += sizeof(u32);
724 }
725 if ((char *)buf + size > (char *)ptr32) {
726 __le32 local;
727 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
728 return -1;
729 local = cpu_to_le32(v);
730 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
731 }
732
733 return 0;
734 }
735
netxen_get_flash_mac_addr(struct netxen_adapter * adapter,__le64 * mac)736 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
737 {
738 __le32 *pmac = (__le32 *) mac;
739 u32 offset;
740
741 offset = NETXEN_USER_START +
742 offsetof(struct netxen_new_user_info, mac_addr) +
743 adapter->portnum * sizeof(u64);
744
745 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
746 return -1;
747
748 if (*mac == cpu_to_le64(~0ULL)) {
749
750 offset = NETXEN_USER_START_OLD +
751 offsetof(struct netxen_user_old_info, mac_addr) +
752 adapter->portnum * sizeof(u64);
753
754 if (netxen_get_flash_block(adapter,
755 offset, sizeof(u64), pmac) == -1)
756 return -1;
757
758 if (*mac == cpu_to_le64(~0ULL))
759 return -1;
760 }
761 return 0;
762 }
763
netxen_p3_get_mac_addr(struct netxen_adapter * adapter,__le64 * mac)764 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
765 {
766 uint32_t crbaddr, mac_hi, mac_lo;
767 int pci_func = adapter->ahw.pci_func;
768
769 crbaddr = CRB_MAC_BLOCK_START +
770 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
771
772 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4);
773 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4);
774
775 if (pci_func & 1)
776 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
777 else
778 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
779
780 return 0;
781 }
782
783 #define CRB_WIN_LOCK_TIMEOUT 100000000
784
crb_win_lock(struct netxen_adapter * adapter)785 static int crb_win_lock(struct netxen_adapter *adapter)
786 {
787 int done = 0, timeout = 0;
788
789 while (!done) {
790 /* acquire semaphore3 from PCI HW block */
791 adapter->hw_read_wx(adapter,
792 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
793 if (done == 1)
794 break;
795 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
796 return -1;
797 timeout++;
798 udelay(1);
799 }
800 netxen_crb_writelit_adapter(adapter,
801 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
802 return 0;
803 }
804
crb_win_unlock(struct netxen_adapter * adapter)805 static void crb_win_unlock(struct netxen_adapter *adapter)
806 {
807 int val;
808
809 adapter->hw_read_wx(adapter,
810 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
811 }
812
813 /*
814 * Changes the CRB window to the specified window.
815 */
816 void
netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter * adapter,u32 wndw)817 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
818 {
819 void __iomem *offset;
820 u32 tmp;
821 int count = 0;
822 uint8_t func = adapter->ahw.pci_func;
823
824 if (adapter->curr_window == wndw)
825 return;
826 /*
827 * Move the CRB window.
828 * We need to write to the "direct access" region of PCI
829 * to avoid a race condition where the window register has
830 * not been successfully written across CRB before the target
831 * register address is received by PCI. The direct region bypasses
832 * the CRB bus.
833 */
834 offset = PCI_OFFSET_SECOND_RANGE(adapter,
835 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
836
837 if (wndw & 0x1)
838 wndw = NETXEN_WINDOW_ONE;
839
840 writel(wndw, offset);
841
842 /* MUST make sure window is set before we forge on... */
843 while ((tmp = readl(offset)) != wndw) {
844 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
845 "registered properly: 0x%08x.\n",
846 netxen_nic_driver_name, __func__, tmp);
847 mdelay(1);
848 if (count >= 10)
849 break;
850 count++;
851 }
852
853 if (wndw == NETXEN_WINDOW_ONE)
854 adapter->curr_window = 1;
855 else
856 adapter->curr_window = 0;
857 }
858
859 /*
860 * Return -1 if off is not valid,
861 * 1 if window access is needed. 'off' is set to offset from
862 * CRB space in 128M pci map
863 * 0 if no window access is needed. 'off' is set to 2M addr
864 * In: 'off' is offset from base in 128M pci map
865 */
866 static int
netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter * adapter,ulong * off,int len)867 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
868 ulong *off, int len)
869 {
870 unsigned long end = *off + len;
871 crb_128M_2M_sub_block_map_t *m;
872
873
874 if (*off >= NETXEN_CRB_MAX)
875 return -1;
876
877 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
878 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
879 (ulong)adapter->ahw.pci_base0;
880 return 0;
881 }
882
883 if (*off < NETXEN_PCI_CRBSPACE)
884 return -1;
885
886 *off -= NETXEN_PCI_CRBSPACE;
887 end = *off + len;
888
889 /*
890 * Try direct map
891 */
892 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
893
894 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
895 *off = *off + m->start_2M - m->start_128M +
896 (ulong)adapter->ahw.pci_base0;
897 return 0;
898 }
899
900 /*
901 * Not in direct map, use crb window
902 */
903 return 1;
904 }
905
906 /*
907 * In: 'off' is offset from CRB space in 128M pci map
908 * Out: 'off' is 2M pci map addr
909 * side effect: lock crb window
910 */
911 static void
netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter * adapter,ulong * off)912 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
913 {
914 u32 win_read;
915
916 adapter->crb_win = CRB_HI(*off);
917 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
918 adapter->ahw.pci_base0));
919 /*
920 * Read back value to make sure write has gone through before trying
921 * to use it.
922 */
923 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
924 if (win_read != adapter->crb_win) {
925 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
926 "Read crbwin (0x%x), off=0x%lx\n",
927 __func__, adapter->crb_win, win_read, *off);
928 }
929 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
930 (ulong)adapter->ahw.pci_base0;
931 }
932
netxen_load_firmware(struct netxen_adapter * adapter)933 int netxen_load_firmware(struct netxen_adapter *adapter)
934 {
935 int i;
936 u32 data, size = 0;
937 u32 flashaddr = NETXEN_BOOTLD_START;
938
939 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4;
940
941 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
942 adapter->pci_write_normalize(adapter,
943 NETXEN_ROMUSB_GLB_CAS_RST, 1);
944
945 for (i = 0; i < size; i++) {
946 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
947 return -EIO;
948
949 adapter->pci_mem_write(adapter, flashaddr, &data, 4);
950 flashaddr += 4;
951 }
952 msleep(1);
953
954 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
955 adapter->pci_write_normalize(adapter,
956 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
957 else {
958 adapter->pci_write_normalize(adapter,
959 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
960 adapter->pci_write_normalize(adapter,
961 NETXEN_ROMUSB_GLB_CAS_RST, 0);
962 }
963
964 return 0;
965 }
966
967 int
netxen_nic_hw_write_wx_128M(struct netxen_adapter * adapter,ulong off,void * data,int len)968 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
969 ulong off, void *data, int len)
970 {
971 void __iomem *addr;
972
973 if (ADDR_IN_WINDOW1(off)) {
974 addr = NETXEN_CRB_NORMALIZE(adapter, off);
975 } else { /* Window 0 */
976 addr = pci_base_offset(adapter, off);
977 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
978 }
979
980 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
981 " data %llx len %d\n",
982 pci_base(adapter, off), off, addr,
983 *(unsigned long long *)data, len);
984 if (!addr) {
985 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
986 return 1;
987 }
988
989 switch (len) {
990 case 1:
991 writeb(*(u8 *) data, addr);
992 break;
993 case 2:
994 writew(*(u16 *) data, addr);
995 break;
996 case 4:
997 writel(*(u32 *) data, addr);
998 break;
999 case 8:
1000 writeq(*(u64 *) data, addr);
1001 break;
1002 default:
1003 DPRINTK(INFO,
1004 "writing data %lx to offset %llx, num words=%d\n",
1005 *(unsigned long *)data, off, (len >> 3));
1006
1007 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
1008 (len >> 3));
1009 break;
1010 }
1011 if (!ADDR_IN_WINDOW1(off))
1012 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1013
1014 return 0;
1015 }
1016
1017 int
netxen_nic_hw_read_wx_128M(struct netxen_adapter * adapter,ulong off,void * data,int len)1018 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1019 ulong off, void *data, int len)
1020 {
1021 void __iomem *addr;
1022
1023 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1024 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1025 } else { /* Window 0 */
1026 addr = pci_base_offset(adapter, off);
1027 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1028 }
1029
1030 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
1031 pci_base(adapter, off), off, addr);
1032 if (!addr) {
1033 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1034 return 1;
1035 }
1036 switch (len) {
1037 case 1:
1038 *(u8 *) data = readb(addr);
1039 break;
1040 case 2:
1041 *(u16 *) data = readw(addr);
1042 break;
1043 case 4:
1044 *(u32 *) data = readl(addr);
1045 break;
1046 case 8:
1047 *(u64 *) data = readq(addr);
1048 break;
1049 default:
1050 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
1051 (len >> 3));
1052 break;
1053 }
1054 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
1055
1056 if (!ADDR_IN_WINDOW1(off))
1057 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1058
1059 return 0;
1060 }
1061
1062 int
netxen_nic_hw_write_wx_2M(struct netxen_adapter * adapter,ulong off,void * data,int len)1063 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1064 ulong off, void *data, int len)
1065 {
1066 unsigned long flags = 0;
1067 int rv;
1068
1069 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1070
1071 if (rv == -1) {
1072 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1073 __func__, off);
1074 dump_stack();
1075 return -1;
1076 }
1077
1078 if (rv == 1) {
1079 write_lock_irqsave(&adapter->adapter_lock, flags);
1080 crb_win_lock(adapter);
1081 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1082 }
1083
1084 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1085 *(unsigned long *)data, off, len);
1086
1087 switch (len) {
1088 case 1:
1089 writeb(*(uint8_t *)data, (void *)off);
1090 break;
1091 case 2:
1092 writew(*(uint16_t *)data, (void *)off);
1093 break;
1094 case 4:
1095 writel(*(uint32_t *)data, (void *)off);
1096 break;
1097 case 8:
1098 writeq(*(uint64_t *)data, (void *)off);
1099 break;
1100 default:
1101 DPRINTK(1, INFO,
1102 "writing data %lx to offset %llx, num words=%d\n",
1103 *(unsigned long *)data, off, (len>>3));
1104 break;
1105 }
1106 if (rv == 1) {
1107 crb_win_unlock(adapter);
1108 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1109 }
1110
1111 return 0;
1112 }
1113
1114 int
netxen_nic_hw_read_wx_2M(struct netxen_adapter * adapter,ulong off,void * data,int len)1115 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1116 ulong off, void *data, int len)
1117 {
1118 unsigned long flags = 0;
1119 int rv;
1120
1121 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1122
1123 if (rv == -1) {
1124 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1125 __func__, off);
1126 dump_stack();
1127 return -1;
1128 }
1129
1130 if (rv == 1) {
1131 write_lock_irqsave(&adapter->adapter_lock, flags);
1132 crb_win_lock(adapter);
1133 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1134 }
1135
1136 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1137
1138 switch (len) {
1139 case 1:
1140 *(uint8_t *)data = readb((void *)off);
1141 break;
1142 case 2:
1143 *(uint16_t *)data = readw((void *)off);
1144 break;
1145 case 4:
1146 *(uint32_t *)data = readl((void *)off);
1147 break;
1148 case 8:
1149 *(uint64_t *)data = readq((void *)off);
1150 break;
1151 default:
1152 break;
1153 }
1154
1155 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
1156
1157 if (rv == 1) {
1158 crb_win_unlock(adapter);
1159 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1160 }
1161
1162 return 0;
1163 }
1164
netxen_nic_reg_write(struct netxen_adapter * adapter,u64 off,u32 val)1165 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1166 {
1167 adapter->hw_write_wx(adapter, off, &val, 4);
1168 }
1169
netxen_nic_reg_read(struct netxen_adapter * adapter,u64 off)1170 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1171 {
1172 int val;
1173 adapter->hw_read_wx(adapter, off, &val, 4);
1174 return val;
1175 }
1176
1177 /* Change the window to 0, write and change back to window 1. */
netxen_nic_write_w0(struct netxen_adapter * adapter,u32 index,u32 value)1178 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1179 {
1180 adapter->hw_write_wx(adapter, index, &value, 4);
1181 }
1182
1183 /* Change the window to 0, read and change back to window 1. */
netxen_nic_read_w0(struct netxen_adapter * adapter,u32 index,u32 * value)1184 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
1185 {
1186 adapter->hw_read_wx(adapter, index, value, 4);
1187 }
1188
netxen_nic_write_w1(struct netxen_adapter * adapter,u32 index,u32 value)1189 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1190 {
1191 adapter->hw_write_wx(adapter, index, &value, 4);
1192 }
1193
netxen_nic_read_w1(struct netxen_adapter * adapter,u32 index,u32 * value)1194 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1195 {
1196 adapter->hw_read_wx(adapter, index, value, 4);
1197 }
1198
1199 /*
1200 * check memory access boundary.
1201 * used by test agent. support ddr access only for now
1202 */
1203 static unsigned long
netxen_nic_pci_mem_bound_check(struct netxen_adapter * adapter,unsigned long long addr,int size)1204 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1205 unsigned long long addr, int size)
1206 {
1207 if (!ADDR_IN_RANGE(addr,
1208 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1209 !ADDR_IN_RANGE(addr+size-1,
1210 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1211 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1212 return 0;
1213 }
1214
1215 return 1;
1216 }
1217
1218 static int netxen_pci_set_window_warning_count;
1219
1220 unsigned long
netxen_nic_pci_set_window_128M(struct netxen_adapter * adapter,unsigned long long addr)1221 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1222 unsigned long long addr)
1223 {
1224 void __iomem *offset;
1225 int window;
1226 unsigned long long qdr_max;
1227 uint8_t func = adapter->ahw.pci_func;
1228
1229 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1230 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1231 } else {
1232 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1233 }
1234
1235 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1236 /* DDR network side */
1237 addr -= NETXEN_ADDR_DDR_NET;
1238 window = (addr >> 25) & 0x3ff;
1239 if (adapter->ahw.ddr_mn_window != window) {
1240 adapter->ahw.ddr_mn_window = window;
1241 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1242 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1243 writel(window, offset);
1244 /* MUST make sure window is set before we forge on... */
1245 readl(offset);
1246 }
1247 addr -= (window * NETXEN_WINDOW_ONE);
1248 addr += NETXEN_PCI_DDR_NET;
1249 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1250 addr -= NETXEN_ADDR_OCM0;
1251 addr += NETXEN_PCI_OCM0;
1252 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1253 addr -= NETXEN_ADDR_OCM1;
1254 addr += NETXEN_PCI_OCM1;
1255 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1256 /* QDR network side */
1257 addr -= NETXEN_ADDR_QDR_NET;
1258 window = (addr >> 22) & 0x3f;
1259 if (adapter->ahw.qdr_sn_window != window) {
1260 adapter->ahw.qdr_sn_window = window;
1261 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1262 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1263 writel((window << 22), offset);
1264 /* MUST make sure window is set before we forge on... */
1265 readl(offset);
1266 }
1267 addr -= (window * 0x400000);
1268 addr += NETXEN_PCI_QDR_NET;
1269 } else {
1270 /*
1271 * peg gdb frequently accesses memory that doesn't exist,
1272 * this limits the chit chat so debugging isn't slowed down.
1273 */
1274 if ((netxen_pci_set_window_warning_count++ < 8)
1275 || (netxen_pci_set_window_warning_count % 64 == 0))
1276 printk("%s: Warning:netxen_nic_pci_set_window()"
1277 " Unknown address range!\n",
1278 netxen_nic_driver_name);
1279 addr = -1UL;
1280 }
1281 return addr;
1282 }
1283
1284 /*
1285 * Note : only 32-bit writes!
1286 */
netxen_nic_pci_write_immediate_128M(struct netxen_adapter * adapter,u64 off,u32 data)1287 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1288 u64 off, u32 data)
1289 {
1290 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1291 return 0;
1292 }
1293
netxen_nic_pci_read_immediate_128M(struct netxen_adapter * adapter,u64 off)1294 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1295 {
1296 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1297 }
1298
netxen_nic_pci_write_normalize_128M(struct netxen_adapter * adapter,u64 off,u32 data)1299 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1300 u64 off, u32 data)
1301 {
1302 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1303 }
1304
netxen_nic_pci_read_normalize_128M(struct netxen_adapter * adapter,u64 off)1305 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1306 {
1307 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1308 }
1309
1310 unsigned long
netxen_nic_pci_set_window_2M(struct netxen_adapter * adapter,unsigned long long addr)1311 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1312 unsigned long long addr)
1313 {
1314 int window;
1315 u32 win_read;
1316
1317 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1318 /* DDR network side */
1319 window = MN_WIN(addr);
1320 adapter->ahw.ddr_mn_window = window;
1321 adapter->hw_write_wx(adapter,
1322 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1323 &window, 4);
1324 adapter->hw_read_wx(adapter,
1325 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1326 &win_read, 4);
1327 if ((win_read << 17) != window) {
1328 printk(KERN_INFO "Written MNwin (0x%x) != "
1329 "Read MNwin (0x%x)\n", window, win_read);
1330 }
1331 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1332 } else if (ADDR_IN_RANGE(addr,
1333 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1334 if ((addr & 0x00ff800) == 0xff800) {
1335 printk("%s: QM access not handled.\n", __func__);
1336 addr = -1UL;
1337 }
1338
1339 window = OCM_WIN(addr);
1340 adapter->ahw.ddr_mn_window = window;
1341 adapter->hw_write_wx(adapter,
1342 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1343 &window, 4);
1344 adapter->hw_read_wx(adapter,
1345 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1346 &win_read, 4);
1347 if ((win_read >> 7) != window) {
1348 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1349 "Read OCMwin (0x%x)\n",
1350 __func__, window, win_read);
1351 }
1352 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1353
1354 } else if (ADDR_IN_RANGE(addr,
1355 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1356 /* QDR network side */
1357 window = MS_WIN(addr);
1358 adapter->ahw.qdr_sn_window = window;
1359 adapter->hw_write_wx(adapter,
1360 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1361 &window, 4);
1362 adapter->hw_read_wx(adapter,
1363 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1364 &win_read, 4);
1365 if (win_read != window) {
1366 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1367 "Read MSwin (0x%x)\n",
1368 __func__, window, win_read);
1369 }
1370 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1371
1372 } else {
1373 /*
1374 * peg gdb frequently accesses memory that doesn't exist,
1375 * this limits the chit chat so debugging isn't slowed down.
1376 */
1377 if ((netxen_pci_set_window_warning_count++ < 8)
1378 || (netxen_pci_set_window_warning_count%64 == 0)) {
1379 printk("%s: Warning:%s Unknown address range!\n",
1380 __func__, netxen_nic_driver_name);
1381 }
1382 addr = -1UL;
1383 }
1384 return addr;
1385 }
1386
netxen_nic_pci_is_same_window(struct netxen_adapter * adapter,unsigned long long addr)1387 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1388 unsigned long long addr)
1389 {
1390 int window;
1391 unsigned long long qdr_max;
1392
1393 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1394 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1395 else
1396 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1397
1398 if (ADDR_IN_RANGE(addr,
1399 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1400 /* DDR network side */
1401 BUG(); /* MN access can not come here */
1402 } else if (ADDR_IN_RANGE(addr,
1403 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1404 return 1;
1405 } else if (ADDR_IN_RANGE(addr,
1406 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1407 return 1;
1408 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1409 /* QDR network side */
1410 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1411 if (adapter->ahw.qdr_sn_window == window)
1412 return 1;
1413 }
1414
1415 return 0;
1416 }
1417
netxen_nic_pci_mem_read_direct(struct netxen_adapter * adapter,u64 off,void * data,int size)1418 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1419 u64 off, void *data, int size)
1420 {
1421 unsigned long flags;
1422 void *addr;
1423 int ret = 0;
1424 u64 start;
1425 uint8_t *mem_ptr = NULL;
1426 unsigned long mem_base;
1427 unsigned long mem_page;
1428
1429 write_lock_irqsave(&adapter->adapter_lock, flags);
1430
1431 /*
1432 * If attempting to access unknown address or straddle hw windows,
1433 * do not access.
1434 */
1435 start = adapter->pci_set_window(adapter, off);
1436 if ((start == -1UL) ||
1437 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1438 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1439 printk(KERN_ERR "%s out of bound pci memory access. "
1440 "offset is 0x%llx\n", netxen_nic_driver_name,
1441 (unsigned long long)off);
1442 return -1;
1443 }
1444
1445 addr = (void *)(pci_base_offset(adapter, start));
1446 if (!addr) {
1447 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1448 mem_base = pci_resource_start(adapter->pdev, 0);
1449 mem_page = start & PAGE_MASK;
1450 /* Map two pages whenever user tries to access addresses in two
1451 consecutive pages.
1452 */
1453 if (mem_page != ((start + size - 1) & PAGE_MASK))
1454 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1455 else
1456 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1457 if (mem_ptr == NULL) {
1458 *(uint8_t *)data = 0;
1459 return -1;
1460 }
1461 addr = mem_ptr;
1462 addr += start & (PAGE_SIZE - 1);
1463 write_lock_irqsave(&adapter->adapter_lock, flags);
1464 }
1465
1466 switch (size) {
1467 case 1:
1468 *(uint8_t *)data = readb(addr);
1469 break;
1470 case 2:
1471 *(uint16_t *)data = readw(addr);
1472 break;
1473 case 4:
1474 *(uint32_t *)data = readl(addr);
1475 break;
1476 case 8:
1477 *(uint64_t *)data = readq(addr);
1478 break;
1479 default:
1480 ret = -1;
1481 break;
1482 }
1483 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1484 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1485
1486 if (mem_ptr)
1487 iounmap(mem_ptr);
1488 return ret;
1489 }
1490
1491 static int
netxen_nic_pci_mem_write_direct(struct netxen_adapter * adapter,u64 off,void * data,int size)1492 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1493 void *data, int size)
1494 {
1495 unsigned long flags;
1496 void *addr;
1497 int ret = 0;
1498 u64 start;
1499 uint8_t *mem_ptr = NULL;
1500 unsigned long mem_base;
1501 unsigned long mem_page;
1502
1503 write_lock_irqsave(&adapter->adapter_lock, flags);
1504
1505 /*
1506 * If attempting to access unknown address or straddle hw windows,
1507 * do not access.
1508 */
1509 start = adapter->pci_set_window(adapter, off);
1510 if ((start == -1UL) ||
1511 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1512 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1513 printk(KERN_ERR "%s out of bound pci memory access. "
1514 "offset is 0x%llx\n", netxen_nic_driver_name,
1515 (unsigned long long)off);
1516 return -1;
1517 }
1518
1519 addr = (void *)(pci_base_offset(adapter, start));
1520 if (!addr) {
1521 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1522 mem_base = pci_resource_start(adapter->pdev, 0);
1523 mem_page = start & PAGE_MASK;
1524 /* Map two pages whenever user tries to access addresses in two
1525 * consecutive pages.
1526 */
1527 if (mem_page != ((start + size - 1) & PAGE_MASK))
1528 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1529 else
1530 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1531 if (mem_ptr == NULL)
1532 return -1;
1533 addr = mem_ptr;
1534 addr += start & (PAGE_SIZE - 1);
1535 write_lock_irqsave(&adapter->adapter_lock, flags);
1536 }
1537
1538 switch (size) {
1539 case 1:
1540 writeb(*(uint8_t *)data, addr);
1541 break;
1542 case 2:
1543 writew(*(uint16_t *)data, addr);
1544 break;
1545 case 4:
1546 writel(*(uint32_t *)data, addr);
1547 break;
1548 case 8:
1549 writeq(*(uint64_t *)data, addr);
1550 break;
1551 default:
1552 ret = -1;
1553 break;
1554 }
1555 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1556 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1557 *(unsigned long long *)data, start);
1558 if (mem_ptr)
1559 iounmap(mem_ptr);
1560 return ret;
1561 }
1562
1563 #define MAX_CTL_CHECK 1000
1564
1565 int
netxen_nic_pci_mem_write_128M(struct netxen_adapter * adapter,u64 off,void * data,int size)1566 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1567 u64 off, void *data, int size)
1568 {
1569 unsigned long flags, mem_crb;
1570 int i, j, ret = 0, loop, sz[2], off0;
1571 uint32_t temp;
1572 uint64_t off8, tmpw, word[2] = {0, 0};
1573
1574 /*
1575 * If not MN, go check for MS or invalid.
1576 */
1577 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1578 return netxen_nic_pci_mem_write_direct(adapter,
1579 off, data, size);
1580
1581 off8 = off & 0xfffffff8;
1582 off0 = off & 0x7;
1583 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1584 sz[1] = size - sz[0];
1585 loop = ((off0 + size - 1) >> 3) + 1;
1586 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1587
1588 if ((size != 8) || (off0 != 0)) {
1589 for (i = 0; i < loop; i++) {
1590 if (adapter->pci_mem_read(adapter,
1591 off8 + (i << 3), &word[i], 8))
1592 return -1;
1593 }
1594 }
1595
1596 switch (size) {
1597 case 1:
1598 tmpw = *((uint8_t *)data);
1599 break;
1600 case 2:
1601 tmpw = *((uint16_t *)data);
1602 break;
1603 case 4:
1604 tmpw = *((uint32_t *)data);
1605 break;
1606 case 8:
1607 default:
1608 tmpw = *((uint64_t *)data);
1609 break;
1610 }
1611 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1612 word[0] |= tmpw << (off0 * 8);
1613
1614 if (loop == 2) {
1615 word[1] &= ~(~0ULL << (sz[1] * 8));
1616 word[1] |= tmpw >> (sz[0] * 8);
1617 }
1618
1619 write_lock_irqsave(&adapter->adapter_lock, flags);
1620 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1621
1622 for (i = 0; i < loop; i++) {
1623 writel((uint32_t)(off8 + (i << 3)),
1624 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1625 writel(0,
1626 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1627 writel(word[i] & 0xffffffff,
1628 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1629 writel((word[i] >> 32) & 0xffffffff,
1630 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1631 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1632 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1633 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1634 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1635
1636 for (j = 0; j < MAX_CTL_CHECK; j++) {
1637 temp = readl(
1638 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1639 if ((temp & MIU_TA_CTL_BUSY) == 0)
1640 break;
1641 }
1642
1643 if (j >= MAX_CTL_CHECK) {
1644 printk("%s: %s Fail to write through agent\n",
1645 __func__, netxen_nic_driver_name);
1646 ret = -1;
1647 break;
1648 }
1649 }
1650
1651 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1652 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1653 return ret;
1654 }
1655
1656 int
netxen_nic_pci_mem_read_128M(struct netxen_adapter * adapter,u64 off,void * data,int size)1657 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1658 u64 off, void *data, int size)
1659 {
1660 unsigned long flags, mem_crb;
1661 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1662 uint32_t temp;
1663 uint64_t off8, val, word[2] = {0, 0};
1664
1665
1666 /*
1667 * If not MN, go check for MS or invalid.
1668 */
1669 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1670 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1671
1672 off8 = off & 0xfffffff8;
1673 off0[0] = off & 0x7;
1674 off0[1] = 0;
1675 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1676 sz[1] = size - sz[0];
1677 loop = ((off0[0] + size - 1) >> 3) + 1;
1678 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1679
1680 write_lock_irqsave(&adapter->adapter_lock, flags);
1681 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1682
1683 for (i = 0; i < loop; i++) {
1684 writel((uint32_t)(off8 + (i << 3)),
1685 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1686 writel(0,
1687 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1688 writel(MIU_TA_CTL_ENABLE,
1689 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1690 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1691 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1692
1693 for (j = 0; j < MAX_CTL_CHECK; j++) {
1694 temp = readl(
1695 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1696 if ((temp & MIU_TA_CTL_BUSY) == 0)
1697 break;
1698 }
1699
1700 if (j >= MAX_CTL_CHECK) {
1701 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1702 __func__, netxen_nic_driver_name);
1703 break;
1704 }
1705
1706 start = off0[i] >> 2;
1707 end = (off0[i] + sz[i] - 1) >> 2;
1708 for (k = start; k <= end; k++) {
1709 word[i] |= ((uint64_t) readl(
1710 (void *)(mem_crb +
1711 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1712 }
1713 }
1714
1715 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1716 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1717
1718 if (j >= MAX_CTL_CHECK)
1719 return -1;
1720
1721 if (sz[0] == 8) {
1722 val = word[0];
1723 } else {
1724 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1725 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1726 }
1727
1728 switch (size) {
1729 case 1:
1730 *(uint8_t *)data = val;
1731 break;
1732 case 2:
1733 *(uint16_t *)data = val;
1734 break;
1735 case 4:
1736 *(uint32_t *)data = val;
1737 break;
1738 case 8:
1739 *(uint64_t *)data = val;
1740 break;
1741 }
1742 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1743 return 0;
1744 }
1745
1746 int
netxen_nic_pci_mem_write_2M(struct netxen_adapter * adapter,u64 off,void * data,int size)1747 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1748 u64 off, void *data, int size)
1749 {
1750 int i, j, ret = 0, loop, sz[2], off0;
1751 uint32_t temp;
1752 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1753
1754 /*
1755 * If not MN, go check for MS or invalid.
1756 */
1757 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1758 mem_crb = NETXEN_CRB_QDR_NET;
1759 else {
1760 mem_crb = NETXEN_CRB_DDR_NET;
1761 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1762 return netxen_nic_pci_mem_write_direct(adapter,
1763 off, data, size);
1764 }
1765
1766 off8 = off & 0xfffffff8;
1767 off0 = off & 0x7;
1768 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1769 sz[1] = size - sz[0];
1770 loop = ((off0 + size - 1) >> 3) + 1;
1771
1772 if ((size != 8) || (off0 != 0)) {
1773 for (i = 0; i < loop; i++) {
1774 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1775 &word[i], 8))
1776 return -1;
1777 }
1778 }
1779
1780 switch (size) {
1781 case 1:
1782 tmpw = *((uint8_t *)data);
1783 break;
1784 case 2:
1785 tmpw = *((uint16_t *)data);
1786 break;
1787 case 4:
1788 tmpw = *((uint32_t *)data);
1789 break;
1790 case 8:
1791 default:
1792 tmpw = *((uint64_t *)data);
1793 break;
1794 }
1795
1796 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1797 word[0] |= tmpw << (off0 * 8);
1798
1799 if (loop == 2) {
1800 word[1] &= ~(~0ULL << (sz[1] * 8));
1801 word[1] |= tmpw >> (sz[0] * 8);
1802 }
1803
1804 /*
1805 * don't lock here - write_wx gets the lock if each time
1806 * write_lock_irqsave(&adapter->adapter_lock, flags);
1807 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1808 */
1809
1810 for (i = 0; i < loop; i++) {
1811 temp = off8 + (i << 3);
1812 adapter->hw_write_wx(adapter,
1813 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1814 temp = 0;
1815 adapter->hw_write_wx(adapter,
1816 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1817 temp = word[i] & 0xffffffff;
1818 adapter->hw_write_wx(adapter,
1819 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1820 temp = (word[i] >> 32) & 0xffffffff;
1821 adapter->hw_write_wx(adapter,
1822 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1823 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1824 adapter->hw_write_wx(adapter,
1825 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1826 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1827 adapter->hw_write_wx(adapter,
1828 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1829
1830 for (j = 0; j < MAX_CTL_CHECK; j++) {
1831 adapter->hw_read_wx(adapter,
1832 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1833 if ((temp & MIU_TA_CTL_BUSY) == 0)
1834 break;
1835 }
1836
1837 if (j >= MAX_CTL_CHECK) {
1838 printk(KERN_ERR "%s: Fail to write through agent\n",
1839 netxen_nic_driver_name);
1840 ret = -1;
1841 break;
1842 }
1843 }
1844
1845 /*
1846 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1847 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1848 */
1849 return ret;
1850 }
1851
1852 int
netxen_nic_pci_mem_read_2M(struct netxen_adapter * adapter,u64 off,void * data,int size)1853 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1854 u64 off, void *data, int size)
1855 {
1856 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1857 uint32_t temp;
1858 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1859
1860 /*
1861 * If not MN, go check for MS or invalid.
1862 */
1863
1864 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1865 mem_crb = NETXEN_CRB_QDR_NET;
1866 else {
1867 mem_crb = NETXEN_CRB_DDR_NET;
1868 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1869 return netxen_nic_pci_mem_read_direct(adapter,
1870 off, data, size);
1871 }
1872
1873 off8 = off & 0xfffffff8;
1874 off0[0] = off & 0x7;
1875 off0[1] = 0;
1876 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1877 sz[1] = size - sz[0];
1878 loop = ((off0[0] + size - 1) >> 3) + 1;
1879
1880 /*
1881 * don't lock here - write_wx gets the lock if each time
1882 * write_lock_irqsave(&adapter->adapter_lock, flags);
1883 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1884 */
1885
1886 for (i = 0; i < loop; i++) {
1887 temp = off8 + (i << 3);
1888 adapter->hw_write_wx(adapter,
1889 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1890 temp = 0;
1891 adapter->hw_write_wx(adapter,
1892 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1893 temp = MIU_TA_CTL_ENABLE;
1894 adapter->hw_write_wx(adapter,
1895 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1896 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1897 adapter->hw_write_wx(adapter,
1898 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1899
1900 for (j = 0; j < MAX_CTL_CHECK; j++) {
1901 adapter->hw_read_wx(adapter,
1902 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1903 if ((temp & MIU_TA_CTL_BUSY) == 0)
1904 break;
1905 }
1906
1907 if (j >= MAX_CTL_CHECK) {
1908 printk(KERN_ERR "%s: Fail to read through agent\n",
1909 netxen_nic_driver_name);
1910 break;
1911 }
1912
1913 start = off0[i] >> 2;
1914 end = (off0[i] + sz[i] - 1) >> 2;
1915 for (k = start; k <= end; k++) {
1916 adapter->hw_read_wx(adapter,
1917 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1918 word[i] |= ((uint64_t)temp << (32 * k));
1919 }
1920 }
1921
1922 /*
1923 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1924 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1925 */
1926
1927 if (j >= MAX_CTL_CHECK)
1928 return -1;
1929
1930 if (sz[0] == 8) {
1931 val = word[0];
1932 } else {
1933 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1934 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1935 }
1936
1937 switch (size) {
1938 case 1:
1939 *(uint8_t *)data = val;
1940 break;
1941 case 2:
1942 *(uint16_t *)data = val;
1943 break;
1944 case 4:
1945 *(uint32_t *)data = val;
1946 break;
1947 case 8:
1948 *(uint64_t *)data = val;
1949 break;
1950 }
1951 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1952 return 0;
1953 }
1954
1955 /*
1956 * Note : only 32-bit writes!
1957 */
netxen_nic_pci_write_immediate_2M(struct netxen_adapter * adapter,u64 off,u32 data)1958 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1959 u64 off, u32 data)
1960 {
1961 adapter->hw_write_wx(adapter, off, &data, 4);
1962
1963 return 0;
1964 }
1965
netxen_nic_pci_read_immediate_2M(struct netxen_adapter * adapter,u64 off)1966 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1967 {
1968 u32 temp;
1969 adapter->hw_read_wx(adapter, off, &temp, 4);
1970 return temp;
1971 }
1972
netxen_nic_pci_write_normalize_2M(struct netxen_adapter * adapter,u64 off,u32 data)1973 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1974 u64 off, u32 data)
1975 {
1976 adapter->hw_write_wx(adapter, off, &data, 4);
1977 }
1978
netxen_nic_pci_read_normalize_2M(struct netxen_adapter * adapter,u64 off)1979 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
1980 {
1981 u32 temp;
1982 adapter->hw_read_wx(adapter, off, &temp, 4);
1983 return temp;
1984 }
1985
1986 #if 0
1987 int
1988 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
1989 {
1990 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
1991 printk(KERN_ERR "%s: erase pxe failed\n",
1992 netxen_nic_driver_name);
1993 return -1;
1994 }
1995 return 0;
1996 }
1997 #endif /* 0 */
1998
netxen_nic_get_board_info(struct netxen_adapter * adapter)1999 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2000 {
2001 int rv = 0;
2002 int addr = NETXEN_BRDCFG_START;
2003 struct netxen_board_info *boardinfo;
2004 int index;
2005 u32 *ptr32;
2006
2007 boardinfo = &adapter->ahw.boardcfg;
2008 ptr32 = (u32 *) boardinfo;
2009
2010 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
2011 index++) {
2012 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2013 return -EIO;
2014 }
2015 ptr32++;
2016 addr += sizeof(u32);
2017 }
2018 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
2019 printk("%s: ERROR reading %s board config."
2020 " Read %x, expected %x\n", netxen_nic_driver_name,
2021 netxen_nic_driver_name,
2022 boardinfo->magic, NETXEN_BDINFO_MAGIC);
2023 rv = -1;
2024 }
2025 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
2026 printk("%s: Unknown board config version."
2027 " Read %x, expected %x\n", netxen_nic_driver_name,
2028 boardinfo->header_version, NETXEN_BDINFO_VERSION);
2029 rv = -1;
2030 }
2031
2032 if (boardinfo->board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2033 u32 gpio = netxen_nic_reg_read(adapter,
2034 NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2035 if ((gpio & 0x8000) == 0)
2036 boardinfo->board_type = NETXEN_BRDTYPE_P3_10G_TP;
2037 }
2038
2039 switch ((netxen_brdtype_t) boardinfo->board_type) {
2040 case NETXEN_BRDTYPE_P2_SB35_4G:
2041 adapter->ahw.board_type = NETXEN_NIC_GBE;
2042 break;
2043 case NETXEN_BRDTYPE_P2_SB31_10G:
2044 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2045 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2046 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2047 case NETXEN_BRDTYPE_P3_HMEZ:
2048 case NETXEN_BRDTYPE_P3_XG_LOM:
2049 case NETXEN_BRDTYPE_P3_10G_CX4:
2050 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2051 case NETXEN_BRDTYPE_P3_IMEZ:
2052 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2053 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2054 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
2055 case NETXEN_BRDTYPE_P3_10G_XFP:
2056 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2057 adapter->ahw.board_type = NETXEN_NIC_XGBE;
2058 break;
2059 case NETXEN_BRDTYPE_P1_BD:
2060 case NETXEN_BRDTYPE_P1_SB:
2061 case NETXEN_BRDTYPE_P1_SMAX:
2062 case NETXEN_BRDTYPE_P1_SOCK:
2063 case NETXEN_BRDTYPE_P3_REF_QG:
2064 case NETXEN_BRDTYPE_P3_4_GB:
2065 case NETXEN_BRDTYPE_P3_4_GB_MM:
2066 adapter->ahw.board_type = NETXEN_NIC_GBE;
2067 break;
2068 case NETXEN_BRDTYPE_P3_10G_TP:
2069 adapter->ahw.board_type = (adapter->portnum < 2) ?
2070 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2071 break;
2072 default:
2073 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
2074 boardinfo->board_type);
2075 rv = -ENODEV;
2076 break;
2077 }
2078
2079 return rv;
2080 }
2081
2082 /* NIU access sections */
2083
netxen_nic_set_mtu_gb(struct netxen_adapter * adapter,int new_mtu)2084 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2085 {
2086 new_mtu += MTU_FUDGE_FACTOR;
2087 netxen_nic_write_w0(adapter,
2088 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2089 new_mtu);
2090 return 0;
2091 }
2092
netxen_nic_set_mtu_xgb(struct netxen_adapter * adapter,int new_mtu)2093 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2094 {
2095 new_mtu += MTU_FUDGE_FACTOR;
2096 if (adapter->physical_port == 0)
2097 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
2098 new_mtu);
2099 else
2100 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2101 new_mtu);
2102 return 0;
2103 }
2104
2105 void
netxen_crb_writelit_adapter(struct netxen_adapter * adapter,unsigned long off,int data)2106 netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2107 unsigned long off, int data)
2108 {
2109 adapter->hw_write_wx(adapter, off, &data, 4);
2110 }
2111
netxen_nic_set_link_parameters(struct netxen_adapter * adapter)2112 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2113 {
2114 __u32 status;
2115 __u32 autoneg;
2116 __u32 port_mode;
2117
2118 if (!netif_carrier_ok(adapter->netdev)) {
2119 adapter->link_speed = 0;
2120 adapter->link_duplex = -1;
2121 adapter->link_autoneg = AUTONEG_ENABLE;
2122 return;
2123 }
2124
2125 if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
2126 adapter->hw_read_wx(adapter,
2127 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2128 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2129 adapter->link_speed = SPEED_1000;
2130 adapter->link_duplex = DUPLEX_FULL;
2131 adapter->link_autoneg = AUTONEG_DISABLE;
2132 return;
2133 }
2134
2135 if (adapter->phy_read
2136 && adapter->phy_read(adapter,
2137 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2138 &status) == 0) {
2139 if (netxen_get_phy_link(status)) {
2140 switch (netxen_get_phy_speed(status)) {
2141 case 0:
2142 adapter->link_speed = SPEED_10;
2143 break;
2144 case 1:
2145 adapter->link_speed = SPEED_100;
2146 break;
2147 case 2:
2148 adapter->link_speed = SPEED_1000;
2149 break;
2150 default:
2151 adapter->link_speed = 0;
2152 break;
2153 }
2154 switch (netxen_get_phy_duplex(status)) {
2155 case 0:
2156 adapter->link_duplex = DUPLEX_HALF;
2157 break;
2158 case 1:
2159 adapter->link_duplex = DUPLEX_FULL;
2160 break;
2161 default:
2162 adapter->link_duplex = -1;
2163 break;
2164 }
2165 if (adapter->phy_read
2166 && adapter->phy_read(adapter,
2167 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2168 &autoneg) != 0)
2169 adapter->link_autoneg = autoneg;
2170 } else
2171 goto link_down;
2172 } else {
2173 link_down:
2174 adapter->link_speed = 0;
2175 adapter->link_duplex = -1;
2176 }
2177 }
2178 }
2179
netxen_nic_flash_print(struct netxen_adapter * adapter)2180 void netxen_nic_flash_print(struct netxen_adapter *adapter)
2181 {
2182 u32 fw_major = 0;
2183 u32 fw_minor = 0;
2184 u32 fw_build = 0;
2185 char brd_name[NETXEN_MAX_SHORT_NAME];
2186 char serial_num[32];
2187 int i, addr;
2188 __le32 *ptr32;
2189
2190 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
2191
2192 adapter->driver_mismatch = 0;
2193
2194 ptr32 = (u32 *)&serial_num;
2195 addr = NETXEN_USER_START +
2196 offsetof(struct netxen_new_user_info, serial_num);
2197 for (i = 0; i < 8; i++) {
2198 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2199 printk("%s: ERROR reading %s board userarea.\n",
2200 netxen_nic_driver_name,
2201 netxen_nic_driver_name);
2202 adapter->driver_mismatch = 1;
2203 return;
2204 }
2205 ptr32++;
2206 addr += sizeof(u32);
2207 }
2208
2209 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2210 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2211 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
2212
2213 adapter->fw_major = fw_major;
2214
2215 if (adapter->portnum == 0) {
2216 get_brd_name_by_type(board_info->board_type, brd_name);
2217
2218 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2219 brd_name, serial_num, adapter->ahw.revision_id);
2220 printk(KERN_INFO "NetXen Firmware version %d.%d.%d\n",
2221 fw_major, fw_minor, fw_build);
2222 }
2223
2224 if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) <
2225 NETXEN_VERSION_CODE(3, 4, 216)) {
2226 adapter->driver_mismatch = 1;
2227 printk(KERN_ERR "%s: firmware version %d.%d.%d unsupported\n",
2228 netxen_nic_driver_name,
2229 fw_major, fw_minor, fw_build);
2230 return;
2231 }
2232 }
2233
2234