1 /* 2 * Copyright (C) 2006 PA Semi, Inc 3 * 4 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and 5 * hardware register layouts. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21 #ifndef PASEMI_MAC_H 22 #define PASEMI_MAC_H 23 24 #include <linux/ethtool.h> 25 #include <linux/netdevice.h> 26 #include <linux/spinlock.h> 27 #include <linux/phy.h> 28 29 /* Must be a power of two */ 30 #define RX_RING_SIZE 2048 31 #define TX_RING_SIZE 4096 32 #define CS_RING_SIZE (TX_RING_SIZE*2) 33 34 35 #define MAX_LRO_DESCRIPTORS 8 36 #define MAX_CS 2 37 38 struct pasemi_mac_txring { 39 struct pasemi_dmachan chan; /* Must be first */ 40 spinlock_t lock; 41 unsigned int size; 42 unsigned int next_to_fill; 43 unsigned int next_to_clean; 44 struct pasemi_mac_buffer *ring_info; 45 struct pasemi_mac *mac; /* Needed in intr handler */ 46 struct timer_list clean_timer; 47 }; 48 49 struct pasemi_mac_rxring { 50 struct pasemi_dmachan chan; /* Must be first */ 51 spinlock_t lock; 52 u64 *buffers; /* RX interface buffer ring */ 53 dma_addr_t buf_dma; 54 unsigned int size; 55 unsigned int next_to_fill; 56 unsigned int next_to_clean; 57 struct pasemi_mac_buffer *ring_info; 58 struct pasemi_mac *mac; /* Needed in intr handler */ 59 }; 60 61 struct pasemi_mac_csring { 62 struct pasemi_dmachan chan; 63 unsigned int size; 64 unsigned int next_to_fill; 65 int events[2]; 66 int last_event; 67 int fun; 68 }; 69 70 struct pasemi_mac { 71 struct net_device *netdev; 72 struct pci_dev *pdev; 73 struct pci_dev *dma_pdev; 74 struct pci_dev *iob_pdev; 75 struct phy_device *phydev; 76 struct napi_struct napi; 77 78 int bufsz; /* RX ring buffer size */ 79 int last_cs; 80 int num_cs; 81 u32 dma_if; 82 u8 type; 83 #define MAC_TYPE_GMAC 1 84 #define MAC_TYPE_XAUI 2 85 86 u8 mac_addr[6]; 87 88 struct net_lro_mgr lro_mgr; 89 struct net_lro_desc lro_desc[MAX_LRO_DESCRIPTORS]; 90 struct timer_list rxtimer; 91 unsigned int lro_max_aggr; 92 93 struct pasemi_mac_txring *tx; 94 struct pasemi_mac_rxring *rx; 95 struct pasemi_mac_csring *cs[MAX_CS]; 96 char tx_irq_name[10]; /* "eth%d tx" */ 97 char rx_irq_name[10]; /* "eth%d rx" */ 98 int link; 99 int speed; 100 int duplex; 101 102 unsigned int msg_enable; 103 char phy_id[BUS_ID_SIZE]; 104 }; 105 106 /* Software status descriptor (ring_info) */ 107 struct pasemi_mac_buffer { 108 struct sk_buff *skb; 109 dma_addr_t dma; 110 }; 111 112 #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) 113 #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) 114 #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) 115 #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) 116 #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) 117 #define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)]) 118 119 #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \ 120 & ((ring)->size - 1)) 121 #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring)) 122 123 /* PCI register offsets and formats */ 124 125 126 /* MAC CFG register offsets */ 127 enum { 128 PAS_MAC_CFG_PCFG = 0x80, 129 PAS_MAC_CFG_MACCFG = 0x84, 130 PAS_MAC_CFG_ADR0 = 0x8c, 131 PAS_MAC_CFG_ADR1 = 0x90, 132 PAS_MAC_CFG_TXP = 0x98, 133 PAS_MAC_CFG_RMON = 0x100, 134 PAS_MAC_IPC_CHNL = 0x208, 135 }; 136 137 /* MAC CFG register fields */ 138 #define PAS_MAC_CFG_PCFG_PE 0x80000000 139 #define PAS_MAC_CFG_PCFG_CE 0x40000000 140 #define PAS_MAC_CFG_PCFG_BU 0x20000000 141 #define PAS_MAC_CFG_PCFG_TT 0x10000000 142 #define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000 143 #define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000 144 #define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000 145 #define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000 146 #define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000 147 #define PAS_MAC_CFG_PCFG_T24 0x02000000 148 #define PAS_MAC_CFG_PCFG_PR 0x01000000 149 #define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000 150 #define PAS_MAC_CFG_PCFG_CRO_S 16 151 #define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00 152 #define PAS_MAC_CFG_PCFG_IPO_S 8 153 #define PAS_MAC_CFG_PCFG_S1 0x00000080 154 #define PAS_MAC_CFG_PCFG_IO_M 0x00000060 155 #define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000 156 #define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020 157 #define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040 158 #define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060 159 #define PAS_MAC_CFG_PCFG_LP 0x00000010 160 #define PAS_MAC_CFG_PCFG_TS 0x00000008 161 #define PAS_MAC_CFG_PCFG_HD 0x00000004 162 #define PAS_MAC_CFG_PCFG_SPD_M 0x00000003 163 #define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000 164 #define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001 165 #define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002 166 #define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003 167 168 #define PAS_MAC_CFG_MACCFG_TXT_M 0x70000000 169 #define PAS_MAC_CFG_MACCFG_TXT_S 28 170 #define PAS_MAC_CFG_MACCFG_PRES_M 0x0f000000 171 #define PAS_MAC_CFG_MACCFG_PRES_S 24 172 #define PAS_MAC_CFG_MACCFG_MAXF_M 0x00ffff00 173 #define PAS_MAC_CFG_MACCFG_MAXF_S 8 174 #define PAS_MAC_CFG_MACCFG_MAXF(x) (((x) << PAS_MAC_CFG_MACCFG_MAXF_S) & \ 175 PAS_MAC_CFG_MACCFG_MAXF_M) 176 #define PAS_MAC_CFG_MACCFG_MINF_M 0x000000ff 177 #define PAS_MAC_CFG_MACCFG_MINF_S 0 178 179 #define PAS_MAC_CFG_TXP_FCF 0x01000000 180 #define PAS_MAC_CFG_TXP_FCE 0x00800000 181 #define PAS_MAC_CFG_TXP_FC 0x00400000 182 #define PAS_MAC_CFG_TXP_FPC_M 0x00300000 183 #define PAS_MAC_CFG_TXP_FPC_S 20 184 #define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \ 185 PAS_MAC_CFG_TXP_FPC_M) 186 #define PAS_MAC_CFG_TXP_RT 0x00080000 187 #define PAS_MAC_CFG_TXP_BL 0x00040000 188 #define PAS_MAC_CFG_TXP_SL_M 0x00030000 189 #define PAS_MAC_CFG_TXP_SL_S 16 190 #define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \ 191 PAS_MAC_CFG_TXP_SL_M) 192 #define PAS_MAC_CFG_TXP_COB_M 0x0000f000 193 #define PAS_MAC_CFG_TXP_COB_S 12 194 #define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \ 195 PAS_MAC_CFG_TXP_COB_M) 196 #define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00 197 #define PAS_MAC_CFG_TXP_TIFT_S 8 198 #define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \ 199 PAS_MAC_CFG_TXP_TIFT_M) 200 #define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff 201 #define PAS_MAC_CFG_TXP_TIFG_S 0 202 #define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \ 203 PAS_MAC_CFG_TXP_TIFG_M) 204 205 #define PAS_MAC_RMON(r) (0x100+(r)*4) 206 207 #define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000 208 #define PAS_MAC_IPC_CHNL_DCHNO_S 16 209 #define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \ 210 PAS_MAC_IPC_CHNL_DCHNO_M) 211 #define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f 212 #define PAS_MAC_IPC_CHNL_BCH_S 0 213 #define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \ 214 PAS_MAC_IPC_CHNL_BCH_M) 215 216 217 #endif /* PASEMI_MAC_H */ 218