1 /*************************************************************************** 2 * 3 * Copyright (C) 2004-2008 SMSC 4 * Copyright (C) 2005-2008 ARM 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 * 20 ***************************************************************************/ 21 #ifndef __SMSC911X_H__ 22 #define __SMSC911X_H__ 23 24 #define TX_FIFO_LOW_THRESHOLD ((u32)1600) 25 #define SMSC911X_EEPROM_SIZE ((u32)7) 26 #define USE_DEBUG 0 27 28 /* This is the maximum number of packets to be received every 29 * NAPI poll */ 30 #define SMSC_NAPI_WEIGHT 16 31 32 /* implements a PHY loopback test at initialisation time, to ensure a packet 33 * can be succesfully looped back */ 34 #define USE_PHY_WORK_AROUND 35 36 #define DPRINTK(nlevel, klevel, fmt, args...) \ 37 ((void)((NETIF_MSG_##nlevel & pdata->msg_enable) && \ 38 printk(KERN_##klevel "%s: %s: " fmt "\n", \ 39 pdata->dev->name, __func__, ## args))) 40 41 #if USE_DEBUG >= 1 42 #define SMSC_WARNING(nlevel, fmt, args...) \ 43 DPRINTK(nlevel, WARNING, fmt, ## args) 44 #else 45 #define SMSC_WARNING(nlevel, fmt, args...) \ 46 ({ do {} while (0); 0; }) 47 #endif 48 49 #if USE_DEBUG >= 2 50 #define SMSC_TRACE(nlevel, fmt, args...) \ 51 DPRINTK(nlevel, INFO, fmt, ## args) 52 #else 53 #define SMSC_TRACE(nlevel, fmt, args...) \ 54 ({ do {} while (0); 0; }) 55 #endif 56 57 #ifdef CONFIG_DEBUG_SPINLOCK 58 #define SMSC_ASSERT_MAC_LOCK(pdata) \ 59 WARN_ON(!spin_is_locked(&pdata->mac_lock)) 60 #else 61 #define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0) 62 #endif /* CONFIG_DEBUG_SPINLOCK */ 63 64 /* SMSC911x registers and bitfields */ 65 #define RX_DATA_FIFO 0x00 66 67 #define TX_DATA_FIFO 0x20 68 #define TX_CMD_A_ON_COMP_ 0x80000000 69 #define TX_CMD_A_BUF_END_ALGN_ 0x03000000 70 #define TX_CMD_A_4_BYTE_ALGN_ 0x00000000 71 #define TX_CMD_A_16_BYTE_ALGN_ 0x01000000 72 #define TX_CMD_A_32_BYTE_ALGN_ 0x02000000 73 #define TX_CMD_A_DATA_OFFSET_ 0x001F0000 74 #define TX_CMD_A_FIRST_SEG_ 0x00002000 75 #define TX_CMD_A_LAST_SEG_ 0x00001000 76 #define TX_CMD_A_BUF_SIZE_ 0x000007FF 77 #define TX_CMD_B_PKT_TAG_ 0xFFFF0000 78 #define TX_CMD_B_ADD_CRC_DISABLE_ 0x00002000 79 #define TX_CMD_B_DISABLE_PADDING_ 0x00001000 80 #define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF 81 82 #define RX_STATUS_FIFO 0x40 83 #define RX_STS_ES_ 0x00008000 84 #define RX_STS_MCAST_ 0x00000400 85 86 #define RX_STATUS_FIFO_PEEK 0x44 87 88 #define TX_STATUS_FIFO 0x48 89 #define TX_STS_ES_ 0x00008000 90 91 #define TX_STATUS_FIFO_PEEK 0x4C 92 93 #define ID_REV 0x50 94 #define ID_REV_CHIP_ID_ 0xFFFF0000 95 #define ID_REV_REV_ID_ 0x0000FFFF 96 97 #define INT_CFG 0x54 98 #define INT_CFG_INT_DEAS_ 0xFF000000 99 #define INT_CFG_INT_DEAS_CLR_ 0x00004000 100 #define INT_CFG_INT_DEAS_STS_ 0x00002000 101 #define INT_CFG_IRQ_INT_ 0x00001000 102 #define INT_CFG_IRQ_EN_ 0x00000100 103 #define INT_CFG_IRQ_POL_ 0x00000010 104 #define INT_CFG_IRQ_TYPE_ 0x00000001 105 106 #define INT_STS 0x58 107 #define INT_STS_SW_INT_ 0x80000000 108 #define INT_STS_TXSTOP_INT_ 0x02000000 109 #define INT_STS_RXSTOP_INT_ 0x01000000 110 #define INT_STS_RXDFH_INT_ 0x00800000 111 #define INT_STS_RXDF_INT_ 0x00400000 112 #define INT_STS_TX_IOC_ 0x00200000 113 #define INT_STS_RXD_INT_ 0x00100000 114 #define INT_STS_GPT_INT_ 0x00080000 115 #define INT_STS_PHY_INT_ 0x00040000 116 #define INT_STS_PME_INT_ 0x00020000 117 #define INT_STS_TXSO_ 0x00010000 118 #define INT_STS_RWT_ 0x00008000 119 #define INT_STS_RXE_ 0x00004000 120 #define INT_STS_TXE_ 0x00002000 121 #define INT_STS_TDFU_ 0x00000800 122 #define INT_STS_TDFO_ 0x00000400 123 #define INT_STS_TDFA_ 0x00000200 124 #define INT_STS_TSFF_ 0x00000100 125 #define INT_STS_TSFL_ 0x00000080 126 #define INT_STS_RXDF_ 0x00000040 127 #define INT_STS_RDFL_ 0x00000020 128 #define INT_STS_RSFF_ 0x00000010 129 #define INT_STS_RSFL_ 0x00000008 130 #define INT_STS_GPIO2_INT_ 0x00000004 131 #define INT_STS_GPIO1_INT_ 0x00000002 132 #define INT_STS_GPIO0_INT_ 0x00000001 133 134 #define INT_EN 0x5C 135 #define INT_EN_SW_INT_EN_ 0x80000000 136 #define INT_EN_TXSTOP_INT_EN_ 0x02000000 137 #define INT_EN_RXSTOP_INT_EN_ 0x01000000 138 #define INT_EN_RXDFH_INT_EN_ 0x00800000 139 #define INT_EN_TIOC_INT_EN_ 0x00200000 140 #define INT_EN_RXD_INT_EN_ 0x00100000 141 #define INT_EN_GPT_INT_EN_ 0x00080000 142 #define INT_EN_PHY_INT_EN_ 0x00040000 143 #define INT_EN_PME_INT_EN_ 0x00020000 144 #define INT_EN_TXSO_EN_ 0x00010000 145 #define INT_EN_RWT_EN_ 0x00008000 146 #define INT_EN_RXE_EN_ 0x00004000 147 #define INT_EN_TXE_EN_ 0x00002000 148 #define INT_EN_TDFU_EN_ 0x00000800 149 #define INT_EN_TDFO_EN_ 0x00000400 150 #define INT_EN_TDFA_EN_ 0x00000200 151 #define INT_EN_TSFF_EN_ 0x00000100 152 #define INT_EN_TSFL_EN_ 0x00000080 153 #define INT_EN_RXDF_EN_ 0x00000040 154 #define INT_EN_RDFL_EN_ 0x00000020 155 #define INT_EN_RSFF_EN_ 0x00000010 156 #define INT_EN_RSFL_EN_ 0x00000008 157 #define INT_EN_GPIO2_INT_ 0x00000004 158 #define INT_EN_GPIO1_INT_ 0x00000002 159 #define INT_EN_GPIO0_INT_ 0x00000001 160 161 #define BYTE_TEST 0x64 162 163 #define FIFO_INT 0x68 164 #define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000 165 #define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000 166 #define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00 167 #define FIFO_INT_RX_STS_LEVEL_ 0x000000FF 168 169 #define RX_CFG 0x6C 170 #define RX_CFG_RX_END_ALGN_ 0xC0000000 171 #define RX_CFG_RX_END_ALGN4_ 0x00000000 172 #define RX_CFG_RX_END_ALGN16_ 0x40000000 173 #define RX_CFG_RX_END_ALGN32_ 0x80000000 174 #define RX_CFG_RX_DMA_CNT_ 0x0FFF0000 175 #define RX_CFG_RX_DUMP_ 0x00008000 176 #define RX_CFG_RXDOFF_ 0x00001F00 177 178 #define TX_CFG 0x70 179 #define TX_CFG_TXS_DUMP_ 0x00008000 180 #define TX_CFG_TXD_DUMP_ 0x00004000 181 #define TX_CFG_TXSAO_ 0x00000004 182 #define TX_CFG_TX_ON_ 0x00000002 183 #define TX_CFG_STOP_TX_ 0x00000001 184 185 #define HW_CFG 0x74 186 #define HW_CFG_TTM_ 0x00200000 187 #define HW_CFG_SF_ 0x00100000 188 #define HW_CFG_TX_FIF_SZ_ 0x000F0000 189 #define HW_CFG_TR_ 0x00003000 190 #define HW_CFG_SRST_ 0x00000001 191 192 /* only available on 115/117 */ 193 #define HW_CFG_PHY_CLK_SEL_ 0x00000060 194 #define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000 195 #define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020 196 #define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040 197 #define HW_CFG_SMI_SEL_ 0x00000010 198 #define HW_CFG_EXT_PHY_DET_ 0x00000008 199 #define HW_CFG_EXT_PHY_EN_ 0x00000004 200 #define HW_CFG_SRST_TO_ 0x00000002 201 202 /* only available on 116/118 */ 203 #define HW_CFG_32_16_BIT_MODE_ 0x00000004 204 205 #define RX_DP_CTRL 0x78 206 #define RX_DP_CTRL_RX_FFWD_ 0x80000000 207 208 #define RX_FIFO_INF 0x7C 209 #define RX_FIFO_INF_RXSUSED_ 0x00FF0000 210 #define RX_FIFO_INF_RXDUSED_ 0x0000FFFF 211 212 #define TX_FIFO_INF 0x80 213 #define TX_FIFO_INF_TSUSED_ 0x00FF0000 214 #define TX_FIFO_INF_TDFREE_ 0x0000FFFF 215 216 #define PMT_CTRL 0x84 217 #define PMT_CTRL_PM_MODE_ 0x00003000 218 #define PMT_CTRL_PM_MODE_D0_ 0x00000000 219 #define PMT_CTRL_PM_MODE_D1_ 0x00001000 220 #define PMT_CTRL_PM_MODE_D2_ 0x00002000 221 #define PMT_CTRL_PM_MODE_D3_ 0x00003000 222 #define PMT_CTRL_PHY_RST_ 0x00000400 223 #define PMT_CTRL_WOL_EN_ 0x00000200 224 #define PMT_CTRL_ED_EN_ 0x00000100 225 #define PMT_CTRL_PME_TYPE_ 0x00000040 226 #define PMT_CTRL_WUPS_ 0x00000030 227 #define PMT_CTRL_WUPS_NOWAKE_ 0x00000000 228 #define PMT_CTRL_WUPS_ED_ 0x00000010 229 #define PMT_CTRL_WUPS_WOL_ 0x00000020 230 #define PMT_CTRL_WUPS_MULTI_ 0x00000030 231 #define PMT_CTRL_PME_IND_ 0x00000008 232 #define PMT_CTRL_PME_POL_ 0x00000004 233 #define PMT_CTRL_PME_EN_ 0x00000002 234 #define PMT_CTRL_READY_ 0x00000001 235 236 #define GPIO_CFG 0x88 237 #define GPIO_CFG_LED3_EN_ 0x40000000 238 #define GPIO_CFG_LED2_EN_ 0x20000000 239 #define GPIO_CFG_LED1_EN_ 0x10000000 240 #define GPIO_CFG_GPIO2_INT_POL_ 0x04000000 241 #define GPIO_CFG_GPIO1_INT_POL_ 0x02000000 242 #define GPIO_CFG_GPIO0_INT_POL_ 0x01000000 243 #define GPIO_CFG_EEPR_EN_ 0x00700000 244 #define GPIO_CFG_GPIOBUF2_ 0x00040000 245 #define GPIO_CFG_GPIOBUF1_ 0x00020000 246 #define GPIO_CFG_GPIOBUF0_ 0x00010000 247 #define GPIO_CFG_GPIODIR2_ 0x00000400 248 #define GPIO_CFG_GPIODIR1_ 0x00000200 249 #define GPIO_CFG_GPIODIR0_ 0x00000100 250 #define GPIO_CFG_GPIOD4_ 0x00000020 251 #define GPIO_CFG_GPIOD3_ 0x00000010 252 #define GPIO_CFG_GPIOD2_ 0x00000004 253 #define GPIO_CFG_GPIOD1_ 0x00000002 254 #define GPIO_CFG_GPIOD0_ 0x00000001 255 256 #define GPT_CFG 0x8C 257 #define GPT_CFG_TIMER_EN_ 0x20000000 258 #define GPT_CFG_GPT_LOAD_ 0x0000FFFF 259 260 #define GPT_CNT 0x90 261 #define GPT_CNT_GPT_CNT_ 0x0000FFFF 262 263 #define WORD_SWAP 0x98 264 265 #define FREE_RUN 0x9C 266 267 #define RX_DROP 0xA0 268 269 #define MAC_CSR_CMD 0xA4 270 #define MAC_CSR_CMD_CSR_BUSY_ 0x80000000 271 #define MAC_CSR_CMD_R_NOT_W_ 0x40000000 272 #define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF 273 274 #define MAC_CSR_DATA 0xA8 275 276 #define AFC_CFG 0xAC 277 #define AFC_CFG_AFC_HI_ 0x00FF0000 278 #define AFC_CFG_AFC_LO_ 0x0000FF00 279 #define AFC_CFG_BACK_DUR_ 0x000000F0 280 #define AFC_CFG_FCMULT_ 0x00000008 281 #define AFC_CFG_FCBRD_ 0x00000004 282 #define AFC_CFG_FCADD_ 0x00000002 283 #define AFC_CFG_FCANY_ 0x00000001 284 285 #define E2P_CMD 0xB0 286 #define E2P_CMD_EPC_BUSY_ 0x80000000 287 #define E2P_CMD_EPC_CMD_ 0x70000000 288 #define E2P_CMD_EPC_CMD_READ_ 0x00000000 289 #define E2P_CMD_EPC_CMD_EWDS_ 0x10000000 290 #define E2P_CMD_EPC_CMD_EWEN_ 0x20000000 291 #define E2P_CMD_EPC_CMD_WRITE_ 0x30000000 292 #define E2P_CMD_EPC_CMD_WRAL_ 0x40000000 293 #define E2P_CMD_EPC_CMD_ERASE_ 0x50000000 294 #define E2P_CMD_EPC_CMD_ERAL_ 0x60000000 295 #define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000 296 #define E2P_CMD_EPC_TIMEOUT_ 0x00000200 297 #define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100 298 #define E2P_CMD_EPC_ADDR_ 0x000000FF 299 300 #define E2P_DATA 0xB4 301 #define E2P_DATA_EEPROM_DATA_ 0x000000FF 302 #define LAN_REGISTER_EXTENT 0x00000100 303 304 /* 305 * MAC Control and Status Register (Indirect Address) 306 * Offset (through the MAC_CSR CMD and DATA port) 307 */ 308 #define MAC_CR 0x01 309 #define MAC_CR_RXALL_ 0x80000000 310 #define MAC_CR_HBDIS_ 0x10000000 311 #define MAC_CR_RCVOWN_ 0x00800000 312 #define MAC_CR_LOOPBK_ 0x00200000 313 #define MAC_CR_FDPX_ 0x00100000 314 #define MAC_CR_MCPAS_ 0x00080000 315 #define MAC_CR_PRMS_ 0x00040000 316 #define MAC_CR_INVFILT_ 0x00020000 317 #define MAC_CR_PASSBAD_ 0x00010000 318 #define MAC_CR_HFILT_ 0x00008000 319 #define MAC_CR_HPFILT_ 0x00002000 320 #define MAC_CR_LCOLL_ 0x00001000 321 #define MAC_CR_BCAST_ 0x00000800 322 #define MAC_CR_DISRTY_ 0x00000400 323 #define MAC_CR_PADSTR_ 0x00000100 324 #define MAC_CR_BOLMT_MASK_ 0x000000C0 325 #define MAC_CR_DFCHK_ 0x00000020 326 #define MAC_CR_TXEN_ 0x00000008 327 #define MAC_CR_RXEN_ 0x00000004 328 329 #define ADDRH 0x02 330 331 #define ADDRL 0x03 332 333 #define HASHH 0x04 334 335 #define HASHL 0x05 336 337 #define MII_ACC 0x06 338 #define MII_ACC_PHY_ADDR_ 0x0000F800 339 #define MII_ACC_MIIRINDA_ 0x000007C0 340 #define MII_ACC_MII_WRITE_ 0x00000002 341 #define MII_ACC_MII_BUSY_ 0x00000001 342 343 #define MII_DATA 0x07 344 345 #define FLOW 0x08 346 #define FLOW_FCPT_ 0xFFFF0000 347 #define FLOW_FCPASS_ 0x00000004 348 #define FLOW_FCEN_ 0x00000002 349 #define FLOW_FCBSY_ 0x00000001 350 351 #define VLAN1 0x09 352 353 #define VLAN2 0x0A 354 355 #define WUFF 0x0B 356 357 #define WUCSR 0x0C 358 #define WUCSR_GUE_ 0x00000200 359 #define WUCSR_WUFR_ 0x00000040 360 #define WUCSR_MPR_ 0x00000020 361 #define WUCSR_WAKE_EN_ 0x00000004 362 #define WUCSR_MPEN_ 0x00000002 363 364 /* 365 * Phy definitions (vendor-specific) 366 */ 367 #define LAN9118_PHY_ID 0x00C0001C 368 369 #define MII_INTSTS 0x1D 370 371 #define MII_INTMSK 0x1E 372 #define PHY_INTMSK_AN_RCV_ (1 << 1) 373 #define PHY_INTMSK_PDFAULT_ (1 << 2) 374 #define PHY_INTMSK_AN_ACK_ (1 << 3) 375 #define PHY_INTMSK_LNKDOWN_ (1 << 4) 376 #define PHY_INTMSK_RFAULT_ (1 << 5) 377 #define PHY_INTMSK_AN_COMP_ (1 << 6) 378 #define PHY_INTMSK_ENERGYON_ (1 << 7) 379 #define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ | \ 380 PHY_INTMSK_AN_COMP_ | \ 381 PHY_INTMSK_RFAULT_ | \ 382 PHY_INTMSK_LNKDOWN_) 383 384 #define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP | \ 385 ADVERTISE_PAUSE_ASYM) 386 387 #define LPA_PAUSE_ALL (LPA_PAUSE_CAP | \ 388 LPA_PAUSE_ASYM) 389 390 #endif /* __SMSC911X_H__ */ 391