1 /*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@lxorguk.ukuu.org.uk>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62 */
63
64 #define DRV_NAME "dmfe"
65 #define DRV_VERSION "1.36.4"
66 #define DRV_RELDATE "2002-01-17"
67
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/string.h>
71 #include <linux/timer.h>
72 #include <linux/ptrace.h>
73 #include <linux/errno.h>
74 #include <linux/ioport.h>
75 #include <linux/slab.h>
76 #include <linux/interrupt.h>
77 #include <linux/pci.h>
78 #include <linux/dma-mapping.h>
79 #include <linux/init.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/ethtool.h>
83 #include <linux/skbuff.h>
84 #include <linux/delay.h>
85 #include <linux/spinlock.h>
86 #include <linux/crc32.h>
87 #include <linux/bitops.h>
88
89 #include <asm/processor.h>
90 #include <asm/io.h>
91 #include <asm/dma.h>
92 #include <asm/uaccess.h>
93 #include <asm/irq.h>
94
95
96 /* Board/System/Debug information/definition ---------------- */
97 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
98 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
99 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
100 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
101
102 #define DM9102_IO_SIZE 0x80
103 #define DM9102A_IO_SIZE 0x100
104 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
105 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
106 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
107 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
108 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
109 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
110 #define TX_BUF_ALLOC 0x600
111 #define RX_ALLOC_SIZE 0x620
112 #define DM910X_RESET 1
113 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
114 #define CR6_DEFAULT 0x00080000 /* HD */
115 #define CR7_DEFAULT 0x180c1
116 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
117 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
118 #define MAX_PACKET_SIZE 1514
119 #define DMFE_MAX_MULTICAST 14
120 #define RX_COPY_SIZE 100
121 #define MAX_CHECK_PACKET 0x8000
122 #define DM9801_NOISE_FLOOR 8
123 #define DM9802_NOISE_FLOOR 5
124
125 #define DMFE_WOL_LINKCHANGE 0x20000000
126 #define DMFE_WOL_SAMPLEPACKET 0x10000000
127 #define DMFE_WOL_MAGICPACKET 0x08000000
128
129
130 #define DMFE_10MHF 0
131 #define DMFE_100MHF 1
132 #define DMFE_10MFD 4
133 #define DMFE_100MFD 5
134 #define DMFE_AUTO 8
135 #define DMFE_1M_HPNA 0x10
136
137 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
138 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
139 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
140 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
141 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
142 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
143
144 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
145 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
146 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
147
148 #define DMFE_DBUG(dbug_now, msg, value) \
149 do { \
150 if (dmfe_debug || (dbug_now)) \
151 printk(KERN_ERR DRV_NAME ": %s %lx\n",\
152 (msg), (long) (value)); \
153 } while (0)
154
155 #define SHOW_MEDIA_TYPE(mode) \
156 printk (KERN_INFO DRV_NAME ": Change Speed to %sMhz %s duplex\n" , \
157 (mode & 1) ? "100":"10", (mode & 4) ? "full":"half");
158
159
160 /* CR9 definition: SROM/MII */
161 #define CR9_SROM_READ 0x4800
162 #define CR9_SRCS 0x1
163 #define CR9_SRCLK 0x2
164 #define CR9_CRDOUT 0x8
165 #define SROM_DATA_0 0x0
166 #define SROM_DATA_1 0x4
167 #define PHY_DATA_1 0x20000
168 #define PHY_DATA_0 0x00000
169 #define MDCLKH 0x10000
170
171 #define PHY_POWER_DOWN 0x800
172
173 #define SROM_V41_CODE 0x14
174
175 #define SROM_CLK_WRITE(data, ioaddr) \
176 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
177 udelay(5); \
178 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
179 udelay(5); \
180 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
181 udelay(5);
182
183 #define __CHK_IO_SIZE(pci_id, dev_rev) \
184 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
185 DM9102A_IO_SIZE: DM9102_IO_SIZE)
186
187 #define CHK_IO_SIZE(pci_dev) \
188 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
189 (pci_dev)->revision))
190
191 /* Sten Check */
192 #define DEVICE net_device
193
194 /* Structure/enum declaration ------------------------------- */
195 struct tx_desc {
196 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
197 char *tx_buf_ptr; /* Data for us */
198 struct tx_desc *next_tx_desc;
199 } __attribute__(( aligned(32) ));
200
201 struct rx_desc {
202 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
203 struct sk_buff *rx_skb_ptr; /* Data for us */
204 struct rx_desc *next_rx_desc;
205 } __attribute__(( aligned(32) ));
206
207 struct dmfe_board_info {
208 u32 chip_id; /* Chip vendor/Device ID */
209 u8 chip_revision; /* Chip revision */
210 struct DEVICE *next_dev; /* next device */
211 struct pci_dev *pdev; /* PCI device */
212 spinlock_t lock;
213
214 long ioaddr; /* I/O base address */
215 u32 cr0_data;
216 u32 cr5_data;
217 u32 cr6_data;
218 u32 cr7_data;
219 u32 cr15_data;
220
221 /* pointer for memory physical address */
222 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
223 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
224 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
225 dma_addr_t first_tx_desc_dma;
226 dma_addr_t first_rx_desc_dma;
227
228 /* descriptor pointer */
229 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
230 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
231 unsigned char *desc_pool_ptr; /* descriptor pool memory */
232 struct tx_desc *first_tx_desc;
233 struct tx_desc *tx_insert_ptr;
234 struct tx_desc *tx_remove_ptr;
235 struct rx_desc *first_rx_desc;
236 struct rx_desc *rx_insert_ptr;
237 struct rx_desc *rx_ready_ptr; /* packet come pointer */
238 unsigned long tx_packet_cnt; /* transmitted packet count */
239 unsigned long tx_queue_cnt; /* wait to send packet count */
240 unsigned long rx_avail_cnt; /* available rx descriptor count */
241 unsigned long interval_rx_cnt; /* rx packet count a callback time */
242
243 u16 HPNA_command; /* For HPNA register 16 */
244 u16 HPNA_timer; /* For HPNA remote device check */
245 u16 dbug_cnt;
246 u16 NIC_capability; /* NIC media capability */
247 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
248
249 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
250 u8 chip_type; /* Keep DM9102A chip type */
251 u8 media_mode; /* user specify media mode */
252 u8 op_mode; /* real work media mode */
253 u8 phy_addr;
254 u8 wait_reset; /* Hardware failed, need to reset */
255 u8 dm910x_chk_mode; /* Operating mode check */
256 u8 first_in_callback; /* Flag to record state */
257 u8 wol_mode; /* user WOL settings */
258 struct timer_list timer;
259
260 /* Driver defined statistic counter */
261 unsigned long tx_fifo_underrun;
262 unsigned long tx_loss_carrier;
263 unsigned long tx_no_carrier;
264 unsigned long tx_late_collision;
265 unsigned long tx_excessive_collision;
266 unsigned long tx_jabber_timeout;
267 unsigned long reset_count;
268 unsigned long reset_cr8;
269 unsigned long reset_fatal;
270 unsigned long reset_TXtimeout;
271
272 /* NIC SROM data */
273 unsigned char srom[128];
274 };
275
276 enum dmfe_offsets {
277 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
278 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
279 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
280 DCR15 = 0x78
281 };
282
283 enum dmfe_CR6_bits {
284 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
285 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
286 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
287 };
288
289 /* Global variable declaration ----------------------------- */
290 static int __devinitdata printed_version;
291 static char version[] __devinitdata =
292 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
293 DRV_VERSION " (" DRV_RELDATE ")\n";
294
295 static int dmfe_debug;
296 static unsigned char dmfe_media_mode = DMFE_AUTO;
297 static u32 dmfe_cr6_user_set;
298
299 /* For module input parameter */
300 static int debug;
301 static u32 cr6set;
302 static unsigned char mode = 8;
303 static u8 chkmode = 1;
304 static u8 HPNA_mode; /* Default: Low Power/High Speed */
305 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
306 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
307 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
308 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
309 4: TX pause packet */
310
311
312 /* function declaration ------------------------------------- */
313 static int dmfe_open(struct DEVICE *);
314 static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
315 static int dmfe_stop(struct DEVICE *);
316 static void dmfe_set_filter_mode(struct DEVICE *);
317 static const struct ethtool_ops netdev_ethtool_ops;
318 static u16 read_srom_word(long ,int);
319 static irqreturn_t dmfe_interrupt(int , void *);
320 #ifdef CONFIG_NET_POLL_CONTROLLER
321 static void poll_dmfe (struct net_device *dev);
322 #endif
323 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
324 static void allocate_rx_buffer(struct dmfe_board_info *);
325 static void update_cr6(u32, unsigned long);
326 static void send_filter_frame(struct DEVICE * ,int);
327 static void dm9132_id_table(struct DEVICE * ,int);
328 static u16 phy_read(unsigned long, u8, u8, u32);
329 static void phy_write(unsigned long, u8, u8, u16, u32);
330 static void phy_write_1bit(unsigned long, u32);
331 static u16 phy_read_1bit(unsigned long);
332 static u8 dmfe_sense_speed(struct dmfe_board_info *);
333 static void dmfe_process_mode(struct dmfe_board_info *);
334 static void dmfe_timer(unsigned long);
335 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
336 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
337 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
338 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
339 static void dmfe_dynamic_reset(struct DEVICE *);
340 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
341 static void dmfe_init_dm910x(struct DEVICE *);
342 static void dmfe_parse_srom(struct dmfe_board_info *);
343 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
344 static void dmfe_program_DM9802(struct dmfe_board_info *);
345 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
346 static void dmfe_set_phyxcer(struct dmfe_board_info *);
347
348 /* DM910X network board routine ---------------------------- */
349
350 static const struct net_device_ops netdev_ops = {
351 .ndo_open = dmfe_open,
352 .ndo_stop = dmfe_stop,
353 .ndo_start_xmit = dmfe_start_xmit,
354 .ndo_set_multicast_list = dmfe_set_filter_mode,
355 .ndo_change_mtu = eth_change_mtu,
356 .ndo_set_mac_address = eth_mac_addr,
357 .ndo_validate_addr = eth_validate_addr,
358 #ifdef CONFIG_NET_POLL_CONTROLLER
359 .ndo_poll_controller = poll_dmfe,
360 #endif
361 };
362
363 /*
364 * Search DM910X board ,allocate space and register it
365 */
366
dmfe_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)367 static int __devinit dmfe_init_one (struct pci_dev *pdev,
368 const struct pci_device_id *ent)
369 {
370 struct dmfe_board_info *db; /* board information structure */
371 struct net_device *dev;
372 u32 pci_pmr;
373 int i, err;
374
375 DMFE_DBUG(0, "dmfe_init_one()", 0);
376
377 if (!printed_version++)
378 printk(version);
379
380 /* Init network device */
381 dev = alloc_etherdev(sizeof(*db));
382 if (dev == NULL)
383 return -ENOMEM;
384 SET_NETDEV_DEV(dev, &pdev->dev);
385
386 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
387 printk(KERN_WARNING DRV_NAME
388 ": 32-bit PCI DMA not available.\n");
389 err = -ENODEV;
390 goto err_out_free;
391 }
392
393 /* Enable Master/IO access, Disable memory access */
394 err = pci_enable_device(pdev);
395 if (err)
396 goto err_out_free;
397
398 if (!pci_resource_start(pdev, 0)) {
399 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
400 err = -ENODEV;
401 goto err_out_disable;
402 }
403
404 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
405 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
406 err = -ENODEV;
407 goto err_out_disable;
408 }
409
410 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
411
412 /* Set Latency Timer 80h */
413 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
414 Need a PCI quirk.. */
415
416 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
417 #endif
418
419 if (pci_request_regions(pdev, DRV_NAME)) {
420 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
421 err = -ENODEV;
422 goto err_out_disable;
423 }
424
425 /* Init system & device */
426 db = netdev_priv(dev);
427
428 /* Allocate Tx/Rx descriptor memory */
429 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
430 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
431 if (!db->desc_pool_ptr)
432 goto err_out_res;
433
434 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
435 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
436 if (!db->buf_pool_ptr)
437 goto err_out_free_desc;
438
439 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
440 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
441 db->buf_pool_start = db->buf_pool_ptr;
442 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
443
444 db->chip_id = ent->driver_data;
445 db->ioaddr = pci_resource_start(pdev, 0);
446 db->chip_revision = pdev->revision;
447 db->wol_mode = 0;
448
449 db->pdev = pdev;
450
451 dev->base_addr = db->ioaddr;
452 dev->irq = pdev->irq;
453 pci_set_drvdata(pdev, dev);
454 dev->netdev_ops = &netdev_ops;
455 dev->ethtool_ops = &netdev_ethtool_ops;
456 netif_carrier_off(dev);
457 spin_lock_init(&db->lock);
458
459 pci_read_config_dword(pdev, 0x50, &pci_pmr);
460 pci_pmr &= 0x70000;
461 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
462 db->chip_type = 1; /* DM9102A E3 */
463 else
464 db->chip_type = 0;
465
466 /* read 64 word srom data */
467 for (i = 0; i < 64; i++)
468 ((__le16 *) db->srom)[i] =
469 cpu_to_le16(read_srom_word(db->ioaddr, i));
470
471 /* Set Node address */
472 for (i = 0; i < 6; i++)
473 dev->dev_addr[i] = db->srom[20 + i];
474
475 err = register_netdev (dev);
476 if (err)
477 goto err_out_free_buf;
478
479 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s, %pM, irq %d.\n",
480 dev->name,
481 ent->driver_data >> 16,
482 pci_name(pdev),
483 dev->dev_addr,
484 dev->irq);
485
486 pci_set_master(pdev);
487
488 return 0;
489
490 err_out_free_buf:
491 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
492 db->buf_pool_ptr, db->buf_pool_dma_ptr);
493 err_out_free_desc:
494 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
495 db->desc_pool_ptr, db->desc_pool_dma_ptr);
496 err_out_res:
497 pci_release_regions(pdev);
498 err_out_disable:
499 pci_disable_device(pdev);
500 err_out_free:
501 pci_set_drvdata(pdev, NULL);
502 free_netdev(dev);
503
504 return err;
505 }
506
507
dmfe_remove_one(struct pci_dev * pdev)508 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
509 {
510 struct net_device *dev = pci_get_drvdata(pdev);
511 struct dmfe_board_info *db = netdev_priv(dev);
512
513 DMFE_DBUG(0, "dmfe_remove_one()", 0);
514
515 if (dev) {
516
517 unregister_netdev(dev);
518
519 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
520 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
521 db->desc_pool_dma_ptr);
522 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
523 db->buf_pool_ptr, db->buf_pool_dma_ptr);
524 pci_release_regions(pdev);
525 free_netdev(dev); /* free board information */
526
527 pci_set_drvdata(pdev, NULL);
528 }
529
530 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
531 }
532
533
534 /*
535 * Open the interface.
536 * The interface is opened whenever "ifconfig" actives it.
537 */
538
dmfe_open(struct DEVICE * dev)539 static int dmfe_open(struct DEVICE *dev)
540 {
541 int ret;
542 struct dmfe_board_info *db = netdev_priv(dev);
543
544 DMFE_DBUG(0, "dmfe_open", 0);
545
546 ret = request_irq(dev->irq, &dmfe_interrupt,
547 IRQF_SHARED, dev->name, dev);
548 if (ret)
549 return ret;
550
551 /* system variable init */
552 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
553 db->tx_packet_cnt = 0;
554 db->tx_queue_cnt = 0;
555 db->rx_avail_cnt = 0;
556 db->wait_reset = 0;
557
558 db->first_in_callback = 0;
559 db->NIC_capability = 0xf; /* All capability*/
560 db->PHY_reg4 = 0x1e0;
561
562 /* CR6 operation mode decision */
563 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
564 (db->chip_revision >= 0x30) ) {
565 db->cr6_data |= DMFE_TXTH_256;
566 db->cr0_data = CR0_DEFAULT;
567 db->dm910x_chk_mode=4; /* Enter the normal mode */
568 } else {
569 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
570 db->cr0_data = 0;
571 db->dm910x_chk_mode = 1; /* Enter the check mode */
572 }
573
574 /* Initilize DM910X board */
575 dmfe_init_dm910x(dev);
576
577 /* Active System Interface */
578 netif_wake_queue(dev);
579
580 /* set and active a timer process */
581 init_timer(&db->timer);
582 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
583 db->timer.data = (unsigned long)dev;
584 db->timer.function = &dmfe_timer;
585 add_timer(&db->timer);
586
587 return 0;
588 }
589
590
591 /* Initilize DM910X board
592 * Reset DM910X board
593 * Initilize TX/Rx descriptor chain structure
594 * Send the set-up frame
595 * Enable Tx/Rx machine
596 */
597
dmfe_init_dm910x(struct DEVICE * dev)598 static void dmfe_init_dm910x(struct DEVICE *dev)
599 {
600 struct dmfe_board_info *db = netdev_priv(dev);
601 unsigned long ioaddr = db->ioaddr;
602
603 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
604
605 /* Reset DM910x MAC controller */
606 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
607 udelay(100);
608 outl(db->cr0_data, ioaddr + DCR0);
609 udelay(5);
610
611 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
612 db->phy_addr = 1;
613
614 /* Parser SROM and media mode */
615 dmfe_parse_srom(db);
616 db->media_mode = dmfe_media_mode;
617
618 /* RESET Phyxcer Chip by GPR port bit 7 */
619 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
620 if (db->chip_id == PCI_DM9009_ID) {
621 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
622 mdelay(300); /* Delay 300 ms */
623 }
624 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
625
626 /* Process Phyxcer Media Mode */
627 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
628 dmfe_set_phyxcer(db);
629
630 /* Media Mode Process */
631 if ( !(db->media_mode & DMFE_AUTO) )
632 db->op_mode = db->media_mode; /* Force Mode */
633
634 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
635 dmfe_descriptor_init(db, ioaddr);
636
637 /* Init CR6 to program DM910x operation */
638 update_cr6(db->cr6_data, ioaddr);
639
640 /* Send setup frame */
641 if (db->chip_id == PCI_DM9132_ID)
642 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
643 else
644 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
645
646 /* Init CR7, interrupt active bit */
647 db->cr7_data = CR7_DEFAULT;
648 outl(db->cr7_data, ioaddr + DCR7);
649
650 /* Init CR15, Tx jabber and Rx watchdog timer */
651 outl(db->cr15_data, ioaddr + DCR15);
652
653 /* Enable DM910X Tx/Rx function */
654 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
655 update_cr6(db->cr6_data, ioaddr);
656 }
657
658
659 /*
660 * Hardware start transmission.
661 * Send a packet to media from the upper layer.
662 */
663
dmfe_start_xmit(struct sk_buff * skb,struct DEVICE * dev)664 static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
665 {
666 struct dmfe_board_info *db = netdev_priv(dev);
667 struct tx_desc *txptr;
668 unsigned long flags;
669
670 DMFE_DBUG(0, "dmfe_start_xmit", 0);
671
672 /* Resource flag check */
673 netif_stop_queue(dev);
674
675 /* Too large packet check */
676 if (skb->len > MAX_PACKET_SIZE) {
677 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
678 dev_kfree_skb(skb);
679 return 0;
680 }
681
682 spin_lock_irqsave(&db->lock, flags);
683
684 /* No Tx resource check, it never happen nromally */
685 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
686 spin_unlock_irqrestore(&db->lock, flags);
687 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n",
688 db->tx_queue_cnt);
689 return 1;
690 }
691
692 /* Disable NIC interrupt */
693 outl(0, dev->base_addr + DCR7);
694
695 /* transmit this packet */
696 txptr = db->tx_insert_ptr;
697 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
698 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
699
700 /* Point to next transmit free descriptor */
701 db->tx_insert_ptr = txptr->next_tx_desc;
702
703 /* Transmit Packet Process */
704 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
705 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
706 db->tx_packet_cnt++; /* Ready to send */
707 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
708 dev->trans_start = jiffies; /* saved time stamp */
709 } else {
710 db->tx_queue_cnt++; /* queue TX packet */
711 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
712 }
713
714 /* Tx resource check */
715 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
716 netif_wake_queue(dev);
717
718 /* Restore CR7 to enable interrupt */
719 spin_unlock_irqrestore(&db->lock, flags);
720 outl(db->cr7_data, dev->base_addr + DCR7);
721
722 /* free this SKB */
723 dev_kfree_skb(skb);
724
725 return 0;
726 }
727
728
729 /*
730 * Stop the interface.
731 * The interface is stopped when it is brought.
732 */
733
dmfe_stop(struct DEVICE * dev)734 static int dmfe_stop(struct DEVICE *dev)
735 {
736 struct dmfe_board_info *db = netdev_priv(dev);
737 unsigned long ioaddr = dev->base_addr;
738
739 DMFE_DBUG(0, "dmfe_stop", 0);
740
741 /* disable system */
742 netif_stop_queue(dev);
743
744 /* deleted timer */
745 del_timer_sync(&db->timer);
746
747 /* Reset & stop DM910X board */
748 outl(DM910X_RESET, ioaddr + DCR0);
749 udelay(5);
750 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
751
752 /* free interrupt */
753 free_irq(dev->irq, dev);
754
755 /* free allocated rx buffer */
756 dmfe_free_rxbuffer(db);
757
758 #if 0
759 /* show statistic counter */
760 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx"
761 " LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
762 db->tx_fifo_underrun, db->tx_excessive_collision,
763 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
764 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
765 db->reset_fatal, db->reset_TXtimeout);
766 #endif
767
768 return 0;
769 }
770
771
772 /*
773 * DM9102 insterrupt handler
774 * receive the packet to upper layer, free the transmitted packet
775 */
776
dmfe_interrupt(int irq,void * dev_id)777 static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
778 {
779 struct DEVICE *dev = dev_id;
780 struct dmfe_board_info *db = netdev_priv(dev);
781 unsigned long ioaddr = dev->base_addr;
782 unsigned long flags;
783
784 DMFE_DBUG(0, "dmfe_interrupt()", 0);
785
786 spin_lock_irqsave(&db->lock, flags);
787
788 /* Got DM910X status */
789 db->cr5_data = inl(ioaddr + DCR5);
790 outl(db->cr5_data, ioaddr + DCR5);
791 if ( !(db->cr5_data & 0xc1) ) {
792 spin_unlock_irqrestore(&db->lock, flags);
793 return IRQ_HANDLED;
794 }
795
796 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
797 outl(0, ioaddr + DCR7);
798
799 /* Check system status */
800 if (db->cr5_data & 0x2000) {
801 /* system bus error happen */
802 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
803 db->reset_fatal++;
804 db->wait_reset = 1; /* Need to RESET */
805 spin_unlock_irqrestore(&db->lock, flags);
806 return IRQ_HANDLED;
807 }
808
809 /* Received the coming packet */
810 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
811 dmfe_rx_packet(dev, db);
812
813 /* reallocate rx descriptor buffer */
814 if (db->rx_avail_cnt<RX_DESC_CNT)
815 allocate_rx_buffer(db);
816
817 /* Free the transmitted descriptor */
818 if ( db->cr5_data & 0x01)
819 dmfe_free_tx_pkt(dev, db);
820
821 /* Mode Check */
822 if (db->dm910x_chk_mode & 0x2) {
823 db->dm910x_chk_mode = 0x4;
824 db->cr6_data |= 0x100;
825 update_cr6(db->cr6_data, db->ioaddr);
826 }
827
828 /* Restore CR7 to enable interrupt mask */
829 outl(db->cr7_data, ioaddr + DCR7);
830
831 spin_unlock_irqrestore(&db->lock, flags);
832 return IRQ_HANDLED;
833 }
834
835
836 #ifdef CONFIG_NET_POLL_CONTROLLER
837 /*
838 * Polling 'interrupt' - used by things like netconsole to send skbs
839 * without having to re-enable interrupts. It's not called while
840 * the interrupt routine is executing.
841 */
842
poll_dmfe(struct net_device * dev)843 static void poll_dmfe (struct net_device *dev)
844 {
845 /* disable_irq here is not very nice, but with the lockless
846 interrupt handler we have no other choice. */
847 disable_irq(dev->irq);
848 dmfe_interrupt (dev->irq, dev);
849 enable_irq(dev->irq);
850 }
851 #endif
852
853 /*
854 * Free TX resource after TX complete
855 */
856
dmfe_free_tx_pkt(struct DEVICE * dev,struct dmfe_board_info * db)857 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
858 {
859 struct tx_desc *txptr;
860 unsigned long ioaddr = dev->base_addr;
861 u32 tdes0;
862
863 txptr = db->tx_remove_ptr;
864 while(db->tx_packet_cnt) {
865 tdes0 = le32_to_cpu(txptr->tdes0);
866 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
867 if (tdes0 & 0x80000000)
868 break;
869
870 /* A packet sent completed */
871 db->tx_packet_cnt--;
872 dev->stats.tx_packets++;
873
874 /* Transmit statistic counter */
875 if ( tdes0 != 0x7fffffff ) {
876 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
877 dev->stats.collisions += (tdes0 >> 3) & 0xf;
878 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
879 if (tdes0 & TDES0_ERR_MASK) {
880 dev->stats.tx_errors++;
881
882 if (tdes0 & 0x0002) { /* UnderRun */
883 db->tx_fifo_underrun++;
884 if ( !(db->cr6_data & CR6_SFT) ) {
885 db->cr6_data = db->cr6_data | CR6_SFT;
886 update_cr6(db->cr6_data, db->ioaddr);
887 }
888 }
889 if (tdes0 & 0x0100)
890 db->tx_excessive_collision++;
891 if (tdes0 & 0x0200)
892 db->tx_late_collision++;
893 if (tdes0 & 0x0400)
894 db->tx_no_carrier++;
895 if (tdes0 & 0x0800)
896 db->tx_loss_carrier++;
897 if (tdes0 & 0x4000)
898 db->tx_jabber_timeout++;
899 }
900 }
901
902 txptr = txptr->next_tx_desc;
903 }/* End of while */
904
905 /* Update TX remove pointer to next */
906 db->tx_remove_ptr = txptr;
907
908 /* Send the Tx packet in queue */
909 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
910 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
911 db->tx_packet_cnt++; /* Ready to send */
912 db->tx_queue_cnt--;
913 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
914 dev->trans_start = jiffies; /* saved time stamp */
915 }
916
917 /* Resource available check */
918 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
919 netif_wake_queue(dev); /* Active upper layer, send again */
920 }
921
922
923 /*
924 * Calculate the CRC valude of the Rx packet
925 * flag = 1 : return the reverse CRC (for the received packet CRC)
926 * 0 : return the normal CRC (for Hash Table index)
927 */
928
cal_CRC(unsigned char * Data,unsigned int Len,u8 flag)929 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
930 {
931 u32 crc = crc32(~0, Data, Len);
932 if (flag) crc = ~crc;
933 return crc;
934 }
935
936
937 /*
938 * Receive the come packet and pass to upper layer
939 */
940
dmfe_rx_packet(struct DEVICE * dev,struct dmfe_board_info * db)941 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
942 {
943 struct rx_desc *rxptr;
944 struct sk_buff *skb, *newskb;
945 int rxlen;
946 u32 rdes0;
947
948 rxptr = db->rx_ready_ptr;
949
950 while(db->rx_avail_cnt) {
951 rdes0 = le32_to_cpu(rxptr->rdes0);
952 if (rdes0 & 0x80000000) /* packet owner check */
953 break;
954
955 db->rx_avail_cnt--;
956 db->interval_rx_cnt++;
957
958 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
959 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
960
961 if ( (rdes0 & 0x300) != 0x300) {
962 /* A packet without First/Last flag */
963 /* reuse this SKB */
964 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
965 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
966 } else {
967 /* A packet with First/Last flag */
968 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
969
970 /* error summary bit check */
971 if (rdes0 & 0x8000) {
972 /* This is a error packet */
973 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
974 dev->stats.rx_errors++;
975 if (rdes0 & 1)
976 dev->stats.rx_fifo_errors++;
977 if (rdes0 & 2)
978 dev->stats.rx_crc_errors++;
979 if (rdes0 & 0x80)
980 dev->stats.rx_length_errors++;
981 }
982
983 if ( !(rdes0 & 0x8000) ||
984 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
985 skb = rxptr->rx_skb_ptr;
986
987 /* Received Packet CRC check need or not */
988 if ( (db->dm910x_chk_mode & 1) &&
989 (cal_CRC(skb->data, rxlen, 1) !=
990 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
991 /* Found a error received packet */
992 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
993 db->dm910x_chk_mode = 3;
994 } else {
995 /* Good packet, send to upper layer */
996 /* Shorst packet used new SKB */
997 if ((rxlen < RX_COPY_SIZE) &&
998 ((newskb = dev_alloc_skb(rxlen + 2))
999 != NULL)) {
1000
1001 skb = newskb;
1002 /* size less than COPY_SIZE, allocate a rxlen SKB */
1003 skb_reserve(skb, 2); /* 16byte align */
1004 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1005 skb_put(skb, rxlen),
1006 rxlen);
1007 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1008 } else
1009 skb_put(skb, rxlen);
1010
1011 skb->protocol = eth_type_trans(skb, dev);
1012 netif_rx(skb);
1013 dev->stats.rx_packets++;
1014 dev->stats.rx_bytes += rxlen;
1015 }
1016 } else {
1017 /* Reuse SKB buffer when the packet is error */
1018 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1019 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1020 }
1021 }
1022
1023 rxptr = rxptr->next_rx_desc;
1024 }
1025
1026 db->rx_ready_ptr = rxptr;
1027 }
1028
1029 /*
1030 * Set DM910X multicast address
1031 */
1032
dmfe_set_filter_mode(struct DEVICE * dev)1033 static void dmfe_set_filter_mode(struct DEVICE * dev)
1034 {
1035 struct dmfe_board_info *db = netdev_priv(dev);
1036 unsigned long flags;
1037
1038 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1039 spin_lock_irqsave(&db->lock, flags);
1040
1041 if (dev->flags & IFF_PROMISC) {
1042 DMFE_DBUG(0, "Enable PROM Mode", 0);
1043 db->cr6_data |= CR6_PM | CR6_PBF;
1044 update_cr6(db->cr6_data, db->ioaddr);
1045 spin_unlock_irqrestore(&db->lock, flags);
1046 return;
1047 }
1048
1049 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1050 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1051 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1052 db->cr6_data |= CR6_PAM;
1053 spin_unlock_irqrestore(&db->lock, flags);
1054 return;
1055 }
1056
1057 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1058 if (db->chip_id == PCI_DM9132_ID)
1059 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1060 else
1061 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1062 spin_unlock_irqrestore(&db->lock, flags);
1063 }
1064
1065 /*
1066 * Ethtool interace
1067 */
1068
dmfe_ethtool_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1069 static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1070 struct ethtool_drvinfo *info)
1071 {
1072 struct dmfe_board_info *np = netdev_priv(dev);
1073
1074 strcpy(info->driver, DRV_NAME);
1075 strcpy(info->version, DRV_VERSION);
1076 if (np->pdev)
1077 strcpy(info->bus_info, pci_name(np->pdev));
1078 else
1079 sprintf(info->bus_info, "EISA 0x%lx %d",
1080 dev->base_addr, dev->irq);
1081 }
1082
dmfe_ethtool_set_wol(struct net_device * dev,struct ethtool_wolinfo * wolinfo)1083 static int dmfe_ethtool_set_wol(struct net_device *dev,
1084 struct ethtool_wolinfo *wolinfo)
1085 {
1086 struct dmfe_board_info *db = netdev_priv(dev);
1087
1088 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1089 WAKE_ARP | WAKE_MAGICSECURE))
1090 return -EOPNOTSUPP;
1091
1092 db->wol_mode = wolinfo->wolopts;
1093 return 0;
1094 }
1095
dmfe_ethtool_get_wol(struct net_device * dev,struct ethtool_wolinfo * wolinfo)1096 static void dmfe_ethtool_get_wol(struct net_device *dev,
1097 struct ethtool_wolinfo *wolinfo)
1098 {
1099 struct dmfe_board_info *db = netdev_priv(dev);
1100
1101 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1102 wolinfo->wolopts = db->wol_mode;
1103 return;
1104 }
1105
1106
1107 static const struct ethtool_ops netdev_ethtool_ops = {
1108 .get_drvinfo = dmfe_ethtool_get_drvinfo,
1109 .get_link = ethtool_op_get_link,
1110 .set_wol = dmfe_ethtool_set_wol,
1111 .get_wol = dmfe_ethtool_get_wol,
1112 };
1113
1114 /*
1115 * A periodic timer routine
1116 * Dynamic media sense, allocate Rx buffer...
1117 */
1118
dmfe_timer(unsigned long data)1119 static void dmfe_timer(unsigned long data)
1120 {
1121 u32 tmp_cr8;
1122 unsigned char tmp_cr12;
1123 struct DEVICE *dev = (struct DEVICE *) data;
1124 struct dmfe_board_info *db = netdev_priv(dev);
1125 unsigned long flags;
1126
1127 int link_ok, link_ok_phy;
1128
1129 DMFE_DBUG(0, "dmfe_timer()", 0);
1130 spin_lock_irqsave(&db->lock, flags);
1131
1132 /* Media mode process when Link OK before enter this route */
1133 if (db->first_in_callback == 0) {
1134 db->first_in_callback = 1;
1135 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1136 db->cr6_data &= ~0x40000;
1137 update_cr6(db->cr6_data, db->ioaddr);
1138 phy_write(db->ioaddr,
1139 db->phy_addr, 0, 0x1000, db->chip_id);
1140 db->cr6_data |= 0x40000;
1141 update_cr6(db->cr6_data, db->ioaddr);
1142 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1143 add_timer(&db->timer);
1144 spin_unlock_irqrestore(&db->lock, flags);
1145 return;
1146 }
1147 }
1148
1149
1150 /* Operating Mode Check */
1151 if ( (db->dm910x_chk_mode & 0x1) &&
1152 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1153 db->dm910x_chk_mode = 0x4;
1154
1155 /* Dynamic reset DM910X : system error or transmit time-out */
1156 tmp_cr8 = inl(db->ioaddr + DCR8);
1157 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1158 db->reset_cr8++;
1159 db->wait_reset = 1;
1160 }
1161 db->interval_rx_cnt = 0;
1162
1163 /* TX polling kick monitor */
1164 if ( db->tx_packet_cnt &&
1165 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1166 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1167
1168 /* TX Timeout */
1169 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1170 db->reset_TXtimeout++;
1171 db->wait_reset = 1;
1172 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1173 dev->name);
1174 }
1175 }
1176
1177 if (db->wait_reset) {
1178 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1179 db->reset_count++;
1180 dmfe_dynamic_reset(dev);
1181 db->first_in_callback = 0;
1182 db->timer.expires = DMFE_TIMER_WUT;
1183 add_timer(&db->timer);
1184 spin_unlock_irqrestore(&db->lock, flags);
1185 return;
1186 }
1187
1188 /* Link status check, Dynamic media type change */
1189 if (db->chip_id == PCI_DM9132_ID)
1190 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1191 else
1192 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1193
1194 if ( ((db->chip_id == PCI_DM9102_ID) &&
1195 (db->chip_revision == 0x30)) ||
1196 ((db->chip_id == PCI_DM9132_ID) &&
1197 (db->chip_revision == 0x10)) ) {
1198 /* DM9102A Chip */
1199 if (tmp_cr12 & 2)
1200 link_ok = 0;
1201 else
1202 link_ok = 1;
1203 }
1204 else
1205 /*0x43 is used instead of 0x3 because bit 6 should represent
1206 link status of external PHY */
1207 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1208
1209
1210 /* If chip reports that link is failed it could be because external
1211 PHY link status pin is not conected correctly to chip
1212 To be sure ask PHY too.
1213 */
1214
1215 /* need a dummy read because of PHY's register latch*/
1216 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1217 link_ok_phy = (phy_read (db->ioaddr,
1218 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1219
1220 if (link_ok_phy != link_ok) {
1221 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1222 link_ok = link_ok | link_ok_phy;
1223 }
1224
1225 if ( !link_ok && netif_carrier_ok(dev)) {
1226 /* Link Failed */
1227 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1228 netif_carrier_off(dev);
1229
1230 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1231 /* AUTO or force 1M Homerun/Longrun don't need */
1232 if ( !(db->media_mode & 0x38) )
1233 phy_write(db->ioaddr, db->phy_addr,
1234 0, 0x1000, db->chip_id);
1235
1236 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1237 if (db->media_mode & DMFE_AUTO) {
1238 /* 10/100M link failed, used 1M Home-Net */
1239 db->cr6_data|=0x00040000; /* bit18=1, MII */
1240 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1241 update_cr6(db->cr6_data, db->ioaddr);
1242 }
1243 } else if (!netif_carrier_ok(dev)) {
1244
1245 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1246
1247 /* Auto Sense Speed */
1248 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1249 netif_carrier_on(dev);
1250 SHOW_MEDIA_TYPE(db->op_mode);
1251 }
1252
1253 dmfe_process_mode(db);
1254 }
1255
1256 /* HPNA remote command check */
1257 if (db->HPNA_command & 0xf00) {
1258 db->HPNA_timer--;
1259 if (!db->HPNA_timer)
1260 dmfe_HPNA_remote_cmd_chk(db);
1261 }
1262
1263 /* Timer active again */
1264 db->timer.expires = DMFE_TIMER_WUT;
1265 add_timer(&db->timer);
1266 spin_unlock_irqrestore(&db->lock, flags);
1267 }
1268
1269
1270 /*
1271 * Dynamic reset the DM910X board
1272 * Stop DM910X board
1273 * Free Tx/Rx allocated memory
1274 * Reset DM910X board
1275 * Re-initilize DM910X board
1276 */
1277
dmfe_dynamic_reset(struct DEVICE * dev)1278 static void dmfe_dynamic_reset(struct DEVICE *dev)
1279 {
1280 struct dmfe_board_info *db = netdev_priv(dev);
1281
1282 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1283
1284 /* Sopt MAC controller */
1285 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1286 update_cr6(db->cr6_data, dev->base_addr);
1287 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1288 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1289
1290 /* Disable upper layer interface */
1291 netif_stop_queue(dev);
1292
1293 /* Free Rx Allocate buffer */
1294 dmfe_free_rxbuffer(db);
1295
1296 /* system variable init */
1297 db->tx_packet_cnt = 0;
1298 db->tx_queue_cnt = 0;
1299 db->rx_avail_cnt = 0;
1300 netif_carrier_off(dev);
1301 db->wait_reset = 0;
1302
1303 /* Re-initilize DM910X board */
1304 dmfe_init_dm910x(dev);
1305
1306 /* Restart upper layer interface */
1307 netif_wake_queue(dev);
1308 }
1309
1310
1311 /*
1312 * free all allocated rx buffer
1313 */
1314
dmfe_free_rxbuffer(struct dmfe_board_info * db)1315 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1316 {
1317 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1318
1319 /* free allocated rx buffer */
1320 while (db->rx_avail_cnt) {
1321 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1322 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1323 db->rx_avail_cnt--;
1324 }
1325 }
1326
1327
1328 /*
1329 * Reuse the SK buffer
1330 */
1331
dmfe_reuse_skb(struct dmfe_board_info * db,struct sk_buff * skb)1332 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1333 {
1334 struct rx_desc *rxptr = db->rx_insert_ptr;
1335
1336 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1337 rxptr->rx_skb_ptr = skb;
1338 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1339 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1340 wmb();
1341 rxptr->rdes0 = cpu_to_le32(0x80000000);
1342 db->rx_avail_cnt++;
1343 db->rx_insert_ptr = rxptr->next_rx_desc;
1344 } else
1345 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1346 }
1347
1348
1349 /*
1350 * Initialize transmit/Receive descriptor
1351 * Using Chain structure, and allocate Tx/Rx buffer
1352 */
1353
dmfe_descriptor_init(struct dmfe_board_info * db,unsigned long ioaddr)1354 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1355 {
1356 struct tx_desc *tmp_tx;
1357 struct rx_desc *tmp_rx;
1358 unsigned char *tmp_buf;
1359 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1360 dma_addr_t tmp_buf_dma;
1361 int i;
1362
1363 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1364
1365 /* tx descriptor start pointer */
1366 db->tx_insert_ptr = db->first_tx_desc;
1367 db->tx_remove_ptr = db->first_tx_desc;
1368 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1369
1370 /* rx descriptor start pointer */
1371 db->first_rx_desc = (void *)db->first_tx_desc +
1372 sizeof(struct tx_desc) * TX_DESC_CNT;
1373
1374 db->first_rx_desc_dma = db->first_tx_desc_dma +
1375 sizeof(struct tx_desc) * TX_DESC_CNT;
1376 db->rx_insert_ptr = db->first_rx_desc;
1377 db->rx_ready_ptr = db->first_rx_desc;
1378 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1379
1380 /* Init Transmit chain */
1381 tmp_buf = db->buf_pool_start;
1382 tmp_buf_dma = db->buf_pool_dma_start;
1383 tmp_tx_dma = db->first_tx_desc_dma;
1384 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1385 tmp_tx->tx_buf_ptr = tmp_buf;
1386 tmp_tx->tdes0 = cpu_to_le32(0);
1387 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1388 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1389 tmp_tx_dma += sizeof(struct tx_desc);
1390 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1391 tmp_tx->next_tx_desc = tmp_tx + 1;
1392 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1393 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1394 }
1395 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1396 tmp_tx->next_tx_desc = db->first_tx_desc;
1397
1398 /* Init Receive descriptor chain */
1399 tmp_rx_dma=db->first_rx_desc_dma;
1400 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1401 tmp_rx->rdes0 = cpu_to_le32(0);
1402 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1403 tmp_rx_dma += sizeof(struct rx_desc);
1404 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1405 tmp_rx->next_rx_desc = tmp_rx + 1;
1406 }
1407 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1408 tmp_rx->next_rx_desc = db->first_rx_desc;
1409
1410 /* pre-allocate Rx buffer */
1411 allocate_rx_buffer(db);
1412 }
1413
1414
1415 /*
1416 * Update CR6 value
1417 * Firstly stop DM910X , then written value and start
1418 */
1419
update_cr6(u32 cr6_data,unsigned long ioaddr)1420 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1421 {
1422 u32 cr6_tmp;
1423
1424 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1425 outl(cr6_tmp, ioaddr + DCR6);
1426 udelay(5);
1427 outl(cr6_data, ioaddr + DCR6);
1428 udelay(5);
1429 }
1430
1431
1432 /*
1433 * Send a setup frame for DM9132
1434 * This setup frame initilize DM910X address filter mode
1435 */
1436
dm9132_id_table(struct DEVICE * dev,int mc_cnt)1437 static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1438 {
1439 struct dev_mc_list *mcptr;
1440 u16 * addrptr;
1441 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1442 u32 hash_val;
1443 u16 i, hash_table[4];
1444
1445 DMFE_DBUG(0, "dm9132_id_table()", 0);
1446
1447 /* Node address */
1448 addrptr = (u16 *) dev->dev_addr;
1449 outw(addrptr[0], ioaddr);
1450 ioaddr += 4;
1451 outw(addrptr[1], ioaddr);
1452 ioaddr += 4;
1453 outw(addrptr[2], ioaddr);
1454 ioaddr += 4;
1455
1456 /* Clear Hash Table */
1457 for (i = 0; i < 4; i++)
1458 hash_table[i] = 0x0;
1459
1460 /* broadcast address */
1461 hash_table[3] = 0x8000;
1462
1463 /* the multicast address in Hash Table : 64 bits */
1464 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1465 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1466 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1467 }
1468
1469 /* Write the hash table to MAC MD table */
1470 for (i = 0; i < 4; i++, ioaddr += 4)
1471 outw(hash_table[i], ioaddr);
1472 }
1473
1474
1475 /*
1476 * Send a setup frame for DM9102/DM9102A
1477 * This setup frame initilize DM910X address filter mode
1478 */
1479
send_filter_frame(struct DEVICE * dev,int mc_cnt)1480 static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1481 {
1482 struct dmfe_board_info *db = netdev_priv(dev);
1483 struct dev_mc_list *mcptr;
1484 struct tx_desc *txptr;
1485 u16 * addrptr;
1486 u32 * suptr;
1487 int i;
1488
1489 DMFE_DBUG(0, "send_filter_frame()", 0);
1490
1491 txptr = db->tx_insert_ptr;
1492 suptr = (u32 *) txptr->tx_buf_ptr;
1493
1494 /* Node address */
1495 addrptr = (u16 *) dev->dev_addr;
1496 *suptr++ = addrptr[0];
1497 *suptr++ = addrptr[1];
1498 *suptr++ = addrptr[2];
1499
1500 /* broadcast address */
1501 *suptr++ = 0xffff;
1502 *suptr++ = 0xffff;
1503 *suptr++ = 0xffff;
1504
1505 /* fit the multicast address */
1506 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1507 addrptr = (u16 *) mcptr->dmi_addr;
1508 *suptr++ = addrptr[0];
1509 *suptr++ = addrptr[1];
1510 *suptr++ = addrptr[2];
1511 }
1512
1513 for (; i<14; i++) {
1514 *suptr++ = 0xffff;
1515 *suptr++ = 0xffff;
1516 *suptr++ = 0xffff;
1517 }
1518
1519 /* prepare the setup frame */
1520 db->tx_insert_ptr = txptr->next_tx_desc;
1521 txptr->tdes1 = cpu_to_le32(0x890000c0);
1522
1523 /* Resource Check and Send the setup packet */
1524 if (!db->tx_packet_cnt) {
1525 /* Resource Empty */
1526 db->tx_packet_cnt++;
1527 txptr->tdes0 = cpu_to_le32(0x80000000);
1528 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1529 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1530 update_cr6(db->cr6_data, dev->base_addr);
1531 dev->trans_start = jiffies;
1532 } else
1533 db->tx_queue_cnt++; /* Put in TX queue */
1534 }
1535
1536
1537 /*
1538 * Allocate rx buffer,
1539 * As possible as allocate maxiumn Rx buffer
1540 */
1541
allocate_rx_buffer(struct dmfe_board_info * db)1542 static void allocate_rx_buffer(struct dmfe_board_info *db)
1543 {
1544 struct rx_desc *rxptr;
1545 struct sk_buff *skb;
1546
1547 rxptr = db->rx_insert_ptr;
1548
1549 while(db->rx_avail_cnt < RX_DESC_CNT) {
1550 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1551 break;
1552 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1553 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1554 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1555 wmb();
1556 rxptr->rdes0 = cpu_to_le32(0x80000000);
1557 rxptr = rxptr->next_rx_desc;
1558 db->rx_avail_cnt++;
1559 }
1560
1561 db->rx_insert_ptr = rxptr;
1562 }
1563
1564
1565 /*
1566 * Read one word data from the serial ROM
1567 */
1568
read_srom_word(long ioaddr,int offset)1569 static u16 read_srom_word(long ioaddr, int offset)
1570 {
1571 int i;
1572 u16 srom_data = 0;
1573 long cr9_ioaddr = ioaddr + DCR9;
1574
1575 outl(CR9_SROM_READ, cr9_ioaddr);
1576 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1577
1578 /* Send the Read Command 110b */
1579 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1580 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1581 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1582
1583 /* Send the offset */
1584 for (i = 5; i >= 0; i--) {
1585 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1586 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1587 }
1588
1589 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1590
1591 for (i = 16; i > 0; i--) {
1592 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1593 udelay(5);
1594 srom_data = (srom_data << 1) |
1595 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1596 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1597 udelay(5);
1598 }
1599
1600 outl(CR9_SROM_READ, cr9_ioaddr);
1601 return srom_data;
1602 }
1603
1604
1605 /*
1606 * Auto sense the media mode
1607 */
1608
dmfe_sense_speed(struct dmfe_board_info * db)1609 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1610 {
1611 u8 ErrFlag = 0;
1612 u16 phy_mode;
1613
1614 /* CR6 bit18=0, select 10/100M */
1615 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1616
1617 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1618 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1619
1620 if ( (phy_mode & 0x24) == 0x24 ) {
1621 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1622 phy_mode = phy_read(db->ioaddr,
1623 db->phy_addr, 7, db->chip_id) & 0xf000;
1624 else /* DM9102/DM9102A */
1625 phy_mode = phy_read(db->ioaddr,
1626 db->phy_addr, 17, db->chip_id) & 0xf000;
1627 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1628 switch (phy_mode) {
1629 case 0x1000: db->op_mode = DMFE_10MHF; break;
1630 case 0x2000: db->op_mode = DMFE_10MFD; break;
1631 case 0x4000: db->op_mode = DMFE_100MHF; break;
1632 case 0x8000: db->op_mode = DMFE_100MFD; break;
1633 default: db->op_mode = DMFE_10MHF;
1634 ErrFlag = 1;
1635 break;
1636 }
1637 } else {
1638 db->op_mode = DMFE_10MHF;
1639 DMFE_DBUG(0, "Link Failed :", phy_mode);
1640 ErrFlag = 1;
1641 }
1642
1643 return ErrFlag;
1644 }
1645
1646
1647 /*
1648 * Set 10/100 phyxcer capability
1649 * AUTO mode : phyxcer register4 is NIC capability
1650 * Force mode: phyxcer register4 is the force media
1651 */
1652
dmfe_set_phyxcer(struct dmfe_board_info * db)1653 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1654 {
1655 u16 phy_reg;
1656
1657 /* Select 10/100M phyxcer */
1658 db->cr6_data &= ~0x40000;
1659 update_cr6(db->cr6_data, db->ioaddr);
1660
1661 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1662 if (db->chip_id == PCI_DM9009_ID) {
1663 phy_reg = phy_read(db->ioaddr,
1664 db->phy_addr, 18, db->chip_id) & ~0x1000;
1665
1666 phy_write(db->ioaddr,
1667 db->phy_addr, 18, phy_reg, db->chip_id);
1668 }
1669
1670 /* Phyxcer capability setting */
1671 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1672
1673 if (db->media_mode & DMFE_AUTO) {
1674 /* AUTO Mode */
1675 phy_reg |= db->PHY_reg4;
1676 } else {
1677 /* Force Mode */
1678 switch(db->media_mode) {
1679 case DMFE_10MHF: phy_reg |= 0x20; break;
1680 case DMFE_10MFD: phy_reg |= 0x40; break;
1681 case DMFE_100MHF: phy_reg |= 0x80; break;
1682 case DMFE_100MFD: phy_reg |= 0x100; break;
1683 }
1684 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1685 }
1686
1687 /* Write new capability to Phyxcer Reg4 */
1688 if ( !(phy_reg & 0x01e0)) {
1689 phy_reg|=db->PHY_reg4;
1690 db->media_mode|=DMFE_AUTO;
1691 }
1692 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1693
1694 /* Restart Auto-Negotiation */
1695 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1696 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1697 if ( !db->chip_type )
1698 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1699 }
1700
1701
1702 /*
1703 * Process op-mode
1704 * AUTO mode : PHY controller in Auto-negotiation Mode
1705 * Force mode: PHY controller in force mode with HUB
1706 * N-way force capability with SWITCH
1707 */
1708
dmfe_process_mode(struct dmfe_board_info * db)1709 static void dmfe_process_mode(struct dmfe_board_info *db)
1710 {
1711 u16 phy_reg;
1712
1713 /* Full Duplex Mode Check */
1714 if (db->op_mode & 0x4)
1715 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1716 else
1717 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1718
1719 /* Transciver Selection */
1720 if (db->op_mode & 0x10) /* 1M HomePNA */
1721 db->cr6_data |= 0x40000;/* External MII select */
1722 else
1723 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1724
1725 update_cr6(db->cr6_data, db->ioaddr);
1726
1727 /* 10/100M phyxcer force mode need */
1728 if ( !(db->media_mode & 0x18)) {
1729 /* Forece Mode */
1730 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1731 if ( !(phy_reg & 0x1) ) {
1732 /* parter without N-Way capability */
1733 phy_reg = 0x0;
1734 switch(db->op_mode) {
1735 case DMFE_10MHF: phy_reg = 0x0; break;
1736 case DMFE_10MFD: phy_reg = 0x100; break;
1737 case DMFE_100MHF: phy_reg = 0x2000; break;
1738 case DMFE_100MFD: phy_reg = 0x2100; break;
1739 }
1740 phy_write(db->ioaddr,
1741 db->phy_addr, 0, phy_reg, db->chip_id);
1742 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1743 mdelay(20);
1744 phy_write(db->ioaddr,
1745 db->phy_addr, 0, phy_reg, db->chip_id);
1746 }
1747 }
1748 }
1749
1750
1751 /*
1752 * Write a word to Phy register
1753 */
1754
phy_write(unsigned long iobase,u8 phy_addr,u8 offset,u16 phy_data,u32 chip_id)1755 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1756 u16 phy_data, u32 chip_id)
1757 {
1758 u16 i;
1759 unsigned long ioaddr;
1760
1761 if (chip_id == PCI_DM9132_ID) {
1762 ioaddr = iobase + 0x80 + offset * 4;
1763 outw(phy_data, ioaddr);
1764 } else {
1765 /* DM9102/DM9102A Chip */
1766 ioaddr = iobase + DCR9;
1767
1768 /* Send 33 synchronization clock to Phy controller */
1769 for (i = 0; i < 35; i++)
1770 phy_write_1bit(ioaddr, PHY_DATA_1);
1771
1772 /* Send start command(01) to Phy */
1773 phy_write_1bit(ioaddr, PHY_DATA_0);
1774 phy_write_1bit(ioaddr, PHY_DATA_1);
1775
1776 /* Send write command(01) to Phy */
1777 phy_write_1bit(ioaddr, PHY_DATA_0);
1778 phy_write_1bit(ioaddr, PHY_DATA_1);
1779
1780 /* Send Phy address */
1781 for (i = 0x10; i > 0; i = i >> 1)
1782 phy_write_1bit(ioaddr,
1783 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1784
1785 /* Send register address */
1786 for (i = 0x10; i > 0; i = i >> 1)
1787 phy_write_1bit(ioaddr,
1788 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1789
1790 /* written trasnition */
1791 phy_write_1bit(ioaddr, PHY_DATA_1);
1792 phy_write_1bit(ioaddr, PHY_DATA_0);
1793
1794 /* Write a word data to PHY controller */
1795 for ( i = 0x8000; i > 0; i >>= 1)
1796 phy_write_1bit(ioaddr,
1797 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1798 }
1799 }
1800
1801
1802 /*
1803 * Read a word data from phy register
1804 */
1805
phy_read(unsigned long iobase,u8 phy_addr,u8 offset,u32 chip_id)1806 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1807 {
1808 int i;
1809 u16 phy_data;
1810 unsigned long ioaddr;
1811
1812 if (chip_id == PCI_DM9132_ID) {
1813 /* DM9132 Chip */
1814 ioaddr = iobase + 0x80 + offset * 4;
1815 phy_data = inw(ioaddr);
1816 } else {
1817 /* DM9102/DM9102A Chip */
1818 ioaddr = iobase + DCR9;
1819
1820 /* Send 33 synchronization clock to Phy controller */
1821 for (i = 0; i < 35; i++)
1822 phy_write_1bit(ioaddr, PHY_DATA_1);
1823
1824 /* Send start command(01) to Phy */
1825 phy_write_1bit(ioaddr, PHY_DATA_0);
1826 phy_write_1bit(ioaddr, PHY_DATA_1);
1827
1828 /* Send read command(10) to Phy */
1829 phy_write_1bit(ioaddr, PHY_DATA_1);
1830 phy_write_1bit(ioaddr, PHY_DATA_0);
1831
1832 /* Send Phy address */
1833 for (i = 0x10; i > 0; i = i >> 1)
1834 phy_write_1bit(ioaddr,
1835 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1836
1837 /* Send register address */
1838 for (i = 0x10; i > 0; i = i >> 1)
1839 phy_write_1bit(ioaddr,
1840 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1841
1842 /* Skip transition state */
1843 phy_read_1bit(ioaddr);
1844
1845 /* read 16bit data */
1846 for (phy_data = 0, i = 0; i < 16; i++) {
1847 phy_data <<= 1;
1848 phy_data |= phy_read_1bit(ioaddr);
1849 }
1850 }
1851
1852 return phy_data;
1853 }
1854
1855
1856 /*
1857 * Write one bit data to Phy Controller
1858 */
1859
phy_write_1bit(unsigned long ioaddr,u32 phy_data)1860 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1861 {
1862 outl(phy_data, ioaddr); /* MII Clock Low */
1863 udelay(1);
1864 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1865 udelay(1);
1866 outl(phy_data, ioaddr); /* MII Clock Low */
1867 udelay(1);
1868 }
1869
1870
1871 /*
1872 * Read one bit phy data from PHY controller
1873 */
1874
phy_read_1bit(unsigned long ioaddr)1875 static u16 phy_read_1bit(unsigned long ioaddr)
1876 {
1877 u16 phy_data;
1878
1879 outl(0x50000, ioaddr);
1880 udelay(1);
1881 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1882 outl(0x40000, ioaddr);
1883 udelay(1);
1884
1885 return phy_data;
1886 }
1887
1888
1889 /*
1890 * Parser SROM and media mode
1891 */
1892
dmfe_parse_srom(struct dmfe_board_info * db)1893 static void dmfe_parse_srom(struct dmfe_board_info * db)
1894 {
1895 char * srom = db->srom;
1896 int dmfe_mode, tmp_reg;
1897
1898 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1899
1900 /* Init CR15 */
1901 db->cr15_data = CR15_DEFAULT;
1902
1903 /* Check SROM Version */
1904 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1905 /* SROM V4.01 */
1906 /* Get NIC support media mode */
1907 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1908 db->PHY_reg4 = 0;
1909 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1910 switch( db->NIC_capability & tmp_reg ) {
1911 case 0x1: db->PHY_reg4 |= 0x0020; break;
1912 case 0x2: db->PHY_reg4 |= 0x0040; break;
1913 case 0x4: db->PHY_reg4 |= 0x0080; break;
1914 case 0x8: db->PHY_reg4 |= 0x0100; break;
1915 }
1916 }
1917
1918 /* Media Mode Force or not check */
1919 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1920 le32_to_cpup((__le32 *) (srom + 36)));
1921 switch(dmfe_mode) {
1922 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1923 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1924 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1925 case 0x100:
1926 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1927 }
1928
1929 /* Special Function setting */
1930 /* VLAN function */
1931 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1932 db->cr15_data |= 0x40;
1933
1934 /* Flow Control */
1935 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1936 db->cr15_data |= 0x400;
1937
1938 /* TX pause packet */
1939 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1940 db->cr15_data |= 0x9800;
1941 }
1942
1943 /* Parse HPNA parameter */
1944 db->HPNA_command = 1;
1945
1946 /* Accept remote command or not */
1947 if (HPNA_rx_cmd == 0)
1948 db->HPNA_command |= 0x8000;
1949
1950 /* Issue remote command & operation mode */
1951 if (HPNA_tx_cmd == 1)
1952 switch(HPNA_mode) { /* Issue Remote Command */
1953 case 0: db->HPNA_command |= 0x0904; break;
1954 case 1: db->HPNA_command |= 0x0a00; break;
1955 case 2: db->HPNA_command |= 0x0506; break;
1956 case 3: db->HPNA_command |= 0x0602; break;
1957 }
1958 else
1959 switch(HPNA_mode) { /* Don't Issue */
1960 case 0: db->HPNA_command |= 0x0004; break;
1961 case 1: db->HPNA_command |= 0x0000; break;
1962 case 2: db->HPNA_command |= 0x0006; break;
1963 case 3: db->HPNA_command |= 0x0002; break;
1964 }
1965
1966 /* Check DM9801 or DM9802 present or not */
1967 db->HPNA_present = 0;
1968 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1969 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1970 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1971 /* DM9801 or DM9802 present */
1972 db->HPNA_timer = 8;
1973 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1974 /* DM9801 HomeRun */
1975 db->HPNA_present = 1;
1976 dmfe_program_DM9801(db, tmp_reg);
1977 } else {
1978 /* DM9802 LongRun */
1979 db->HPNA_present = 2;
1980 dmfe_program_DM9802(db);
1981 }
1982 }
1983
1984 }
1985
1986
1987 /*
1988 * Init HomeRun DM9801
1989 */
1990
dmfe_program_DM9801(struct dmfe_board_info * db,int HPNA_rev)1991 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1992 {
1993 uint reg17, reg25;
1994
1995 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1996 switch(HPNA_rev) {
1997 case 0xb900: /* DM9801 E3 */
1998 db->HPNA_command |= 0x1000;
1999 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2000 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2001 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2002 break;
2003 case 0xb901: /* DM9801 E4 */
2004 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2005 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2006 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2007 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2008 break;
2009 case 0xb902: /* DM9801 E5 */
2010 case 0xb903: /* DM9801 E6 */
2011 default:
2012 db->HPNA_command |= 0x1000;
2013 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2014 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2015 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2016 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2017 break;
2018 }
2019 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2020 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2021 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2022 }
2023
2024
2025 /*
2026 * Init HomeRun DM9802
2027 */
2028
dmfe_program_DM9802(struct dmfe_board_info * db)2029 static void dmfe_program_DM9802(struct dmfe_board_info * db)
2030 {
2031 uint phy_reg;
2032
2033 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2034 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2035 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2036 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2037 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2038 }
2039
2040
2041 /*
2042 * Check remote HPNA power and speed status. If not correct,
2043 * issue command again.
2044 */
2045
dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)2046 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2047 {
2048 uint phy_reg;
2049
2050 /* Got remote device status */
2051 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2052 switch(phy_reg) {
2053 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2054 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2055 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2056 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2057 }
2058
2059 /* Check remote device status match our setting ot not */
2060 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
2061 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2062 db->chip_id);
2063 db->HPNA_timer=8;
2064 } else
2065 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2066 }
2067
2068
2069
2070 static struct pci_device_id dmfe_pci_tbl[] = {
2071 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2072 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2073 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2074 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2075 { 0, }
2076 };
2077 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2078
2079
2080 #ifdef CONFIG_PM
dmfe_suspend(struct pci_dev * pci_dev,pm_message_t state)2081 static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2082 {
2083 struct net_device *dev = pci_get_drvdata(pci_dev);
2084 struct dmfe_board_info *db = netdev_priv(dev);
2085 u32 tmp;
2086
2087 /* Disable upper layer interface */
2088 netif_device_detach(dev);
2089
2090 /* Disable Tx/Rx */
2091 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2092 update_cr6(db->cr6_data, dev->base_addr);
2093
2094 /* Disable Interrupt */
2095 outl(0, dev->base_addr + DCR7);
2096 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2097
2098 /* Fre RX buffers */
2099 dmfe_free_rxbuffer(db);
2100
2101 /* Enable WOL */
2102 pci_read_config_dword(pci_dev, 0x40, &tmp);
2103 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2104
2105 if (db->wol_mode & WAKE_PHY)
2106 tmp |= DMFE_WOL_LINKCHANGE;
2107 if (db->wol_mode & WAKE_MAGIC)
2108 tmp |= DMFE_WOL_MAGICPACKET;
2109
2110 pci_write_config_dword(pci_dev, 0x40, tmp);
2111
2112 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2113 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2114
2115 /* Power down device*/
2116 pci_save_state(pci_dev);
2117 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
2118
2119 return 0;
2120 }
2121
dmfe_resume(struct pci_dev * pci_dev)2122 static int dmfe_resume(struct pci_dev *pci_dev)
2123 {
2124 struct net_device *dev = pci_get_drvdata(pci_dev);
2125 u32 tmp;
2126
2127 pci_set_power_state(pci_dev, PCI_D0);
2128 pci_restore_state(pci_dev);
2129
2130 /* Re-initilize DM910X board */
2131 dmfe_init_dm910x(dev);
2132
2133 /* Disable WOL */
2134 pci_read_config_dword(pci_dev, 0x40, &tmp);
2135
2136 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2137 pci_write_config_dword(pci_dev, 0x40, tmp);
2138
2139 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2140 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2141
2142 /* Restart upper layer interface */
2143 netif_device_attach(dev);
2144
2145 return 0;
2146 }
2147 #else
2148 #define dmfe_suspend NULL
2149 #define dmfe_resume NULL
2150 #endif
2151
2152 static struct pci_driver dmfe_driver = {
2153 .name = "dmfe",
2154 .id_table = dmfe_pci_tbl,
2155 .probe = dmfe_init_one,
2156 .remove = __devexit_p(dmfe_remove_one),
2157 .suspend = dmfe_suspend,
2158 .resume = dmfe_resume
2159 };
2160
2161 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2162 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2163 MODULE_LICENSE("GPL");
2164 MODULE_VERSION(DRV_VERSION);
2165
2166 module_param(debug, int, 0);
2167 module_param(mode, byte, 0);
2168 module_param(cr6set, int, 0);
2169 module_param(chkmode, byte, 0);
2170 module_param(HPNA_mode, byte, 0);
2171 module_param(HPNA_rx_cmd, byte, 0);
2172 module_param(HPNA_tx_cmd, byte, 0);
2173 module_param(HPNA_NoiseFloor, byte, 0);
2174 module_param(SF_mode, byte, 0);
2175 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2176 MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2177 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2178
2179 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2180 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2181
2182 /* Description:
2183 * when user used insmod to add module, system invoked init_module()
2184 * to initilize and register.
2185 */
2186
dmfe_init_module(void)2187 static int __init dmfe_init_module(void)
2188 {
2189 int rc;
2190
2191 printk(version);
2192 printed_version = 1;
2193
2194 DMFE_DBUG(0, "init_module() ", debug);
2195
2196 if (debug)
2197 dmfe_debug = debug; /* set debug flag */
2198 if (cr6set)
2199 dmfe_cr6_user_set = cr6set;
2200
2201 switch(mode) {
2202 case DMFE_10MHF:
2203 case DMFE_100MHF:
2204 case DMFE_10MFD:
2205 case DMFE_100MFD:
2206 case DMFE_1M_HPNA:
2207 dmfe_media_mode = mode;
2208 break;
2209 default:dmfe_media_mode = DMFE_AUTO;
2210 break;
2211 }
2212
2213 if (HPNA_mode > 4)
2214 HPNA_mode = 0; /* Default: LP/HS */
2215 if (HPNA_rx_cmd > 1)
2216 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2217 if (HPNA_tx_cmd > 1)
2218 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2219 if (HPNA_NoiseFloor > 15)
2220 HPNA_NoiseFloor = 0;
2221
2222 rc = pci_register_driver(&dmfe_driver);
2223 if (rc < 0)
2224 return rc;
2225
2226 return 0;
2227 }
2228
2229
2230 /*
2231 * Description:
2232 * when user used rmmod to delete module, system invoked clean_module()
2233 * to un-register all registered services.
2234 */
2235
dmfe_cleanup_module(void)2236 static void __exit dmfe_cleanup_module(void)
2237 {
2238 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2239 pci_unregister_driver(&dmfe_driver);
2240 }
2241
2242 module_init(dmfe_init_module);
2243 module_exit(dmfe_cleanup_module);
2244