1 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2 /*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28 [link no longer provides useful info -jgarzik]
29
30 */
31
32 #define DRV_NAME "via-rhine"
33 #define DRV_VERSION "1.4.3"
34 #define DRV_RELDATE "2007-03-06"
35
36
37 /* A few user-configurable values.
38 These may be modified when a driver module is loaded. */
39
40 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
41 static int max_interrupt_work = 20;
42
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1518 effectively disables this feature. */
45 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
46 || defined(CONFIG_SPARC) || defined(__ia64__) \
47 || defined(__sh__) || defined(__mips__)
48 static int rx_copybreak = 1518;
49 #else
50 static int rx_copybreak;
51 #endif
52
53 /* Work-around for broken BIOSes: they are unable to get the chip back out of
54 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
55 static int avoid_D3;
56
57 /*
58 * In case you are looking for 'options[]' or 'full_duplex[]', they
59 * are gone. Use ethtool(8) instead.
60 */
61
62 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
63 The Rhine has a 64 element 8390-like hash table. */
64 static const int multicast_filter_limit = 32;
65
66
67 /* Operational parameters that are set at compile time. */
68
69 /* Keep the ring sizes a power of two for compile efficiency.
70 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
71 Making the Tx ring too large decreases the effectiveness of channel
72 bonding and packet priority.
73 There are no ill effects from too-large receive rings. */
74 #define TX_RING_SIZE 16
75 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
76 #define RX_RING_SIZE 64
77
78 /* Operational parameters that usually are not changed. */
79
80 /* Time in jiffies before concluding the transmitter is hung. */
81 #define TX_TIMEOUT (2*HZ)
82
83 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85 #include <linux/module.h>
86 #include <linux/moduleparam.h>
87 #include <linux/kernel.h>
88 #include <linux/string.h>
89 #include <linux/timer.h>
90 #include <linux/errno.h>
91 #include <linux/ioport.h>
92 #include <linux/slab.h>
93 #include <linux/interrupt.h>
94 #include <linux/pci.h>
95 #include <linux/dma-mapping.h>
96 #include <linux/netdevice.h>
97 #include <linux/etherdevice.h>
98 #include <linux/skbuff.h>
99 #include <linux/init.h>
100 #include <linux/delay.h>
101 #include <linux/mii.h>
102 #include <linux/ethtool.h>
103 #include <linux/crc32.h>
104 #include <linux/bitops.h>
105 #include <asm/processor.h> /* Processor type for cache alignment. */
106 #include <asm/io.h>
107 #include <asm/irq.h>
108 #include <asm/uaccess.h>
109 #include <linux/dmi.h>
110
111 /* These identify the driver base version and may not be removed. */
112 static char version[] __devinitdata =
113 KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
114
115 /* This driver was written to use PCI memory space. Some early versions
116 of the Rhine may only work correctly with I/O space accesses. */
117 #ifdef CONFIG_VIA_RHINE_MMIO
118 #define USE_MMIO
119 #else
120 #endif
121
122 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
123 MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
124 MODULE_LICENSE("GPL");
125
126 module_param(max_interrupt_work, int, 0);
127 module_param(debug, int, 0);
128 module_param(rx_copybreak, int, 0);
129 module_param(avoid_D3, bool, 0);
130 MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
131 MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
132 MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
133 MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
134
135 /*
136 Theory of Operation
137
138 I. Board Compatibility
139
140 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
141 controller.
142
143 II. Board-specific settings
144
145 Boards with this chip are functional only in a bus-master PCI slot.
146
147 Many operational settings are loaded from the EEPROM to the Config word at
148 offset 0x78. For most of these settings, this driver assumes that they are
149 correct.
150 If this driver is compiled to use PCI memory space operations the EEPROM
151 must be configured to enable memory ops.
152
153 III. Driver operation
154
155 IIIa. Ring buffers
156
157 This driver uses two statically allocated fixed-size descriptor lists
158 formed into rings by a branch from the final descriptor to the beginning of
159 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
160
161 IIIb/c. Transmit/Receive Structure
162
163 This driver attempts to use a zero-copy receive and transmit scheme.
164
165 Alas, all data buffers are required to start on a 32 bit boundary, so
166 the driver must often copy transmit packets into bounce buffers.
167
168 The driver allocates full frame size skbuffs for the Rx ring buffers at
169 open() time and passes the skb->data field to the chip as receive data
170 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
171 a fresh skbuff is allocated and the frame is copied to the new skbuff.
172 When the incoming frame is larger, the skbuff is passed directly up the
173 protocol stack. Buffers consumed this way are replaced by newly allocated
174 skbuffs in the last phase of rhine_rx().
175
176 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
177 using a full-sized skbuff for small frames vs. the copying costs of larger
178 frames. New boards are typically used in generously configured machines
179 and the underfilled buffers have negligible impact compared to the benefit of
180 a single allocation size, so the default value of zero results in never
181 copying packets. When copying is done, the cost is usually mitigated by using
182 a combined copy/checksum routine. Copying also preloads the cache, which is
183 most useful with small frames.
184
185 Since the VIA chips are only able to transfer data to buffers on 32 bit
186 boundaries, the IP header at offset 14 in an ethernet frame isn't
187 longword aligned for further processing. Copying these unaligned buffers
188 has the beneficial effect of 16-byte aligning the IP header.
189
190 IIId. Synchronization
191
192 The driver runs as two independent, single-threaded flows of control. One
193 is the send-packet routine, which enforces single-threaded use by the
194 netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
195 which is single threaded by the hardware and interrupt handling software.
196
197 The send packet thread has partial control over the Tx ring. It locks the
198 netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
199 the ring is not available it stops the transmit queue by
200 calling netif_stop_queue.
201
202 The interrupt handler has exclusive control over the Rx ring and records stats
203 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
204 empty by incrementing the dirty_tx mark. If at least half of the entries in
205 the Rx ring are available the transmit queue is woken up if it was stopped.
206
207 IV. Notes
208
209 IVb. References
210
211 Preliminary VT86C100A manual from http://www.via.com.tw/
212 http://www.scyld.com/expert/100mbps.html
213 http://www.scyld.com/expert/NWay.html
214 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
215 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
216
217
218 IVc. Errata
219
220 The VT86C100A manual is not reliable information.
221 The 3043 chip does not handle unaligned transmit or receive buffers, resulting
222 in significant performance degradation for bounce buffer copies on transmit
223 and unaligned IP headers on receive.
224 The chip does not pad to minimum transmit length.
225
226 */
227
228
229 /* This table drives the PCI probe routines. It's mostly boilerplate in all
230 of the drivers, and will likely be provided by some future kernel.
231 Note the matching code -- the first table entry matchs all 56** cards but
232 second only the 1234 card.
233 */
234
235 enum rhine_revs {
236 VT86C100A = 0x00,
237 VTunknown0 = 0x20,
238 VT6102 = 0x40,
239 VT8231 = 0x50, /* Integrated MAC */
240 VT8233 = 0x60, /* Integrated MAC */
241 VT8235 = 0x74, /* Integrated MAC */
242 VT8237 = 0x78, /* Integrated MAC */
243 VTunknown1 = 0x7C,
244 VT6105 = 0x80,
245 VT6105_B0 = 0x83,
246 VT6105L = 0x8A,
247 VT6107 = 0x8C,
248 VTunknown2 = 0x8E,
249 VT6105M = 0x90, /* Management adapter */
250 };
251
252 enum rhine_quirks {
253 rqWOL = 0x0001, /* Wake-On-LAN support */
254 rqForceReset = 0x0002,
255 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
256 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
257 rqRhineI = 0x0100, /* See comment below */
258 };
259 /*
260 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
261 * MMIO as well as for the collision counter and the Tx FIFO underflow
262 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
263 */
264
265 /* Beware of PCI posted writes */
266 #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
267
268 static const struct pci_device_id rhine_pci_tbl[] = {
269 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
270 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
271 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
272 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
273 { } /* terminate list */
274 };
275 MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
276
277
278 /* Offsets to the device registers. */
279 enum register_offsets {
280 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
281 ChipCmd1=0x09,
282 IntrStatus=0x0C, IntrEnable=0x0E,
283 MulticastFilter0=0x10, MulticastFilter1=0x14,
284 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
285 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
286 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
287 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
288 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
289 StickyHW=0x83, IntrStatus2=0x84,
290 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
291 WOLcrClr1=0xA6, WOLcgClr=0xA7,
292 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
293 };
294
295 /* Bits in ConfigD */
296 enum backoff_bits {
297 BackOptional=0x01, BackModify=0x02,
298 BackCaptureEffect=0x04, BackRandom=0x08
299 };
300
301 #ifdef USE_MMIO
302 /* Registers we check that mmio and reg are the same. */
303 static const int mmio_verify_registers[] = {
304 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
305 0
306 };
307 #endif
308
309 /* Bits in the interrupt status/mask registers. */
310 enum intr_status_bits {
311 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
312 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
313 IntrPCIErr=0x0040,
314 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
315 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
316 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
317 IntrRxWakeUp=0x8000,
318 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
319 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
320 IntrTxErrSummary=0x082218,
321 };
322
323 /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
324 enum wol_bits {
325 WOLucast = 0x10,
326 WOLmagic = 0x20,
327 WOLbmcast = 0x30,
328 WOLlnkon = 0x40,
329 WOLlnkoff = 0x80,
330 };
331
332 /* The Rx and Tx buffer descriptors. */
333 struct rx_desc {
334 __le32 rx_status;
335 __le32 desc_length; /* Chain flag, Buffer/frame length */
336 __le32 addr;
337 __le32 next_desc;
338 };
339 struct tx_desc {
340 __le32 tx_status;
341 __le32 desc_length; /* Chain flag, Tx Config, Frame length */
342 __le32 addr;
343 __le32 next_desc;
344 };
345
346 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
347 #define TXDESC 0x00e08000
348
349 enum rx_status_bits {
350 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
351 };
352
353 /* Bits in *_desc.*_status */
354 enum desc_status_bits {
355 DescOwn=0x80000000
356 };
357
358 /* Bits in ChipCmd. */
359 enum chip_cmd_bits {
360 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
361 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
362 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
363 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
364 };
365
366 struct rhine_private {
367 /* Descriptor rings */
368 struct rx_desc *rx_ring;
369 struct tx_desc *tx_ring;
370 dma_addr_t rx_ring_dma;
371 dma_addr_t tx_ring_dma;
372
373 /* The addresses of receive-in-place skbuffs. */
374 struct sk_buff *rx_skbuff[RX_RING_SIZE];
375 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
376
377 /* The saved address of a sent-in-place packet/buffer, for later free(). */
378 struct sk_buff *tx_skbuff[TX_RING_SIZE];
379 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
380
381 /* Tx bounce buffers (Rhine-I only) */
382 unsigned char *tx_buf[TX_RING_SIZE];
383 unsigned char *tx_bufs;
384 dma_addr_t tx_bufs_dma;
385
386 struct pci_dev *pdev;
387 long pioaddr;
388 struct net_device *dev;
389 struct napi_struct napi;
390 struct net_device_stats stats;
391 spinlock_t lock;
392
393 /* Frequently used values: keep some adjacent for cache effect. */
394 u32 quirks;
395 struct rx_desc *rx_head_desc;
396 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
397 unsigned int cur_tx, dirty_tx;
398 unsigned int rx_buf_sz; /* Based on MTU+slack. */
399 u8 wolopts;
400
401 u8 tx_thresh, rx_thresh;
402
403 struct mii_if_info mii_if;
404 void __iomem *base;
405 };
406
407 static int mdio_read(struct net_device *dev, int phy_id, int location);
408 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
409 static int rhine_open(struct net_device *dev);
410 static void rhine_tx_timeout(struct net_device *dev);
411 static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
412 static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
413 static void rhine_tx(struct net_device *dev);
414 static int rhine_rx(struct net_device *dev, int limit);
415 static void rhine_error(struct net_device *dev, int intr_status);
416 static void rhine_set_rx_mode(struct net_device *dev);
417 static struct net_device_stats *rhine_get_stats(struct net_device *dev);
418 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
419 static const struct ethtool_ops netdev_ethtool_ops;
420 static int rhine_close(struct net_device *dev);
421 static void rhine_shutdown (struct pci_dev *pdev);
422
423 #define RHINE_WAIT_FOR(condition) do { \
424 int i=1024; \
425 while (!(condition) && --i) \
426 ; \
427 if (debug > 1 && i < 512) \
428 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
429 DRV_NAME, 1024-i, __func__, __LINE__); \
430 } while(0)
431
get_intr_status(struct net_device * dev)432 static inline u32 get_intr_status(struct net_device *dev)
433 {
434 struct rhine_private *rp = netdev_priv(dev);
435 void __iomem *ioaddr = rp->base;
436 u32 intr_status;
437
438 intr_status = ioread16(ioaddr + IntrStatus);
439 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
440 if (rp->quirks & rqStatusWBRace)
441 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
442 return intr_status;
443 }
444
445 /*
446 * Get power related registers into sane state.
447 * Notify user about past WOL event.
448 */
rhine_power_init(struct net_device * dev)449 static void rhine_power_init(struct net_device *dev)
450 {
451 struct rhine_private *rp = netdev_priv(dev);
452 void __iomem *ioaddr = rp->base;
453 u16 wolstat;
454
455 if (rp->quirks & rqWOL) {
456 /* Make sure chip is in power state D0 */
457 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
458
459 /* Disable "force PME-enable" */
460 iowrite8(0x80, ioaddr + WOLcgClr);
461
462 /* Clear power-event config bits (WOL) */
463 iowrite8(0xFF, ioaddr + WOLcrClr);
464 /* More recent cards can manage two additional patterns */
465 if (rp->quirks & rq6patterns)
466 iowrite8(0x03, ioaddr + WOLcrClr1);
467
468 /* Save power-event status bits */
469 wolstat = ioread8(ioaddr + PwrcsrSet);
470 if (rp->quirks & rq6patterns)
471 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
472
473 /* Clear power-event status bits */
474 iowrite8(0xFF, ioaddr + PwrcsrClr);
475 if (rp->quirks & rq6patterns)
476 iowrite8(0x03, ioaddr + PwrcsrClr1);
477
478 if (wolstat) {
479 char *reason;
480 switch (wolstat) {
481 case WOLmagic:
482 reason = "Magic packet";
483 break;
484 case WOLlnkon:
485 reason = "Link went up";
486 break;
487 case WOLlnkoff:
488 reason = "Link went down";
489 break;
490 case WOLucast:
491 reason = "Unicast packet";
492 break;
493 case WOLbmcast:
494 reason = "Multicast/broadcast packet";
495 break;
496 default:
497 reason = "Unknown";
498 }
499 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
500 DRV_NAME, reason);
501 }
502 }
503 }
504
rhine_chip_reset(struct net_device * dev)505 static void rhine_chip_reset(struct net_device *dev)
506 {
507 struct rhine_private *rp = netdev_priv(dev);
508 void __iomem *ioaddr = rp->base;
509
510 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
511 IOSYNC;
512
513 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
514 printk(KERN_INFO "%s: Reset not complete yet. "
515 "Trying harder.\n", DRV_NAME);
516
517 /* Force reset */
518 if (rp->quirks & rqForceReset)
519 iowrite8(0x40, ioaddr + MiscCmd);
520
521 /* Reset can take somewhat longer (rare) */
522 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
523 }
524
525 if (debug > 1)
526 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
527 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
528 "failed" : "succeeded");
529 }
530
531 #ifdef USE_MMIO
enable_mmio(long pioaddr,u32 quirks)532 static void enable_mmio(long pioaddr, u32 quirks)
533 {
534 int n;
535 if (quirks & rqRhineI) {
536 /* More recent docs say that this bit is reserved ... */
537 n = inb(pioaddr + ConfigA) | 0x20;
538 outb(n, pioaddr + ConfigA);
539 } else {
540 n = inb(pioaddr + ConfigD) | 0x80;
541 outb(n, pioaddr + ConfigD);
542 }
543 }
544 #endif
545
546 /*
547 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
548 * (plus 0x6C for Rhine-I/II)
549 */
rhine_reload_eeprom(long pioaddr,struct net_device * dev)550 static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
551 {
552 struct rhine_private *rp = netdev_priv(dev);
553 void __iomem *ioaddr = rp->base;
554
555 outb(0x20, pioaddr + MACRegEEcsr);
556 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
557
558 #ifdef USE_MMIO
559 /*
560 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
561 * MMIO. If reloading EEPROM was done first this could be avoided, but
562 * it is not known if that still works with the "win98-reboot" problem.
563 */
564 enable_mmio(pioaddr, rp->quirks);
565 #endif
566
567 /* Turn off EEPROM-controlled wake-up (magic packet) */
568 if (rp->quirks & rqWOL)
569 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
570
571 }
572
573 #ifdef CONFIG_NET_POLL_CONTROLLER
rhine_poll(struct net_device * dev)574 static void rhine_poll(struct net_device *dev)
575 {
576 disable_irq(dev->irq);
577 rhine_interrupt(dev->irq, (void *)dev);
578 enable_irq(dev->irq);
579 }
580 #endif
581
rhine_napipoll(struct napi_struct * napi,int budget)582 static int rhine_napipoll(struct napi_struct *napi, int budget)
583 {
584 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
585 struct net_device *dev = rp->dev;
586 void __iomem *ioaddr = rp->base;
587 int work_done;
588
589 work_done = rhine_rx(dev, budget);
590
591 if (work_done < budget) {
592 netif_rx_complete(napi);
593
594 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
595 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
596 IntrTxDone | IntrTxError | IntrTxUnderrun |
597 IntrPCIErr | IntrStatsMax | IntrLinkChange,
598 ioaddr + IntrEnable);
599 }
600 return work_done;
601 }
602
rhine_hw_init(struct net_device * dev,long pioaddr)603 static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
604 {
605 struct rhine_private *rp = netdev_priv(dev);
606
607 /* Reset the chip to erase previous misconfiguration. */
608 rhine_chip_reset(dev);
609
610 /* Rhine-I needs extra time to recuperate before EEPROM reload */
611 if (rp->quirks & rqRhineI)
612 msleep(5);
613
614 /* Reload EEPROM controlled bytes cleared by soft reset */
615 rhine_reload_eeprom(pioaddr, dev);
616 }
617
618 static const struct net_device_ops rhine_netdev_ops = {
619 .ndo_open = rhine_open,
620 .ndo_stop = rhine_close,
621 .ndo_start_xmit = rhine_start_tx,
622 .ndo_get_stats = rhine_get_stats,
623 .ndo_set_multicast_list = rhine_set_rx_mode,
624 .ndo_validate_addr = eth_validate_addr,
625 .ndo_set_mac_address = eth_mac_addr,
626 .ndo_do_ioctl = netdev_ioctl,
627 .ndo_tx_timeout = rhine_tx_timeout,
628 #ifdef CONFIG_NET_POLL_CONTROLLER
629 .ndo_poll_controller = rhine_poll,
630 #endif
631 };
632
rhine_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)633 static int __devinit rhine_init_one(struct pci_dev *pdev,
634 const struct pci_device_id *ent)
635 {
636 struct net_device *dev;
637 struct rhine_private *rp;
638 int i, rc;
639 u32 quirks;
640 long pioaddr;
641 long memaddr;
642 void __iomem *ioaddr;
643 int io_size, phy_id;
644 const char *name;
645 #ifdef USE_MMIO
646 int bar = 1;
647 #else
648 int bar = 0;
649 #endif
650
651 /* when built into the kernel, we only print version if device is found */
652 #ifndef MODULE
653 static int printed_version;
654 if (!printed_version++)
655 printk(version);
656 #endif
657
658 io_size = 256;
659 phy_id = 0;
660 quirks = 0;
661 name = "Rhine";
662 if (pdev->revision < VTunknown0) {
663 quirks = rqRhineI;
664 io_size = 128;
665 }
666 else if (pdev->revision >= VT6102) {
667 quirks = rqWOL | rqForceReset;
668 if (pdev->revision < VT6105) {
669 name = "Rhine II";
670 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
671 }
672 else {
673 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
674 if (pdev->revision >= VT6105_B0)
675 quirks |= rq6patterns;
676 if (pdev->revision < VT6105M)
677 name = "Rhine III";
678 else
679 name = "Rhine III (Management Adapter)";
680 }
681 }
682
683 rc = pci_enable_device(pdev);
684 if (rc)
685 goto err_out;
686
687 /* this should always be supported */
688 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
689 if (rc) {
690 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
691 "the card!?\n");
692 goto err_out;
693 }
694
695 /* sanity check */
696 if ((pci_resource_len(pdev, 0) < io_size) ||
697 (pci_resource_len(pdev, 1) < io_size)) {
698 rc = -EIO;
699 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
700 goto err_out;
701 }
702
703 pioaddr = pci_resource_start(pdev, 0);
704 memaddr = pci_resource_start(pdev, 1);
705
706 pci_set_master(pdev);
707
708 dev = alloc_etherdev(sizeof(struct rhine_private));
709 if (!dev) {
710 rc = -ENOMEM;
711 printk(KERN_ERR "alloc_etherdev failed\n");
712 goto err_out;
713 }
714 SET_NETDEV_DEV(dev, &pdev->dev);
715
716 rp = netdev_priv(dev);
717 rp->dev = dev;
718 rp->quirks = quirks;
719 rp->pioaddr = pioaddr;
720 rp->pdev = pdev;
721
722 rc = pci_request_regions(pdev, DRV_NAME);
723 if (rc)
724 goto err_out_free_netdev;
725
726 ioaddr = pci_iomap(pdev, bar, io_size);
727 if (!ioaddr) {
728 rc = -EIO;
729 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
730 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
731 goto err_out_free_res;
732 }
733
734 #ifdef USE_MMIO
735 enable_mmio(pioaddr, quirks);
736
737 /* Check that selected MMIO registers match the PIO ones */
738 i = 0;
739 while (mmio_verify_registers[i]) {
740 int reg = mmio_verify_registers[i++];
741 unsigned char a = inb(pioaddr+reg);
742 unsigned char b = readb(ioaddr+reg);
743 if (a != b) {
744 rc = -EIO;
745 printk(KERN_ERR "MMIO do not match PIO [%02x] "
746 "(%02x != %02x)\n", reg, a, b);
747 goto err_out_unmap;
748 }
749 }
750 #endif /* USE_MMIO */
751
752 dev->base_addr = (unsigned long)ioaddr;
753 rp->base = ioaddr;
754
755 /* Get chip registers into a sane state */
756 rhine_power_init(dev);
757 rhine_hw_init(dev, pioaddr);
758
759 for (i = 0; i < 6; i++)
760 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
761 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
762
763 if (!is_valid_ether_addr(dev->perm_addr)) {
764 rc = -EIO;
765 printk(KERN_ERR "Invalid MAC address\n");
766 goto err_out_unmap;
767 }
768
769 /* For Rhine-I/II, phy_id is loaded from EEPROM */
770 if (!phy_id)
771 phy_id = ioread8(ioaddr + 0x6C);
772
773 dev->irq = pdev->irq;
774
775 spin_lock_init(&rp->lock);
776 rp->mii_if.dev = dev;
777 rp->mii_if.mdio_read = mdio_read;
778 rp->mii_if.mdio_write = mdio_write;
779 rp->mii_if.phy_id_mask = 0x1f;
780 rp->mii_if.reg_num_mask = 0x1f;
781
782 /* The chip-specific entries in the device structure. */
783 dev->netdev_ops = &rhine_netdev_ops;
784 dev->ethtool_ops = &netdev_ethtool_ops,
785 dev->watchdog_timeo = TX_TIMEOUT;
786
787 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
788
789 if (rp->quirks & rqRhineI)
790 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
791
792 /* dev->name not defined before register_netdev()! */
793 rc = register_netdev(dev);
794 if (rc)
795 goto err_out_unmap;
796
797 printk(KERN_INFO "%s: VIA %s at 0x%lx, %pM, IRQ %d.\n",
798 dev->name, name,
799 #ifdef USE_MMIO
800 memaddr,
801 #else
802 (long)ioaddr,
803 #endif
804 dev->dev_addr, pdev->irq);
805
806 pci_set_drvdata(pdev, dev);
807
808 {
809 u16 mii_cmd;
810 int mii_status = mdio_read(dev, phy_id, 1);
811 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
812 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
813 if (mii_status != 0xffff && mii_status != 0x0000) {
814 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
815 printk(KERN_INFO "%s: MII PHY found at address "
816 "%d, status 0x%4.4x advertising %4.4x "
817 "Link %4.4x.\n", dev->name, phy_id,
818 mii_status, rp->mii_if.advertising,
819 mdio_read(dev, phy_id, 5));
820
821 /* set IFF_RUNNING */
822 if (mii_status & BMSR_LSTATUS)
823 netif_carrier_on(dev);
824 else
825 netif_carrier_off(dev);
826
827 }
828 }
829 rp->mii_if.phy_id = phy_id;
830 if (debug > 1 && avoid_D3)
831 printk(KERN_INFO "%s: No D3 power state at shutdown.\n",
832 dev->name);
833
834 return 0;
835
836 err_out_unmap:
837 pci_iounmap(pdev, ioaddr);
838 err_out_free_res:
839 pci_release_regions(pdev);
840 err_out_free_netdev:
841 free_netdev(dev);
842 err_out:
843 return rc;
844 }
845
alloc_ring(struct net_device * dev)846 static int alloc_ring(struct net_device* dev)
847 {
848 struct rhine_private *rp = netdev_priv(dev);
849 void *ring;
850 dma_addr_t ring_dma;
851
852 ring = pci_alloc_consistent(rp->pdev,
853 RX_RING_SIZE * sizeof(struct rx_desc) +
854 TX_RING_SIZE * sizeof(struct tx_desc),
855 &ring_dma);
856 if (!ring) {
857 printk(KERN_ERR "Could not allocate DMA memory.\n");
858 return -ENOMEM;
859 }
860 if (rp->quirks & rqRhineI) {
861 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
862 PKT_BUF_SZ * TX_RING_SIZE,
863 &rp->tx_bufs_dma);
864 if (rp->tx_bufs == NULL) {
865 pci_free_consistent(rp->pdev,
866 RX_RING_SIZE * sizeof(struct rx_desc) +
867 TX_RING_SIZE * sizeof(struct tx_desc),
868 ring, ring_dma);
869 return -ENOMEM;
870 }
871 }
872
873 rp->rx_ring = ring;
874 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
875 rp->rx_ring_dma = ring_dma;
876 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
877
878 return 0;
879 }
880
free_ring(struct net_device * dev)881 static void free_ring(struct net_device* dev)
882 {
883 struct rhine_private *rp = netdev_priv(dev);
884
885 pci_free_consistent(rp->pdev,
886 RX_RING_SIZE * sizeof(struct rx_desc) +
887 TX_RING_SIZE * sizeof(struct tx_desc),
888 rp->rx_ring, rp->rx_ring_dma);
889 rp->tx_ring = NULL;
890
891 if (rp->tx_bufs)
892 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
893 rp->tx_bufs, rp->tx_bufs_dma);
894
895 rp->tx_bufs = NULL;
896
897 }
898
alloc_rbufs(struct net_device * dev)899 static void alloc_rbufs(struct net_device *dev)
900 {
901 struct rhine_private *rp = netdev_priv(dev);
902 dma_addr_t next;
903 int i;
904
905 rp->dirty_rx = rp->cur_rx = 0;
906
907 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
908 rp->rx_head_desc = &rp->rx_ring[0];
909 next = rp->rx_ring_dma;
910
911 /* Init the ring entries */
912 for (i = 0; i < RX_RING_SIZE; i++) {
913 rp->rx_ring[i].rx_status = 0;
914 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
915 next += sizeof(struct rx_desc);
916 rp->rx_ring[i].next_desc = cpu_to_le32(next);
917 rp->rx_skbuff[i] = NULL;
918 }
919 /* Mark the last entry as wrapping the ring. */
920 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
921
922 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
923 for (i = 0; i < RX_RING_SIZE; i++) {
924 struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
925 rp->rx_skbuff[i] = skb;
926 if (skb == NULL)
927 break;
928 skb->dev = dev; /* Mark as being used by this device. */
929
930 rp->rx_skbuff_dma[i] =
931 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
932 PCI_DMA_FROMDEVICE);
933
934 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
935 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
936 }
937 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
938 }
939
free_rbufs(struct net_device * dev)940 static void free_rbufs(struct net_device* dev)
941 {
942 struct rhine_private *rp = netdev_priv(dev);
943 int i;
944
945 /* Free all the skbuffs in the Rx queue. */
946 for (i = 0; i < RX_RING_SIZE; i++) {
947 rp->rx_ring[i].rx_status = 0;
948 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
949 if (rp->rx_skbuff[i]) {
950 pci_unmap_single(rp->pdev,
951 rp->rx_skbuff_dma[i],
952 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
953 dev_kfree_skb(rp->rx_skbuff[i]);
954 }
955 rp->rx_skbuff[i] = NULL;
956 }
957 }
958
alloc_tbufs(struct net_device * dev)959 static void alloc_tbufs(struct net_device* dev)
960 {
961 struct rhine_private *rp = netdev_priv(dev);
962 dma_addr_t next;
963 int i;
964
965 rp->dirty_tx = rp->cur_tx = 0;
966 next = rp->tx_ring_dma;
967 for (i = 0; i < TX_RING_SIZE; i++) {
968 rp->tx_skbuff[i] = NULL;
969 rp->tx_ring[i].tx_status = 0;
970 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
971 next += sizeof(struct tx_desc);
972 rp->tx_ring[i].next_desc = cpu_to_le32(next);
973 if (rp->quirks & rqRhineI)
974 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
975 }
976 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
977
978 }
979
free_tbufs(struct net_device * dev)980 static void free_tbufs(struct net_device* dev)
981 {
982 struct rhine_private *rp = netdev_priv(dev);
983 int i;
984
985 for (i = 0; i < TX_RING_SIZE; i++) {
986 rp->tx_ring[i].tx_status = 0;
987 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
988 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
989 if (rp->tx_skbuff[i]) {
990 if (rp->tx_skbuff_dma[i]) {
991 pci_unmap_single(rp->pdev,
992 rp->tx_skbuff_dma[i],
993 rp->tx_skbuff[i]->len,
994 PCI_DMA_TODEVICE);
995 }
996 dev_kfree_skb(rp->tx_skbuff[i]);
997 }
998 rp->tx_skbuff[i] = NULL;
999 rp->tx_buf[i] = NULL;
1000 }
1001 }
1002
rhine_check_media(struct net_device * dev,unsigned int init_media)1003 static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1004 {
1005 struct rhine_private *rp = netdev_priv(dev);
1006 void __iomem *ioaddr = rp->base;
1007
1008 mii_check_media(&rp->mii_if, debug, init_media);
1009
1010 if (rp->mii_if.full_duplex)
1011 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1012 ioaddr + ChipCmd1);
1013 else
1014 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1015 ioaddr + ChipCmd1);
1016 if (debug > 1)
1017 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1018 rp->mii_if.force_media, netif_carrier_ok(dev));
1019 }
1020
1021 /* Called after status of force_media possibly changed */
rhine_set_carrier(struct mii_if_info * mii)1022 static void rhine_set_carrier(struct mii_if_info *mii)
1023 {
1024 if (mii->force_media) {
1025 /* autoneg is off: Link is always assumed to be up */
1026 if (!netif_carrier_ok(mii->dev))
1027 netif_carrier_on(mii->dev);
1028 }
1029 else /* Let MMI library update carrier status */
1030 rhine_check_media(mii->dev, 0);
1031 if (debug > 1)
1032 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1033 mii->dev->name, mii->force_media,
1034 netif_carrier_ok(mii->dev));
1035 }
1036
init_registers(struct net_device * dev)1037 static void init_registers(struct net_device *dev)
1038 {
1039 struct rhine_private *rp = netdev_priv(dev);
1040 void __iomem *ioaddr = rp->base;
1041 int i;
1042
1043 for (i = 0; i < 6; i++)
1044 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1045
1046 /* Initialize other registers. */
1047 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1048 /* Configure initial FIFO thresholds. */
1049 iowrite8(0x20, ioaddr + TxConfig);
1050 rp->tx_thresh = 0x20;
1051 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1052
1053 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1054 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1055
1056 rhine_set_rx_mode(dev);
1057
1058 napi_enable(&rp->napi);
1059
1060 /* Enable interrupts by setting the interrupt mask. */
1061 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1062 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1063 IntrTxDone | IntrTxError | IntrTxUnderrun |
1064 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1065 ioaddr + IntrEnable);
1066
1067 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1068 ioaddr + ChipCmd);
1069 rhine_check_media(dev, 1);
1070 }
1071
1072 /* Enable MII link status auto-polling (required for IntrLinkChange) */
rhine_enable_linkmon(void __iomem * ioaddr)1073 static void rhine_enable_linkmon(void __iomem *ioaddr)
1074 {
1075 iowrite8(0, ioaddr + MIICmd);
1076 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1077 iowrite8(0x80, ioaddr + MIICmd);
1078
1079 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1080
1081 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1082 }
1083
1084 /* Disable MII link status auto-polling (required for MDIO access) */
rhine_disable_linkmon(void __iomem * ioaddr,u32 quirks)1085 static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1086 {
1087 iowrite8(0, ioaddr + MIICmd);
1088
1089 if (quirks & rqRhineI) {
1090 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1091
1092 /* Can be called from ISR. Evil. */
1093 mdelay(1);
1094
1095 /* 0x80 must be set immediately before turning it off */
1096 iowrite8(0x80, ioaddr + MIICmd);
1097
1098 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1099
1100 /* Heh. Now clear 0x80 again. */
1101 iowrite8(0, ioaddr + MIICmd);
1102 }
1103 else
1104 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1105 }
1106
1107 /* Read and write over the MII Management Data I/O (MDIO) interface. */
1108
mdio_read(struct net_device * dev,int phy_id,int regnum)1109 static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1110 {
1111 struct rhine_private *rp = netdev_priv(dev);
1112 void __iomem *ioaddr = rp->base;
1113 int result;
1114
1115 rhine_disable_linkmon(ioaddr, rp->quirks);
1116
1117 /* rhine_disable_linkmon already cleared MIICmd */
1118 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1119 iowrite8(regnum, ioaddr + MIIRegAddr);
1120 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1121 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1122 result = ioread16(ioaddr + MIIData);
1123
1124 rhine_enable_linkmon(ioaddr);
1125 return result;
1126 }
1127
mdio_write(struct net_device * dev,int phy_id,int regnum,int value)1128 static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1129 {
1130 struct rhine_private *rp = netdev_priv(dev);
1131 void __iomem *ioaddr = rp->base;
1132
1133 rhine_disable_linkmon(ioaddr, rp->quirks);
1134
1135 /* rhine_disable_linkmon already cleared MIICmd */
1136 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1137 iowrite8(regnum, ioaddr + MIIRegAddr);
1138 iowrite16(value, ioaddr + MIIData);
1139 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1140 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1141
1142 rhine_enable_linkmon(ioaddr);
1143 }
1144
rhine_open(struct net_device * dev)1145 static int rhine_open(struct net_device *dev)
1146 {
1147 struct rhine_private *rp = netdev_priv(dev);
1148 void __iomem *ioaddr = rp->base;
1149 int rc;
1150
1151 rc = request_irq(rp->pdev->irq, &rhine_interrupt, IRQF_SHARED, dev->name,
1152 dev);
1153 if (rc)
1154 return rc;
1155
1156 if (debug > 1)
1157 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1158 dev->name, rp->pdev->irq);
1159
1160 rc = alloc_ring(dev);
1161 if (rc) {
1162 free_irq(rp->pdev->irq, dev);
1163 return rc;
1164 }
1165 alloc_rbufs(dev);
1166 alloc_tbufs(dev);
1167 rhine_chip_reset(dev);
1168 init_registers(dev);
1169 if (debug > 2)
1170 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1171 "MII status: %4.4x.\n",
1172 dev->name, ioread16(ioaddr + ChipCmd),
1173 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1174
1175 netif_start_queue(dev);
1176
1177 return 0;
1178 }
1179
rhine_tx_timeout(struct net_device * dev)1180 static void rhine_tx_timeout(struct net_device *dev)
1181 {
1182 struct rhine_private *rp = netdev_priv(dev);
1183 void __iomem *ioaddr = rp->base;
1184
1185 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1186 "%4.4x, resetting...\n",
1187 dev->name, ioread16(ioaddr + IntrStatus),
1188 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1189
1190 /* protect against concurrent rx interrupts */
1191 disable_irq(rp->pdev->irq);
1192
1193 napi_disable(&rp->napi);
1194
1195 spin_lock(&rp->lock);
1196
1197 /* clear all descriptors */
1198 free_tbufs(dev);
1199 free_rbufs(dev);
1200 alloc_tbufs(dev);
1201 alloc_rbufs(dev);
1202
1203 /* Reinitialize the hardware. */
1204 rhine_chip_reset(dev);
1205 init_registers(dev);
1206
1207 spin_unlock(&rp->lock);
1208 enable_irq(rp->pdev->irq);
1209
1210 dev->trans_start = jiffies;
1211 rp->stats.tx_errors++;
1212 netif_wake_queue(dev);
1213 }
1214
rhine_start_tx(struct sk_buff * skb,struct net_device * dev)1215 static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1216 {
1217 struct rhine_private *rp = netdev_priv(dev);
1218 void __iomem *ioaddr = rp->base;
1219 unsigned entry;
1220
1221 /* Caution: the write order is important here, set the field
1222 with the "ownership" bits last. */
1223
1224 /* Calculate the next Tx descriptor entry. */
1225 entry = rp->cur_tx % TX_RING_SIZE;
1226
1227 if (skb_padto(skb, ETH_ZLEN))
1228 return 0;
1229
1230 rp->tx_skbuff[entry] = skb;
1231
1232 if ((rp->quirks & rqRhineI) &&
1233 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
1234 /* Must use alignment buffer. */
1235 if (skb->len > PKT_BUF_SZ) {
1236 /* packet too long, drop it */
1237 dev_kfree_skb(skb);
1238 rp->tx_skbuff[entry] = NULL;
1239 rp->stats.tx_dropped++;
1240 return 0;
1241 }
1242
1243 /* Padding is not copied and so must be redone. */
1244 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1245 if (skb->len < ETH_ZLEN)
1246 memset(rp->tx_buf[entry] + skb->len, 0,
1247 ETH_ZLEN - skb->len);
1248 rp->tx_skbuff_dma[entry] = 0;
1249 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1250 (rp->tx_buf[entry] -
1251 rp->tx_bufs));
1252 } else {
1253 rp->tx_skbuff_dma[entry] =
1254 pci_map_single(rp->pdev, skb->data, skb->len,
1255 PCI_DMA_TODEVICE);
1256 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1257 }
1258
1259 rp->tx_ring[entry].desc_length =
1260 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1261
1262 /* lock eth irq */
1263 spin_lock_irq(&rp->lock);
1264 wmb();
1265 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1266 wmb();
1267
1268 rp->cur_tx++;
1269
1270 /* Non-x86 Todo: explicitly flush cache lines here. */
1271
1272 /* Wake the potentially-idle transmit channel */
1273 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1274 ioaddr + ChipCmd1);
1275 IOSYNC;
1276
1277 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1278 netif_stop_queue(dev);
1279
1280 dev->trans_start = jiffies;
1281
1282 spin_unlock_irq(&rp->lock);
1283
1284 if (debug > 4) {
1285 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1286 dev->name, rp->cur_tx-1, entry);
1287 }
1288 return 0;
1289 }
1290
1291 /* The interrupt handler does all of the Rx thread work and cleans up
1292 after the Tx thread. */
rhine_interrupt(int irq,void * dev_instance)1293 static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
1294 {
1295 struct net_device *dev = dev_instance;
1296 struct rhine_private *rp = netdev_priv(dev);
1297 void __iomem *ioaddr = rp->base;
1298 u32 intr_status;
1299 int boguscnt = max_interrupt_work;
1300 int handled = 0;
1301
1302 while ((intr_status = get_intr_status(dev))) {
1303 handled = 1;
1304
1305 /* Acknowledge all of the current interrupt sources ASAP. */
1306 if (intr_status & IntrTxDescRace)
1307 iowrite8(0x08, ioaddr + IntrStatus2);
1308 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1309 IOSYNC;
1310
1311 if (debug > 4)
1312 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1313 dev->name, intr_status);
1314
1315 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
1316 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
1317 iowrite16(IntrTxAborted |
1318 IntrTxDone | IntrTxError | IntrTxUnderrun |
1319 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1320 ioaddr + IntrEnable);
1321
1322 netif_rx_schedule(&rp->napi);
1323 }
1324
1325 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1326 if (intr_status & IntrTxErrSummary) {
1327 /* Avoid scavenging before Tx engine turned off */
1328 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1329 if (debug > 2 &&
1330 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1331 printk(KERN_WARNING "%s: "
1332 "rhine_interrupt() Tx engine "
1333 "still on.\n", dev->name);
1334 }
1335 rhine_tx(dev);
1336 }
1337
1338 /* Abnormal error summary/uncommon events handlers. */
1339 if (intr_status & (IntrPCIErr | IntrLinkChange |
1340 IntrStatsMax | IntrTxError | IntrTxAborted |
1341 IntrTxUnderrun | IntrTxDescRace))
1342 rhine_error(dev, intr_status);
1343
1344 if (--boguscnt < 0) {
1345 printk(KERN_WARNING "%s: Too much work at interrupt, "
1346 "status=%#8.8x.\n",
1347 dev->name, intr_status);
1348 break;
1349 }
1350 }
1351
1352 if (debug > 3)
1353 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1354 dev->name, ioread16(ioaddr + IntrStatus));
1355 return IRQ_RETVAL(handled);
1356 }
1357
1358 /* This routine is logically part of the interrupt handler, but isolated
1359 for clarity. */
rhine_tx(struct net_device * dev)1360 static void rhine_tx(struct net_device *dev)
1361 {
1362 struct rhine_private *rp = netdev_priv(dev);
1363 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1364
1365 spin_lock(&rp->lock);
1366
1367 /* find and cleanup dirty tx descriptors */
1368 while (rp->dirty_tx != rp->cur_tx) {
1369 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1370 if (debug > 6)
1371 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
1372 entry, txstatus);
1373 if (txstatus & DescOwn)
1374 break;
1375 if (txstatus & 0x8000) {
1376 if (debug > 1)
1377 printk(KERN_DEBUG "%s: Transmit error, "
1378 "Tx status %8.8x.\n",
1379 dev->name, txstatus);
1380 rp->stats.tx_errors++;
1381 if (txstatus & 0x0400) rp->stats.tx_carrier_errors++;
1382 if (txstatus & 0x0200) rp->stats.tx_window_errors++;
1383 if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
1384 if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
1385 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1386 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1387 rp->stats.tx_fifo_errors++;
1388 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1389 break; /* Keep the skb - we try again */
1390 }
1391 /* Transmitter restarted in 'abnormal' handler. */
1392 } else {
1393 if (rp->quirks & rqRhineI)
1394 rp->stats.collisions += (txstatus >> 3) & 0x0F;
1395 else
1396 rp->stats.collisions += txstatus & 0x0F;
1397 if (debug > 6)
1398 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1399 (txstatus >> 3) & 0xF,
1400 txstatus & 0xF);
1401 rp->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1402 rp->stats.tx_packets++;
1403 }
1404 /* Free the original skb. */
1405 if (rp->tx_skbuff_dma[entry]) {
1406 pci_unmap_single(rp->pdev,
1407 rp->tx_skbuff_dma[entry],
1408 rp->tx_skbuff[entry]->len,
1409 PCI_DMA_TODEVICE);
1410 }
1411 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1412 rp->tx_skbuff[entry] = NULL;
1413 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1414 }
1415 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1416 netif_wake_queue(dev);
1417
1418 spin_unlock(&rp->lock);
1419 }
1420
1421 /* Process up to limit frames from receive ring */
rhine_rx(struct net_device * dev,int limit)1422 static int rhine_rx(struct net_device *dev, int limit)
1423 {
1424 struct rhine_private *rp = netdev_priv(dev);
1425 int count;
1426 int entry = rp->cur_rx % RX_RING_SIZE;
1427
1428 if (debug > 4) {
1429 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1430 dev->name, entry,
1431 le32_to_cpu(rp->rx_head_desc->rx_status));
1432 }
1433
1434 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1435 for (count = 0; count < limit; ++count) {
1436 struct rx_desc *desc = rp->rx_head_desc;
1437 u32 desc_status = le32_to_cpu(desc->rx_status);
1438 int data_size = desc_status >> 16;
1439
1440 if (desc_status & DescOwn)
1441 break;
1442
1443 if (debug > 4)
1444 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
1445 desc_status);
1446
1447 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1448 if ((desc_status & RxWholePkt) != RxWholePkt) {
1449 printk(KERN_WARNING "%s: Oversized Ethernet "
1450 "frame spanned multiple buffers, entry "
1451 "%#x length %d status %8.8x!\n",
1452 dev->name, entry, data_size,
1453 desc_status);
1454 printk(KERN_WARNING "%s: Oversized Ethernet "
1455 "frame %p vs %p.\n", dev->name,
1456 rp->rx_head_desc, &rp->rx_ring[entry]);
1457 rp->stats.rx_length_errors++;
1458 } else if (desc_status & RxErr) {
1459 /* There was a error. */
1460 if (debug > 2)
1461 printk(KERN_DEBUG "rhine_rx() Rx "
1462 "error was %8.8x.\n",
1463 desc_status);
1464 rp->stats.rx_errors++;
1465 if (desc_status & 0x0030) rp->stats.rx_length_errors++;
1466 if (desc_status & 0x0048) rp->stats.rx_fifo_errors++;
1467 if (desc_status & 0x0004) rp->stats.rx_frame_errors++;
1468 if (desc_status & 0x0002) {
1469 /* this can also be updated outside the interrupt handler */
1470 spin_lock(&rp->lock);
1471 rp->stats.rx_crc_errors++;
1472 spin_unlock(&rp->lock);
1473 }
1474 }
1475 } else {
1476 struct sk_buff *skb;
1477 /* Length should omit the CRC */
1478 int pkt_len = data_size - 4;
1479
1480 /* Check if the packet is long enough to accept without
1481 copying to a minimally-sized skbuff. */
1482 if (pkt_len < rx_copybreak &&
1483 (skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN)) != NULL) {
1484 skb_reserve(skb, NET_IP_ALIGN); /* 16 byte align the IP header */
1485 pci_dma_sync_single_for_cpu(rp->pdev,
1486 rp->rx_skbuff_dma[entry],
1487 rp->rx_buf_sz,
1488 PCI_DMA_FROMDEVICE);
1489
1490 skb_copy_to_linear_data(skb,
1491 rp->rx_skbuff[entry]->data,
1492 pkt_len);
1493 skb_put(skb, pkt_len);
1494 pci_dma_sync_single_for_device(rp->pdev,
1495 rp->rx_skbuff_dma[entry],
1496 rp->rx_buf_sz,
1497 PCI_DMA_FROMDEVICE);
1498 } else {
1499 skb = rp->rx_skbuff[entry];
1500 if (skb == NULL) {
1501 printk(KERN_ERR "%s: Inconsistent Rx "
1502 "descriptor chain.\n",
1503 dev->name);
1504 break;
1505 }
1506 rp->rx_skbuff[entry] = NULL;
1507 skb_put(skb, pkt_len);
1508 pci_unmap_single(rp->pdev,
1509 rp->rx_skbuff_dma[entry],
1510 rp->rx_buf_sz,
1511 PCI_DMA_FROMDEVICE);
1512 }
1513 skb->protocol = eth_type_trans(skb, dev);
1514 netif_receive_skb(skb);
1515 rp->stats.rx_bytes += pkt_len;
1516 rp->stats.rx_packets++;
1517 }
1518 entry = (++rp->cur_rx) % RX_RING_SIZE;
1519 rp->rx_head_desc = &rp->rx_ring[entry];
1520 }
1521
1522 /* Refill the Rx ring buffers. */
1523 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1524 struct sk_buff *skb;
1525 entry = rp->dirty_rx % RX_RING_SIZE;
1526 if (rp->rx_skbuff[entry] == NULL) {
1527 skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1528 rp->rx_skbuff[entry] = skb;
1529 if (skb == NULL)
1530 break; /* Better luck next round. */
1531 skb->dev = dev; /* Mark as being used by this device. */
1532 rp->rx_skbuff_dma[entry] =
1533 pci_map_single(rp->pdev, skb->data,
1534 rp->rx_buf_sz,
1535 PCI_DMA_FROMDEVICE);
1536 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1537 }
1538 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1539 }
1540
1541 return count;
1542 }
1543
1544 /*
1545 * Clears the "tally counters" for CRC errors and missed frames(?).
1546 * It has been reported that some chips need a write of 0 to clear
1547 * these, for others the counters are set to 1 when written to and
1548 * instead cleared when read. So we clear them both ways ...
1549 */
clear_tally_counters(void __iomem * ioaddr)1550 static inline void clear_tally_counters(void __iomem *ioaddr)
1551 {
1552 iowrite32(0, ioaddr + RxMissed);
1553 ioread16(ioaddr + RxCRCErrs);
1554 ioread16(ioaddr + RxMissed);
1555 }
1556
rhine_restart_tx(struct net_device * dev)1557 static void rhine_restart_tx(struct net_device *dev) {
1558 struct rhine_private *rp = netdev_priv(dev);
1559 void __iomem *ioaddr = rp->base;
1560 int entry = rp->dirty_tx % TX_RING_SIZE;
1561 u32 intr_status;
1562
1563 /*
1564 * If new errors occured, we need to sort them out before doing Tx.
1565 * In that case the ISR will be back here RSN anyway.
1566 */
1567 intr_status = get_intr_status(dev);
1568
1569 if ((intr_status & IntrTxErrSummary) == 0) {
1570
1571 /* We know better than the chip where it should continue. */
1572 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1573 ioaddr + TxRingPtr);
1574
1575 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1576 ioaddr + ChipCmd);
1577 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1578 ioaddr + ChipCmd1);
1579 IOSYNC;
1580 }
1581 else {
1582 /* This should never happen */
1583 if (debug > 1)
1584 printk(KERN_WARNING "%s: rhine_restart_tx() "
1585 "Another error occured %8.8x.\n",
1586 dev->name, intr_status);
1587 }
1588
1589 }
1590
rhine_error(struct net_device * dev,int intr_status)1591 static void rhine_error(struct net_device *dev, int intr_status)
1592 {
1593 struct rhine_private *rp = netdev_priv(dev);
1594 void __iomem *ioaddr = rp->base;
1595
1596 spin_lock(&rp->lock);
1597
1598 if (intr_status & IntrLinkChange)
1599 rhine_check_media(dev, 0);
1600 if (intr_status & IntrStatsMax) {
1601 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1602 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1603 clear_tally_counters(ioaddr);
1604 }
1605 if (intr_status & IntrTxAborted) {
1606 if (debug > 1)
1607 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1608 dev->name, intr_status);
1609 }
1610 if (intr_status & IntrTxUnderrun) {
1611 if (rp->tx_thresh < 0xE0)
1612 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1613 if (debug > 1)
1614 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1615 "threshold now %2.2x.\n",
1616 dev->name, rp->tx_thresh);
1617 }
1618 if (intr_status & IntrTxDescRace) {
1619 if (debug > 2)
1620 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1621 dev->name);
1622 }
1623 if ((intr_status & IntrTxError) &&
1624 (intr_status & (IntrTxAborted |
1625 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1626 if (rp->tx_thresh < 0xE0) {
1627 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1628 }
1629 if (debug > 1)
1630 printk(KERN_INFO "%s: Unspecified error. Tx "
1631 "threshold now %2.2x.\n",
1632 dev->name, rp->tx_thresh);
1633 }
1634 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1635 IntrTxError))
1636 rhine_restart_tx(dev);
1637
1638 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1639 IntrTxError | IntrTxAborted | IntrNormalSummary |
1640 IntrTxDescRace)) {
1641 if (debug > 1)
1642 printk(KERN_ERR "%s: Something Wicked happened! "
1643 "%8.8x.\n", dev->name, intr_status);
1644 }
1645
1646 spin_unlock(&rp->lock);
1647 }
1648
rhine_get_stats(struct net_device * dev)1649 static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1650 {
1651 struct rhine_private *rp = netdev_priv(dev);
1652 void __iomem *ioaddr = rp->base;
1653 unsigned long flags;
1654
1655 spin_lock_irqsave(&rp->lock, flags);
1656 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1657 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1658 clear_tally_counters(ioaddr);
1659 spin_unlock_irqrestore(&rp->lock, flags);
1660
1661 return &rp->stats;
1662 }
1663
rhine_set_rx_mode(struct net_device * dev)1664 static void rhine_set_rx_mode(struct net_device *dev)
1665 {
1666 struct rhine_private *rp = netdev_priv(dev);
1667 void __iomem *ioaddr = rp->base;
1668 u32 mc_filter[2]; /* Multicast hash filter */
1669 u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1670
1671 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1672 rx_mode = 0x1C;
1673 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1674 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1675 } else if ((dev->mc_count > multicast_filter_limit)
1676 || (dev->flags & IFF_ALLMULTI)) {
1677 /* Too many to match, or accept all multicasts. */
1678 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1679 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1680 rx_mode = 0x0C;
1681 } else {
1682 struct dev_mc_list *mclist;
1683 int i;
1684 memset(mc_filter, 0, sizeof(mc_filter));
1685 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1686 i++, mclist = mclist->next) {
1687 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1688
1689 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1690 }
1691 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1692 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1693 rx_mode = 0x0C;
1694 }
1695 iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1696 }
1697
netdev_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1698 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1699 {
1700 struct rhine_private *rp = netdev_priv(dev);
1701
1702 strcpy(info->driver, DRV_NAME);
1703 strcpy(info->version, DRV_VERSION);
1704 strcpy(info->bus_info, pci_name(rp->pdev));
1705 }
1706
netdev_get_settings(struct net_device * dev,struct ethtool_cmd * cmd)1707 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1708 {
1709 struct rhine_private *rp = netdev_priv(dev);
1710 int rc;
1711
1712 spin_lock_irq(&rp->lock);
1713 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1714 spin_unlock_irq(&rp->lock);
1715
1716 return rc;
1717 }
1718
netdev_set_settings(struct net_device * dev,struct ethtool_cmd * cmd)1719 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1720 {
1721 struct rhine_private *rp = netdev_priv(dev);
1722 int rc;
1723
1724 spin_lock_irq(&rp->lock);
1725 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1726 spin_unlock_irq(&rp->lock);
1727 rhine_set_carrier(&rp->mii_if);
1728
1729 return rc;
1730 }
1731
netdev_nway_reset(struct net_device * dev)1732 static int netdev_nway_reset(struct net_device *dev)
1733 {
1734 struct rhine_private *rp = netdev_priv(dev);
1735
1736 return mii_nway_restart(&rp->mii_if);
1737 }
1738
netdev_get_link(struct net_device * dev)1739 static u32 netdev_get_link(struct net_device *dev)
1740 {
1741 struct rhine_private *rp = netdev_priv(dev);
1742
1743 return mii_link_ok(&rp->mii_if);
1744 }
1745
netdev_get_msglevel(struct net_device * dev)1746 static u32 netdev_get_msglevel(struct net_device *dev)
1747 {
1748 return debug;
1749 }
1750
netdev_set_msglevel(struct net_device * dev,u32 value)1751 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1752 {
1753 debug = value;
1754 }
1755
rhine_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1756 static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1757 {
1758 struct rhine_private *rp = netdev_priv(dev);
1759
1760 if (!(rp->quirks & rqWOL))
1761 return;
1762
1763 spin_lock_irq(&rp->lock);
1764 wol->supported = WAKE_PHY | WAKE_MAGIC |
1765 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1766 wol->wolopts = rp->wolopts;
1767 spin_unlock_irq(&rp->lock);
1768 }
1769
rhine_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1770 static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1771 {
1772 struct rhine_private *rp = netdev_priv(dev);
1773 u32 support = WAKE_PHY | WAKE_MAGIC |
1774 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1775
1776 if (!(rp->quirks & rqWOL))
1777 return -EINVAL;
1778
1779 if (wol->wolopts & ~support)
1780 return -EINVAL;
1781
1782 spin_lock_irq(&rp->lock);
1783 rp->wolopts = wol->wolopts;
1784 spin_unlock_irq(&rp->lock);
1785
1786 return 0;
1787 }
1788
1789 static const struct ethtool_ops netdev_ethtool_ops = {
1790 .get_drvinfo = netdev_get_drvinfo,
1791 .get_settings = netdev_get_settings,
1792 .set_settings = netdev_set_settings,
1793 .nway_reset = netdev_nway_reset,
1794 .get_link = netdev_get_link,
1795 .get_msglevel = netdev_get_msglevel,
1796 .set_msglevel = netdev_set_msglevel,
1797 .get_wol = rhine_get_wol,
1798 .set_wol = rhine_set_wol,
1799 };
1800
netdev_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1801 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1802 {
1803 struct rhine_private *rp = netdev_priv(dev);
1804 int rc;
1805
1806 if (!netif_running(dev))
1807 return -EINVAL;
1808
1809 spin_lock_irq(&rp->lock);
1810 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1811 spin_unlock_irq(&rp->lock);
1812 rhine_set_carrier(&rp->mii_if);
1813
1814 return rc;
1815 }
1816
rhine_close(struct net_device * dev)1817 static int rhine_close(struct net_device *dev)
1818 {
1819 struct rhine_private *rp = netdev_priv(dev);
1820 void __iomem *ioaddr = rp->base;
1821
1822 spin_lock_irq(&rp->lock);
1823
1824 netif_stop_queue(dev);
1825 napi_disable(&rp->napi);
1826
1827 if (debug > 1)
1828 printk(KERN_DEBUG "%s: Shutting down ethercard, "
1829 "status was %4.4x.\n",
1830 dev->name, ioread16(ioaddr + ChipCmd));
1831
1832 /* Switch to loopback mode to avoid hardware races. */
1833 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1834
1835 /* Disable interrupts by clearing the interrupt mask. */
1836 iowrite16(0x0000, ioaddr + IntrEnable);
1837
1838 /* Stop the chip's Tx and Rx processes. */
1839 iowrite16(CmdStop, ioaddr + ChipCmd);
1840
1841 spin_unlock_irq(&rp->lock);
1842
1843 free_irq(rp->pdev->irq, dev);
1844 free_rbufs(dev);
1845 free_tbufs(dev);
1846 free_ring(dev);
1847
1848 return 0;
1849 }
1850
1851
rhine_remove_one(struct pci_dev * pdev)1852 static void __devexit rhine_remove_one(struct pci_dev *pdev)
1853 {
1854 struct net_device *dev = pci_get_drvdata(pdev);
1855 struct rhine_private *rp = netdev_priv(dev);
1856
1857 unregister_netdev(dev);
1858
1859 pci_iounmap(pdev, rp->base);
1860 pci_release_regions(pdev);
1861
1862 free_netdev(dev);
1863 pci_disable_device(pdev);
1864 pci_set_drvdata(pdev, NULL);
1865 }
1866
rhine_shutdown(struct pci_dev * pdev)1867 static void rhine_shutdown (struct pci_dev *pdev)
1868 {
1869 struct net_device *dev = pci_get_drvdata(pdev);
1870 struct rhine_private *rp = netdev_priv(dev);
1871 void __iomem *ioaddr = rp->base;
1872
1873 if (!(rp->quirks & rqWOL))
1874 return; /* Nothing to do for non-WOL adapters */
1875
1876 rhine_power_init(dev);
1877
1878 /* Make sure we use pattern 0, 1 and not 4, 5 */
1879 if (rp->quirks & rq6patterns)
1880 iowrite8(0x04, ioaddr + WOLcgClr);
1881
1882 if (rp->wolopts & WAKE_MAGIC) {
1883 iowrite8(WOLmagic, ioaddr + WOLcrSet);
1884 /*
1885 * Turn EEPROM-controlled wake-up back on -- some hardware may
1886 * not cooperate otherwise.
1887 */
1888 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1889 }
1890
1891 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1892 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1893
1894 if (rp->wolopts & WAKE_PHY)
1895 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1896
1897 if (rp->wolopts & WAKE_UCAST)
1898 iowrite8(WOLucast, ioaddr + WOLcrSet);
1899
1900 if (rp->wolopts) {
1901 /* Enable legacy WOL (for old motherboards) */
1902 iowrite8(0x01, ioaddr + PwcfgSet);
1903 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1904 }
1905
1906 /* Hit power state D3 (sleep) */
1907 if (!avoid_D3)
1908 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
1909
1910 /* TODO: Check use of pci_enable_wake() */
1911
1912 }
1913
1914 #ifdef CONFIG_PM
rhine_suspend(struct pci_dev * pdev,pm_message_t state)1915 static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1916 {
1917 struct net_device *dev = pci_get_drvdata(pdev);
1918 struct rhine_private *rp = netdev_priv(dev);
1919 unsigned long flags;
1920
1921 if (!netif_running(dev))
1922 return 0;
1923
1924 napi_disable(&rp->napi);
1925
1926 netif_device_detach(dev);
1927 pci_save_state(pdev);
1928
1929 spin_lock_irqsave(&rp->lock, flags);
1930 rhine_shutdown(pdev);
1931 spin_unlock_irqrestore(&rp->lock, flags);
1932
1933 free_irq(dev->irq, dev);
1934 return 0;
1935 }
1936
rhine_resume(struct pci_dev * pdev)1937 static int rhine_resume(struct pci_dev *pdev)
1938 {
1939 struct net_device *dev = pci_get_drvdata(pdev);
1940 struct rhine_private *rp = netdev_priv(dev);
1941 unsigned long flags;
1942 int ret;
1943
1944 if (!netif_running(dev))
1945 return 0;
1946
1947 if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
1948 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
1949
1950 ret = pci_set_power_state(pdev, PCI_D0);
1951 if (debug > 1)
1952 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
1953 dev->name, ret ? "failed" : "succeeded", ret);
1954
1955 pci_restore_state(pdev);
1956
1957 spin_lock_irqsave(&rp->lock, flags);
1958 #ifdef USE_MMIO
1959 enable_mmio(rp->pioaddr, rp->quirks);
1960 #endif
1961 rhine_power_init(dev);
1962 free_tbufs(dev);
1963 free_rbufs(dev);
1964 alloc_tbufs(dev);
1965 alloc_rbufs(dev);
1966 init_registers(dev);
1967 spin_unlock_irqrestore(&rp->lock, flags);
1968
1969 netif_device_attach(dev);
1970
1971 return 0;
1972 }
1973 #endif /* CONFIG_PM */
1974
1975 static struct pci_driver rhine_driver = {
1976 .name = DRV_NAME,
1977 .id_table = rhine_pci_tbl,
1978 .probe = rhine_init_one,
1979 .remove = __devexit_p(rhine_remove_one),
1980 #ifdef CONFIG_PM
1981 .suspend = rhine_suspend,
1982 .resume = rhine_resume,
1983 #endif /* CONFIG_PM */
1984 .shutdown = rhine_shutdown,
1985 };
1986
1987 static struct dmi_system_id __initdata rhine_dmi_table[] = {
1988 {
1989 .ident = "EPIA-M",
1990 .matches = {
1991 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
1992 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
1993 },
1994 },
1995 {
1996 .ident = "KV7",
1997 .matches = {
1998 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
1999 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2000 },
2001 },
2002 { NULL }
2003 };
2004
rhine_init(void)2005 static int __init rhine_init(void)
2006 {
2007 /* when a module, this is printed whether or not devices are found in probe */
2008 #ifdef MODULE
2009 printk(version);
2010 #endif
2011 if (dmi_check_system(rhine_dmi_table)) {
2012 /* these BIOSes fail at PXE boot if chip is in D3 */
2013 avoid_D3 = 1;
2014 printk(KERN_WARNING "%s: Broken BIOS detected, avoid_D3 "
2015 "enabled.\n",
2016 DRV_NAME);
2017 }
2018 else if (avoid_D3)
2019 printk(KERN_INFO "%s: avoid_D3 set.\n", DRV_NAME);
2020
2021 return pci_register_driver(&rhine_driver);
2022 }
2023
2024
rhine_cleanup(void)2025 static void __exit rhine_cleanup(void)
2026 {
2027 pci_unregister_driver(&rhine_driver);
2028 }
2029
2030
2031 module_init(rhine_init);
2032 module_exit(rhine_cleanup);
2033