1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "core.h"
19 #include "reg.h"
20 #include "hw.h"
21
22 #define ATH_PCI_VERSION "0.1"
23
24 static char *dev_info = "ath9k";
25
26 MODULE_AUTHOR("Atheros Communications");
27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29 MODULE_LICENSE("Dual BSD/GPL");
30
31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
32 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
33 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
34 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
37 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
38 { 0 }
39 };
40
41 static void ath_detach(struct ath_softc *sc);
42
43 /* return bus cachesize in 4B word units */
44
bus_read_cachesize(struct ath_softc * sc,int * csz)45 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
46 {
47 u8 u8tmp;
48
49 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
50 *csz = (int)u8tmp;
51
52 /*
53 * This check was put in to avoid "unplesant" consequences if
54 * the bootrom has not fully initialized all PCI devices.
55 * Sometimes the cache line size register is not set
56 */
57
58 if (*csz == 0)
59 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
60 }
61
ath_setcurmode(struct ath_softc * sc,enum wireless_mode mode)62 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
63 {
64 sc->cur_rate_table = sc->hw_rate_table[mode];
65 /*
66 * All protection frames are transmited at 2Mb/s for
67 * 11g, otherwise at 1Mb/s.
68 * XXX select protection rate index from rate table.
69 */
70 sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
71 }
72
ath_chan2mode(struct ath9k_channel * chan)73 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
74 {
75 if (chan->chanmode == CHANNEL_A)
76 return ATH9K_MODE_11A;
77 else if (chan->chanmode == CHANNEL_G)
78 return ATH9K_MODE_11G;
79 else if (chan->chanmode == CHANNEL_B)
80 return ATH9K_MODE_11B;
81 else if (chan->chanmode == CHANNEL_A_HT20)
82 return ATH9K_MODE_11NA_HT20;
83 else if (chan->chanmode == CHANNEL_G_HT20)
84 return ATH9K_MODE_11NG_HT20;
85 else if (chan->chanmode == CHANNEL_A_HT40PLUS)
86 return ATH9K_MODE_11NA_HT40PLUS;
87 else if (chan->chanmode == CHANNEL_A_HT40MINUS)
88 return ATH9K_MODE_11NA_HT40MINUS;
89 else if (chan->chanmode == CHANNEL_G_HT40PLUS)
90 return ATH9K_MODE_11NG_HT40PLUS;
91 else if (chan->chanmode == CHANNEL_G_HT40MINUS)
92 return ATH9K_MODE_11NG_HT40MINUS;
93
94 WARN_ON(1); /* should not get here */
95
96 return ATH9K_MODE_11B;
97 }
98
ath_update_txpow(struct ath_softc * sc)99 static void ath_update_txpow(struct ath_softc *sc)
100 {
101 struct ath_hal *ah = sc->sc_ah;
102 u32 txpow;
103
104 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
105 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
106 /* read back in case value is clamped */
107 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
108 sc->sc_curtxpow = txpow;
109 }
110 }
111
parse_mpdudensity(u8 mpdudensity)112 static u8 parse_mpdudensity(u8 mpdudensity)
113 {
114 /*
115 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
116 * 0 for no restriction
117 * 1 for 1/4 us
118 * 2 for 1/2 us
119 * 3 for 1 us
120 * 4 for 2 us
121 * 5 for 4 us
122 * 6 for 8 us
123 * 7 for 16 us
124 */
125 switch (mpdudensity) {
126 case 0:
127 return 0;
128 case 1:
129 case 2:
130 case 3:
131 /* Our lower layer calculations limit our precision to
132 1 microsecond */
133 return 1;
134 case 4:
135 return 2;
136 case 5:
137 return 4;
138 case 6:
139 return 8;
140 case 7:
141 return 16;
142 default:
143 return 0;
144 }
145 }
146
ath_setup_rates(struct ath_softc * sc,enum ieee80211_band band)147 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
148 {
149 struct ath_rate_table *rate_table = NULL;
150 struct ieee80211_supported_band *sband;
151 struct ieee80211_rate *rate;
152 int i, maxrates;
153
154 switch (band) {
155 case IEEE80211_BAND_2GHZ:
156 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
157 break;
158 case IEEE80211_BAND_5GHZ:
159 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
160 break;
161 default:
162 break;
163 }
164
165 if (rate_table == NULL)
166 return;
167
168 sband = &sc->sbands[band];
169 rate = sc->rates[band];
170
171 if (rate_table->rate_cnt > ATH_RATE_MAX)
172 maxrates = ATH_RATE_MAX;
173 else
174 maxrates = rate_table->rate_cnt;
175
176 for (i = 0; i < maxrates; i++) {
177 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
178 rate[i].hw_value = rate_table->info[i].ratecode;
179 sband->n_bitrates++;
180 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
181 rate[i].bitrate / 10, rate[i].hw_value);
182 }
183 }
184
ath_setup_channels(struct ath_softc * sc)185 static int ath_setup_channels(struct ath_softc *sc)
186 {
187 struct ath_hal *ah = sc->sc_ah;
188 int nchan, i, a = 0, b = 0;
189 u8 regclassids[ATH_REGCLASSIDS_MAX];
190 u32 nregclass = 0;
191 struct ieee80211_supported_band *band_2ghz;
192 struct ieee80211_supported_band *band_5ghz;
193 struct ieee80211_channel *chan_2ghz;
194 struct ieee80211_channel *chan_5ghz;
195 struct ath9k_channel *c;
196
197 /* Fill in ah->ah_channels */
198 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
199 regclassids, ATH_REGCLASSIDS_MAX,
200 &nregclass, CTRY_DEFAULT, false, 1)) {
201 u32 rd = ah->ah_currentRD;
202 DPRINTF(sc, ATH_DBG_FATAL,
203 "Unable to collect channel list; "
204 "regdomain likely %u country code %u\n",
205 rd, CTRY_DEFAULT);
206 return -EINVAL;
207 }
208
209 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
210 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
211 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
212 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
213
214 for (i = 0; i < nchan; i++) {
215 c = &ah->ah_channels[i];
216 if (IS_CHAN_2GHZ(c)) {
217 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
218 chan_2ghz[a].center_freq = c->channel;
219 chan_2ghz[a].max_power = c->maxTxPower;
220
221 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
222 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
223 if (c->channelFlags & CHANNEL_PASSIVE)
224 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
225
226 band_2ghz->n_channels = ++a;
227
228 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
229 "channelFlags: 0x%x\n",
230 c->channel, c->channelFlags);
231 } else if (IS_CHAN_5GHZ(c)) {
232 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
233 chan_5ghz[b].center_freq = c->channel;
234 chan_5ghz[b].max_power = c->maxTxPower;
235
236 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
237 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
238 if (c->channelFlags & CHANNEL_PASSIVE)
239 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
240
241 band_5ghz->n_channels = ++b;
242
243 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
244 "channelFlags: 0x%x\n",
245 c->channel, c->channelFlags);
246 }
247 }
248
249 return 0;
250 }
251
252 /*
253 * Set/change channels. If the channel is really being changed, it's done
254 * by reseting the chip. To accomplish this we must first cleanup any pending
255 * DMA, then restart stuff.
256 */
ath_set_channel(struct ath_softc * sc,struct ath9k_channel * hchan)257 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
258 {
259 struct ath_hal *ah = sc->sc_ah;
260 bool fastcc = true, stopped;
261
262 if (sc->sc_flags & SC_OP_INVALID)
263 return -EIO;
264
265 if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
266 hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
267 (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
268 (sc->sc_flags & SC_OP_FULL_RESET)) {
269 int status;
270 /*
271 * This is only performed if the channel settings have
272 * actually changed.
273 *
274 * To switch channels clear any pending DMA operations;
275 * wait long enough for the RX fifo to drain, reset the
276 * hardware at the new frequency, and then re-enable
277 * the relevant bits of the h/w.
278 */
279 ath9k_hw_set_interrupts(ah, 0);
280 ath_draintxq(sc, false);
281 stopped = ath_stoprecv(sc);
282
283 /* XXX: do not flush receive queue here. We don't want
284 * to flush data frames already in queue because of
285 * changing channel. */
286
287 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
288 fastcc = false;
289
290 DPRINTF(sc, ATH_DBG_CONFIG,
291 "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
292 sc->sc_ah->ah_curchan->channel,
293 hchan->channel, hchan->channelFlags, sc->tx_chan_width);
294
295 spin_lock_bh(&sc->sc_resetlock);
296 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
297 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
298 sc->sc_ht_extprotspacing, fastcc, &status)) {
299 DPRINTF(sc, ATH_DBG_FATAL,
300 "Unable to reset channel %u (%uMhz) "
301 "flags 0x%x hal status %u\n",
302 ath9k_hw_mhz2ieee(ah, hchan->channel,
303 hchan->channelFlags),
304 hchan->channel, hchan->channelFlags, status);
305 spin_unlock_bh(&sc->sc_resetlock);
306 return -EIO;
307 }
308 spin_unlock_bh(&sc->sc_resetlock);
309
310 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
311 sc->sc_flags &= ~SC_OP_FULL_RESET;
312
313 if (ath_startrecv(sc) != 0) {
314 DPRINTF(sc, ATH_DBG_FATAL,
315 "Unable to restart recv logic\n");
316 return -EIO;
317 }
318
319 ath_setcurmode(sc, ath_chan2mode(hchan));
320 ath_update_txpow(sc);
321 ath9k_hw_set_interrupts(ah, sc->sc_imask);
322 }
323 return 0;
324 }
325
326 /*
327 * This routine performs the periodic noise floor calibration function
328 * that is used to adjust and optimize the chip performance. This
329 * takes environmental changes (location, temperature) into account.
330 * When the task is complete, it reschedules itself depending on the
331 * appropriate interval that was calculated.
332 */
ath_ani_calibrate(unsigned long data)333 static void ath_ani_calibrate(unsigned long data)
334 {
335 struct ath_softc *sc;
336 struct ath_hal *ah;
337 bool longcal = false;
338 bool shortcal = false;
339 bool aniflag = false;
340 unsigned int timestamp = jiffies_to_msecs(jiffies);
341 u32 cal_interval;
342
343 sc = (struct ath_softc *)data;
344 ah = sc->sc_ah;
345
346 /*
347 * don't calibrate when we're scanning.
348 * we are most likely not on our home channel.
349 */
350 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
351 return;
352
353 /* Long calibration runs independently of short calibration. */
354 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
355 longcal = true;
356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
357 sc->sc_ani.sc_longcal_timer = timestamp;
358 }
359
360 /* Short calibration applies only while sc_caldone is false */
361 if (!sc->sc_ani.sc_caldone) {
362 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
363 ATH_SHORT_CALINTERVAL) {
364 shortcal = true;
365 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
366 sc->sc_ani.sc_shortcal_timer = timestamp;
367 sc->sc_ani.sc_resetcal_timer = timestamp;
368 }
369 } else {
370 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
371 ATH_RESTART_CALINTERVAL) {
372 ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
373 &sc->sc_ani.sc_caldone);
374 if (sc->sc_ani.sc_caldone)
375 sc->sc_ani.sc_resetcal_timer = timestamp;
376 }
377 }
378
379 /* Verify whether we must check ANI */
380 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
381 ATH_ANI_POLLINTERVAL) {
382 aniflag = true;
383 sc->sc_ani.sc_checkani_timer = timestamp;
384 }
385
386 /* Skip all processing if there's nothing to do. */
387 if (longcal || shortcal || aniflag) {
388 /* Call ANI routine if necessary */
389 if (aniflag)
390 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
391 ah->ah_curchan);
392
393 /* Perform calibration if necessary */
394 if (longcal || shortcal) {
395 bool iscaldone = false;
396
397 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
398 sc->sc_rx_chainmask, longcal,
399 &iscaldone)) {
400 if (longcal)
401 sc->sc_ani.sc_noise_floor =
402 ath9k_hw_getchan_noise(ah,
403 ah->ah_curchan);
404
405 DPRINTF(sc, ATH_DBG_ANI,
406 "calibrate chan %u/%x nf: %d\n",
407 ah->ah_curchan->channel,
408 ah->ah_curchan->channelFlags,
409 sc->sc_ani.sc_noise_floor);
410 } else {
411 DPRINTF(sc, ATH_DBG_ANY,
412 "calibrate chan %u/%x failed\n",
413 ah->ah_curchan->channel,
414 ah->ah_curchan->channelFlags);
415 }
416 sc->sc_ani.sc_caldone = iscaldone;
417 }
418 }
419
420 /*
421 * Set timer interval based on previous results.
422 * The interval must be the shortest necessary to satisfy ANI,
423 * short calibration and long calibration.
424 */
425 cal_interval = ATH_LONG_CALINTERVAL;
426 if (sc->sc_ah->ah_config.enable_ani)
427 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
428 if (!sc->sc_ani.sc_caldone)
429 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
430
431 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
432 }
433
434 /*
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
437 * the chainmask configuration.
438 */
ath_update_chainmask(struct ath_softc * sc,int is_ht)439 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
440 {
441 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
442 if (is_ht) {
443 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
444 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
445 } else {
446 sc->sc_tx_chainmask = 1;
447 sc->sc_rx_chainmask = 1;
448 }
449
450 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
451 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
452 }
453
ath_node_attach(struct ath_softc * sc,struct ieee80211_sta * sta)454 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
455 {
456 struct ath_node *an;
457
458 an = (struct ath_node *)sta->drv_priv;
459
460 if (sc->sc_flags & SC_OP_TXAGGR)
461 ath_tx_node_init(sc, an);
462
463 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
466 }
467
ath_node_detach(struct ath_softc * sc,struct ieee80211_sta * sta)468 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
469 {
470 struct ath_node *an = (struct ath_node *)sta->drv_priv;
471
472 if (sc->sc_flags & SC_OP_TXAGGR)
473 ath_tx_node_cleanup(sc, an);
474 }
475
ath9k_tasklet(unsigned long data)476 static void ath9k_tasklet(unsigned long data)
477 {
478 struct ath_softc *sc = (struct ath_softc *)data;
479 u32 status = sc->sc_intrstatus;
480
481 if (status & ATH9K_INT_FATAL) {
482 /* need a chip reset */
483 ath_reset(sc, false);
484 return;
485 } else {
486
487 if (status &
488 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
489 spin_lock_bh(&sc->rx.rxflushlock);
490 ath_rx_tasklet(sc, 0);
491 spin_unlock_bh(&sc->rx.rxflushlock);
492 }
493 /* XXX: optimize this */
494 if (status & ATH9K_INT_TX)
495 ath_tx_tasklet(sc);
496 }
497
498 /* re-enable hardware interrupt */
499 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
500 }
501
ath_isr(int irq,void * dev)502 static irqreturn_t ath_isr(int irq, void *dev)
503 {
504 struct ath_softc *sc = dev;
505 struct ath_hal *ah = sc->sc_ah;
506 enum ath9k_int status;
507 bool sched = false;
508
509 do {
510 if (sc->sc_flags & SC_OP_INVALID) {
511 /*
512 * The hardware is not ready/present, don't
513 * touch anything. Note this can happen early
514 * on if the IRQ is shared.
515 */
516 return IRQ_NONE;
517 }
518 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
519 return IRQ_NONE;
520 }
521
522 /*
523 * Figure out the reason(s) for the interrupt. Note
524 * that the hal returns a pseudo-ISR that may include
525 * bits we haven't explicitly enabled so we mask the
526 * value to insure we only process bits we requested.
527 */
528 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
529
530 status &= sc->sc_imask; /* discard unasked-for bits */
531
532 /*
533 * If there are no status bits set, then this interrupt was not
534 * for me (should have been caught above).
535 */
536 if (!status)
537 return IRQ_NONE;
538
539 sc->sc_intrstatus = status;
540
541 if (status & ATH9K_INT_FATAL) {
542 /* need a chip reset */
543 sched = true;
544 } else if (status & ATH9K_INT_RXORN) {
545 /* need a chip reset */
546 sched = true;
547 } else {
548 if (status & ATH9K_INT_SWBA) {
549 /* schedule a tasklet for beacon handling */
550 tasklet_schedule(&sc->bcon_tasklet);
551 }
552 if (status & ATH9K_INT_RXEOL) {
553 /*
554 * NB: the hardware should re-read the link when
555 * RXE bit is written, but it doesn't work
556 * at least on older hardware revs.
557 */
558 sched = true;
559 }
560
561 if (status & ATH9K_INT_TXURN)
562 /* bump tx trigger level */
563 ath9k_hw_updatetxtriglevel(ah, true);
564 /* XXX: optimize this */
565 if (status & ATH9K_INT_RX)
566 sched = true;
567 if (status & ATH9K_INT_TX)
568 sched = true;
569 if (status & ATH9K_INT_BMISS)
570 sched = true;
571 /* carrier sense timeout */
572 if (status & ATH9K_INT_CST)
573 sched = true;
574 if (status & ATH9K_INT_MIB) {
575 /*
576 * Disable interrupts until we service the MIB
577 * interrupt; otherwise it will continue to
578 * fire.
579 */
580 ath9k_hw_set_interrupts(ah, 0);
581 /*
582 * Let the hal handle the event. We assume
583 * it will clear whatever condition caused
584 * the interrupt.
585 */
586 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
587 ath9k_hw_set_interrupts(ah, sc->sc_imask);
588 }
589 if (status & ATH9K_INT_TIM_TIMER) {
590 if (!(ah->ah_caps.hw_caps &
591 ATH9K_HW_CAP_AUTOSLEEP)) {
592 /* Clear RxAbort bit so that we can
593 * receive frames */
594 ath9k_hw_setrxabort(ah, 0);
595 sched = true;
596 }
597 }
598 }
599 } while (0);
600
601 ath_debug_stat_interrupt(sc, status);
602
603 if (sched) {
604 /* turn off every interrupt except SWBA */
605 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
606 tasklet_schedule(&sc->intr_tq);
607 }
608
609 return IRQ_HANDLED;
610 }
611
ath_get_channel(struct ath_softc * sc,struct ieee80211_channel * chan)612 static int ath_get_channel(struct ath_softc *sc,
613 struct ieee80211_channel *chan)
614 {
615 int i;
616
617 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
618 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
619 return i;
620 }
621
622 return -1;
623 }
624
ath_get_extchanmode(struct ath_softc * sc,struct ieee80211_channel * chan,enum nl80211_channel_type channel_type)625 static u32 ath_get_extchanmode(struct ath_softc *sc,
626 struct ieee80211_channel *chan,
627 enum nl80211_channel_type channel_type)
628 {
629 u32 chanmode = 0;
630
631 switch (chan->band) {
632 case IEEE80211_BAND_2GHZ:
633 switch(channel_type) {
634 case NL80211_CHAN_NO_HT:
635 case NL80211_CHAN_HT20:
636 chanmode = CHANNEL_G_HT20;
637 break;
638 case NL80211_CHAN_HT40PLUS:
639 chanmode = CHANNEL_G_HT40PLUS;
640 break;
641 case NL80211_CHAN_HT40MINUS:
642 chanmode = CHANNEL_G_HT40MINUS;
643 break;
644 }
645 break;
646 case IEEE80211_BAND_5GHZ:
647 switch(channel_type) {
648 case NL80211_CHAN_NO_HT:
649 case NL80211_CHAN_HT20:
650 chanmode = CHANNEL_A_HT20;
651 break;
652 case NL80211_CHAN_HT40PLUS:
653 chanmode = CHANNEL_A_HT40PLUS;
654 break;
655 case NL80211_CHAN_HT40MINUS:
656 chanmode = CHANNEL_A_HT40MINUS;
657 break;
658 }
659 break;
660 default:
661 break;
662 }
663
664 return chanmode;
665 }
666
ath_keyset(struct ath_softc * sc,u16 keyix,struct ath9k_keyval * hk,const u8 mac[ETH_ALEN])667 static int ath_keyset(struct ath_softc *sc, u16 keyix,
668 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
669 {
670 bool status;
671
672 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
673 keyix, hk, mac, false);
674
675 return status != false;
676 }
677
ath_setkey_tkip(struct ath_softc * sc,u16 keyix,const u8 * key,struct ath9k_keyval * hk,const u8 * addr)678 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
679 struct ath9k_keyval *hk,
680 const u8 *addr)
681 {
682 const u8 *key_rxmic;
683 const u8 *key_txmic;
684
685 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
686 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
687
688 if (addr == NULL) {
689 /* Group key installation */
690 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
691 return ath_keyset(sc, keyix, hk, addr);
692 }
693 if (!sc->sc_splitmic) {
694 /*
695 * data key goes at first index,
696 * the hal handles the MIC keys at index+64.
697 */
698 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
699 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
700 return ath_keyset(sc, keyix, hk, addr);
701 }
702 /*
703 * TX key goes at first index, RX key at +32.
704 * The hal handles the MIC keys at index+64.
705 */
706 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
707 if (!ath_keyset(sc, keyix, hk, NULL)) {
708 /* Txmic entry failed. No need to proceed further */
709 DPRINTF(sc, ATH_DBG_KEYCACHE,
710 "Setting TX MIC Key Failed\n");
711 return 0;
712 }
713
714 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
715 /* XXX delete tx key on failure? */
716 return ath_keyset(sc, keyix + 32, hk, addr);
717 }
718
ath_reserve_key_cache_slot_tkip(struct ath_softc * sc)719 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
720 {
721 int i;
722
723 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
724 if (test_bit(i, sc->sc_keymap) ||
725 test_bit(i + 64, sc->sc_keymap))
726 continue; /* At least one part of TKIP key allocated */
727 if (sc->sc_splitmic &&
728 (test_bit(i + 32, sc->sc_keymap) ||
729 test_bit(i + 64 + 32, sc->sc_keymap)))
730 continue; /* At least one part of TKIP key allocated */
731
732 /* Found a free slot for a TKIP key */
733 return i;
734 }
735 return -1;
736 }
737
ath_reserve_key_cache_slot(struct ath_softc * sc)738 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
739 {
740 int i;
741
742 /* First, try to find slots that would not be available for TKIP. */
743 if (sc->sc_splitmic) {
744 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
745 if (!test_bit(i, sc->sc_keymap) &&
746 (test_bit(i + 32, sc->sc_keymap) ||
747 test_bit(i + 64, sc->sc_keymap) ||
748 test_bit(i + 64 + 32, sc->sc_keymap)))
749 return i;
750 if (!test_bit(i + 32, sc->sc_keymap) &&
751 (test_bit(i, sc->sc_keymap) ||
752 test_bit(i + 64, sc->sc_keymap) ||
753 test_bit(i + 64 + 32, sc->sc_keymap)))
754 return i + 32;
755 if (!test_bit(i + 64, sc->sc_keymap) &&
756 (test_bit(i , sc->sc_keymap) ||
757 test_bit(i + 32, sc->sc_keymap) ||
758 test_bit(i + 64 + 32, sc->sc_keymap)))
759 return i + 64;
760 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
761 (test_bit(i, sc->sc_keymap) ||
762 test_bit(i + 32, sc->sc_keymap) ||
763 test_bit(i + 64, sc->sc_keymap)))
764 return i + 64 + 32;
765 }
766 } else {
767 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
768 if (!test_bit(i, sc->sc_keymap) &&
769 test_bit(i + 64, sc->sc_keymap))
770 return i;
771 if (test_bit(i, sc->sc_keymap) &&
772 !test_bit(i + 64, sc->sc_keymap))
773 return i + 64;
774 }
775 }
776
777 /* No partially used TKIP slots, pick any available slot */
778 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
779 /* Do not allow slots that could be needed for TKIP group keys
780 * to be used. This limitation could be removed if we know that
781 * TKIP will not be used. */
782 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
783 continue;
784 if (sc->sc_splitmic) {
785 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
786 continue;
787 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
788 continue;
789 }
790
791 if (!test_bit(i, sc->sc_keymap))
792 return i; /* Found a free slot for a key */
793 }
794
795 /* No free slot found */
796 return -1;
797 }
798
ath_key_config(struct ath_softc * sc,const u8 * addr,struct ieee80211_key_conf * key)799 static int ath_key_config(struct ath_softc *sc,
800 const u8 *addr,
801 struct ieee80211_key_conf *key)
802 {
803 struct ath9k_keyval hk;
804 const u8 *mac = NULL;
805 int ret = 0;
806 int idx;
807
808 memset(&hk, 0, sizeof(hk));
809
810 switch (key->alg) {
811 case ALG_WEP:
812 hk.kv_type = ATH9K_CIPHER_WEP;
813 break;
814 case ALG_TKIP:
815 hk.kv_type = ATH9K_CIPHER_TKIP;
816 break;
817 case ALG_CCMP:
818 hk.kv_type = ATH9K_CIPHER_AES_CCM;
819 break;
820 default:
821 return -EINVAL;
822 }
823
824 hk.kv_len = key->keylen;
825 memcpy(hk.kv_val, key->key, key->keylen);
826
827 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
828 /* For now, use the default keys for broadcast keys. This may
829 * need to change with virtual interfaces. */
830 idx = key->keyidx;
831 } else if (key->keyidx) {
832 struct ieee80211_vif *vif;
833
834 mac = addr;
835 vif = sc->sc_vaps[0];
836 if (vif->type != NL80211_IFTYPE_AP) {
837 /* Only keyidx 0 should be used with unicast key, but
838 * allow this for client mode for now. */
839 idx = key->keyidx;
840 } else
841 return -EIO;
842 } else {
843 mac = addr;
844 if (key->alg == ALG_TKIP)
845 idx = ath_reserve_key_cache_slot_tkip(sc);
846 else
847 idx = ath_reserve_key_cache_slot(sc);
848 if (idx < 0)
849 return -EIO; /* no free key cache entries */
850 }
851
852 if (key->alg == ALG_TKIP)
853 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
854 else
855 ret = ath_keyset(sc, idx, &hk, mac);
856
857 if (!ret)
858 return -EIO;
859
860 set_bit(idx, sc->sc_keymap);
861 if (key->alg == ALG_TKIP) {
862 set_bit(idx + 64, sc->sc_keymap);
863 if (sc->sc_splitmic) {
864 set_bit(idx + 32, sc->sc_keymap);
865 set_bit(idx + 64 + 32, sc->sc_keymap);
866 }
867 }
868
869 return idx;
870 }
871
ath_key_delete(struct ath_softc * sc,struct ieee80211_key_conf * key)872 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
873 {
874 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
875 if (key->hw_key_idx < IEEE80211_WEP_NKID)
876 return;
877
878 clear_bit(key->hw_key_idx, sc->sc_keymap);
879 if (key->alg != ALG_TKIP)
880 return;
881
882 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
883 if (sc->sc_splitmic) {
884 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
885 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
886 }
887 }
888
setup_ht_cap(struct ieee80211_sta_ht_cap * ht_info)889 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
890 {
891 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
892 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
893
894 ht_info->ht_supported = true;
895 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
896 IEEE80211_HT_CAP_SM_PS |
897 IEEE80211_HT_CAP_SGI_40 |
898 IEEE80211_HT_CAP_DSSSCCK40;
899
900 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
901 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
902 /* set up supported mcs set */
903 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
904 ht_info->mcs.rx_mask[0] = 0xff;
905 ht_info->mcs.rx_mask[1] = 0xff;
906 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
907 }
908
ath9k_bss_assoc_info(struct ath_softc * sc,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf)909 static void ath9k_bss_assoc_info(struct ath_softc *sc,
910 struct ieee80211_vif *vif,
911 struct ieee80211_bss_conf *bss_conf)
912 {
913 struct ath_vap *avp = (void *)vif->drv_priv;
914
915 if (bss_conf->assoc) {
916 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
917 bss_conf->aid, sc->sc_curbssid);
918
919 /* New association, store aid */
920 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
921 sc->sc_curaid = bss_conf->aid;
922 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
923 sc->sc_curaid);
924 }
925
926 /* Configure the beacon */
927 ath_beacon_config(sc, 0);
928 sc->sc_flags |= SC_OP_BEACONS;
929
930 /* Reset rssi stats */
931 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
932 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
933 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
934 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
935
936 /* Start ANI */
937 mod_timer(&sc->sc_ani.timer,
938 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
939
940 } else {
941 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
942 sc->sc_curaid = 0;
943 }
944 }
945
946 /********************************/
947 /* LED functions */
948 /********************************/
949
ath_led_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)950 static void ath_led_brightness(struct led_classdev *led_cdev,
951 enum led_brightness brightness)
952 {
953 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
954 struct ath_softc *sc = led->sc;
955
956 switch (brightness) {
957 case LED_OFF:
958 if (led->led_type == ATH_LED_ASSOC ||
959 led->led_type == ATH_LED_RADIO)
960 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
961 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
962 (led->led_type == ATH_LED_RADIO) ? 1 :
963 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
964 break;
965 case LED_FULL:
966 if (led->led_type == ATH_LED_ASSOC)
967 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
968 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
969 break;
970 default:
971 break;
972 }
973 }
974
ath_register_led(struct ath_softc * sc,struct ath_led * led,char * trigger)975 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
976 char *trigger)
977 {
978 int ret;
979
980 led->sc = sc;
981 led->led_cdev.name = led->name;
982 led->led_cdev.default_trigger = trigger;
983 led->led_cdev.brightness_set = ath_led_brightness;
984
985 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
986 if (ret)
987 DPRINTF(sc, ATH_DBG_FATAL,
988 "Failed to register led:%s", led->name);
989 else
990 led->registered = 1;
991 return ret;
992 }
993
ath_unregister_led(struct ath_led * led)994 static void ath_unregister_led(struct ath_led *led)
995 {
996 if (led->registered) {
997 led_classdev_unregister(&led->led_cdev);
998 led->registered = 0;
999 }
1000 }
1001
ath_deinit_leds(struct ath_softc * sc)1002 static void ath_deinit_leds(struct ath_softc *sc)
1003 {
1004 ath_unregister_led(&sc->assoc_led);
1005 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1006 ath_unregister_led(&sc->tx_led);
1007 ath_unregister_led(&sc->rx_led);
1008 ath_unregister_led(&sc->radio_led);
1009 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1010 }
1011
ath_init_leds(struct ath_softc * sc)1012 static void ath_init_leds(struct ath_softc *sc)
1013 {
1014 char *trigger;
1015 int ret;
1016
1017 /* Configure gpio 1 for output */
1018 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1019 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1020 /* LED off, active low */
1021 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1022
1023 trigger = ieee80211_get_radio_led_name(sc->hw);
1024 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1025 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1026 ret = ath_register_led(sc, &sc->radio_led, trigger);
1027 sc->radio_led.led_type = ATH_LED_RADIO;
1028 if (ret)
1029 goto fail;
1030
1031 trigger = ieee80211_get_assoc_led_name(sc->hw);
1032 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1033 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1034 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1035 sc->assoc_led.led_type = ATH_LED_ASSOC;
1036 if (ret)
1037 goto fail;
1038
1039 trigger = ieee80211_get_tx_led_name(sc->hw);
1040 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1041 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1042 ret = ath_register_led(sc, &sc->tx_led, trigger);
1043 sc->tx_led.led_type = ATH_LED_TX;
1044 if (ret)
1045 goto fail;
1046
1047 trigger = ieee80211_get_rx_led_name(sc->hw);
1048 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1049 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1050 ret = ath_register_led(sc, &sc->rx_led, trigger);
1051 sc->rx_led.led_type = ATH_LED_RX;
1052 if (ret)
1053 goto fail;
1054
1055 return;
1056
1057 fail:
1058 ath_deinit_leds(sc);
1059 }
1060
1061 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1062
1063 /*******************/
1064 /* Rfkill */
1065 /*******************/
1066
ath_radio_enable(struct ath_softc * sc)1067 static void ath_radio_enable(struct ath_softc *sc)
1068 {
1069 struct ath_hal *ah = sc->sc_ah;
1070 int status;
1071
1072 spin_lock_bh(&sc->sc_resetlock);
1073 if (!ath9k_hw_reset(ah, ah->ah_curchan,
1074 sc->tx_chan_width,
1075 sc->sc_tx_chainmask,
1076 sc->sc_rx_chainmask,
1077 sc->sc_ht_extprotspacing,
1078 false, &status)) {
1079 DPRINTF(sc, ATH_DBG_FATAL,
1080 "Unable to reset channel %u (%uMhz) "
1081 "flags 0x%x hal status %u\n",
1082 ath9k_hw_mhz2ieee(ah,
1083 ah->ah_curchan->channel,
1084 ah->ah_curchan->channelFlags),
1085 ah->ah_curchan->channel,
1086 ah->ah_curchan->channelFlags, status);
1087 }
1088 spin_unlock_bh(&sc->sc_resetlock);
1089
1090 ath_update_txpow(sc);
1091 if (ath_startrecv(sc) != 0) {
1092 DPRINTF(sc, ATH_DBG_FATAL,
1093 "Unable to restart recv logic\n");
1094 return;
1095 }
1096
1097 if (sc->sc_flags & SC_OP_BEACONS)
1098 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1099
1100 /* Re-Enable interrupts */
1101 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1102
1103 /* Enable LED */
1104 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1105 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1106 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1107
1108 ieee80211_wake_queues(sc->hw);
1109 }
1110
ath_radio_disable(struct ath_softc * sc)1111 static void ath_radio_disable(struct ath_softc *sc)
1112 {
1113 struct ath_hal *ah = sc->sc_ah;
1114 int status;
1115
1116
1117 ieee80211_stop_queues(sc->hw);
1118
1119 /* Disable LED */
1120 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1121 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1122
1123 /* Disable interrupts */
1124 ath9k_hw_set_interrupts(ah, 0);
1125
1126 ath_draintxq(sc, false); /* clear pending tx frames */
1127 ath_stoprecv(sc); /* turn off frame recv */
1128 ath_flushrecv(sc); /* flush recv queue */
1129
1130 spin_lock_bh(&sc->sc_resetlock);
1131 if (!ath9k_hw_reset(ah, ah->ah_curchan,
1132 sc->tx_chan_width,
1133 sc->sc_tx_chainmask,
1134 sc->sc_rx_chainmask,
1135 sc->sc_ht_extprotspacing,
1136 false, &status)) {
1137 DPRINTF(sc, ATH_DBG_FATAL,
1138 "Unable to reset channel %u (%uMhz) "
1139 "flags 0x%x hal status %u\n",
1140 ath9k_hw_mhz2ieee(ah,
1141 ah->ah_curchan->channel,
1142 ah->ah_curchan->channelFlags),
1143 ah->ah_curchan->channel,
1144 ah->ah_curchan->channelFlags, status);
1145 }
1146 spin_unlock_bh(&sc->sc_resetlock);
1147
1148 ath9k_hw_phy_disable(ah);
1149 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1150 }
1151
ath_is_rfkill_set(struct ath_softc * sc)1152 static bool ath_is_rfkill_set(struct ath_softc *sc)
1153 {
1154 struct ath_hal *ah = sc->sc_ah;
1155
1156 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1157 ah->ah_rfkill_polarity;
1158 }
1159
1160 /* h/w rfkill poll function */
ath_rfkill_poll(struct work_struct * work)1161 static void ath_rfkill_poll(struct work_struct *work)
1162 {
1163 struct ath_softc *sc = container_of(work, struct ath_softc,
1164 rf_kill.rfkill_poll.work);
1165 bool radio_on;
1166
1167 if (sc->sc_flags & SC_OP_INVALID)
1168 return;
1169
1170 radio_on = !ath_is_rfkill_set(sc);
1171
1172 /*
1173 * enable/disable radio only when there is a
1174 * state change in RF switch
1175 */
1176 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1177 enum rfkill_state state;
1178
1179 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1180 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1181 : RFKILL_STATE_HARD_BLOCKED;
1182 } else if (radio_on) {
1183 ath_radio_enable(sc);
1184 state = RFKILL_STATE_UNBLOCKED;
1185 } else {
1186 ath_radio_disable(sc);
1187 state = RFKILL_STATE_HARD_BLOCKED;
1188 }
1189
1190 if (state == RFKILL_STATE_HARD_BLOCKED)
1191 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1192 else
1193 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1194
1195 rfkill_force_state(sc->rf_kill.rfkill, state);
1196 }
1197
1198 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1199 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1200 }
1201
1202 /* s/w rfkill handler */
ath_sw_toggle_radio(void * data,enum rfkill_state state)1203 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1204 {
1205 struct ath_softc *sc = data;
1206
1207 switch (state) {
1208 case RFKILL_STATE_SOFT_BLOCKED:
1209 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1210 SC_OP_RFKILL_SW_BLOCKED)))
1211 ath_radio_disable(sc);
1212 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1213 return 0;
1214 case RFKILL_STATE_UNBLOCKED:
1215 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1216 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1217 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1218 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1219 "radio as it is disabled by h/w\n");
1220 return -EPERM;
1221 }
1222 ath_radio_enable(sc);
1223 }
1224 return 0;
1225 default:
1226 return -EINVAL;
1227 }
1228 }
1229
1230 /* Init s/w rfkill */
ath_init_sw_rfkill(struct ath_softc * sc)1231 static int ath_init_sw_rfkill(struct ath_softc *sc)
1232 {
1233 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1234 RFKILL_TYPE_WLAN);
1235 if (!sc->rf_kill.rfkill) {
1236 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1237 return -ENOMEM;
1238 }
1239
1240 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1241 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1242 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1243 sc->rf_kill.rfkill->data = sc;
1244 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1245 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1246 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1247
1248 return 0;
1249 }
1250
1251 /* Deinitialize rfkill */
ath_deinit_rfkill(struct ath_softc * sc)1252 static void ath_deinit_rfkill(struct ath_softc *sc)
1253 {
1254 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1255 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1256
1257 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1258 rfkill_unregister(sc->rf_kill.rfkill);
1259 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1260 sc->rf_kill.rfkill = NULL;
1261 }
1262 }
1263
ath_start_rfkill_poll(struct ath_softc * sc)1264 static int ath_start_rfkill_poll(struct ath_softc *sc)
1265 {
1266 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1267 queue_delayed_work(sc->hw->workqueue,
1268 &sc->rf_kill.rfkill_poll, 0);
1269
1270 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1271 if (rfkill_register(sc->rf_kill.rfkill)) {
1272 DPRINTF(sc, ATH_DBG_FATAL,
1273 "Unable to register rfkill\n");
1274 rfkill_free(sc->rf_kill.rfkill);
1275
1276 /* Deinitialize the device */
1277 ath_detach(sc);
1278 if (sc->pdev->irq)
1279 free_irq(sc->pdev->irq, sc);
1280 pci_iounmap(sc->pdev, sc->mem);
1281 pci_release_region(sc->pdev, 0);
1282 pci_disable_device(sc->pdev);
1283 ieee80211_free_hw(sc->hw);
1284 return -EIO;
1285 } else {
1286 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1287 }
1288 }
1289
1290 return 0;
1291 }
1292 #endif /* CONFIG_RFKILL */
1293
ath_detach(struct ath_softc * sc)1294 static void ath_detach(struct ath_softc *sc)
1295 {
1296 struct ieee80211_hw *hw = sc->hw;
1297 int i = 0;
1298
1299 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1300
1301 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1302 ath_deinit_rfkill(sc);
1303 #endif
1304 ath_deinit_leds(sc);
1305
1306 ieee80211_unregister_hw(hw);
1307 ath_rx_cleanup(sc);
1308 ath_tx_cleanup(sc);
1309
1310 tasklet_kill(&sc->intr_tq);
1311 tasklet_kill(&sc->bcon_tasklet);
1312
1313 if (!(sc->sc_flags & SC_OP_INVALID))
1314 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1315
1316 /* cleanup tx queues */
1317 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1318 if (ATH_TXQ_SETUP(sc, i))
1319 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1320
1321 ath9k_hw_detach(sc->sc_ah);
1322 ath9k_exit_debug(sc);
1323 }
1324
ath_init(u16 devid,struct ath_softc * sc)1325 static int ath_init(u16 devid, struct ath_softc *sc)
1326 {
1327 struct ath_hal *ah = NULL;
1328 int status;
1329 int error = 0, i;
1330 int csz = 0;
1331
1332 /* XXX: hardware will not be ready until ath_open() being called */
1333 sc->sc_flags |= SC_OP_INVALID;
1334
1335 if (ath9k_init_debug(sc) < 0)
1336 printk(KERN_ERR "Unable to create debugfs files\n");
1337
1338 spin_lock_init(&sc->sc_resetlock);
1339 spin_lock_init(&sc->sc_serial_rw);
1340 mutex_init(&sc->mutex);
1341 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1342 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1343 (unsigned long)sc);
1344
1345 /*
1346 * Cache line size is used to size and align various
1347 * structures used to communicate with the hardware.
1348 */
1349 bus_read_cachesize(sc, &csz);
1350 /* XXX assert csz is non-zero */
1351 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1352
1353 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1354 if (ah == NULL) {
1355 DPRINTF(sc, ATH_DBG_FATAL,
1356 "Unable to attach hardware; HAL status %u\n", status);
1357 error = -ENXIO;
1358 goto bad;
1359 }
1360 sc->sc_ah = ah;
1361
1362 /* Get the hardware key cache size. */
1363 sc->sc_keymax = ah->ah_caps.keycache_size;
1364 if (sc->sc_keymax > ATH_KEYMAX) {
1365 DPRINTF(sc, ATH_DBG_KEYCACHE,
1366 "Warning, using only %u entries in %u key cache\n",
1367 ATH_KEYMAX, sc->sc_keymax);
1368 sc->sc_keymax = ATH_KEYMAX;
1369 }
1370
1371 /*
1372 * Reset the key cache since some parts do not
1373 * reset the contents on initial power up.
1374 */
1375 for (i = 0; i < sc->sc_keymax; i++)
1376 ath9k_hw_keyreset(ah, (u16) i);
1377
1378 /* Collect the channel list using the default country code */
1379
1380 error = ath_setup_channels(sc);
1381 if (error)
1382 goto bad;
1383
1384 /* default to MONITOR mode */
1385 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1386
1387
1388 /* Setup rate tables */
1389
1390 ath_rate_attach(sc);
1391 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1392 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1393
1394 /*
1395 * Allocate hardware transmit queues: one queue for
1396 * beacon frames and one data queue for each QoS
1397 * priority. Note that the hal handles reseting
1398 * these queues at the needed time.
1399 */
1400 sc->beacon.beaconq = ath_beaconq_setup(ah);
1401 if (sc->beacon.beaconq == -1) {
1402 DPRINTF(sc, ATH_DBG_FATAL,
1403 "Unable to setup a beacon xmit queue\n");
1404 error = -EIO;
1405 goto bad2;
1406 }
1407 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1408 if (sc->beacon.cabq == NULL) {
1409 DPRINTF(sc, ATH_DBG_FATAL,
1410 "Unable to setup CAB xmit queue\n");
1411 error = -EIO;
1412 goto bad2;
1413 }
1414
1415 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1416 ath_cabq_update(sc);
1417
1418 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1419 sc->tx.hwq_map[i] = -1;
1420
1421 /* Setup data queues */
1422 /* NB: ensure BK queue is the lowest priority h/w queue */
1423 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1424 DPRINTF(sc, ATH_DBG_FATAL,
1425 "Unable to setup xmit queue for BK traffic\n");
1426 error = -EIO;
1427 goto bad2;
1428 }
1429
1430 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1431 DPRINTF(sc, ATH_DBG_FATAL,
1432 "Unable to setup xmit queue for BE traffic\n");
1433 error = -EIO;
1434 goto bad2;
1435 }
1436 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1437 DPRINTF(sc, ATH_DBG_FATAL,
1438 "Unable to setup xmit queue for VI traffic\n");
1439 error = -EIO;
1440 goto bad2;
1441 }
1442 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1443 DPRINTF(sc, ATH_DBG_FATAL,
1444 "Unable to setup xmit queue for VO traffic\n");
1445 error = -EIO;
1446 goto bad2;
1447 }
1448
1449 /* Initializes the noise floor to a reasonable default value.
1450 * Later on this will be updated during ANI processing. */
1451
1452 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1453 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1454
1455 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1456 ATH9K_CIPHER_TKIP, NULL)) {
1457 /*
1458 * Whether we should enable h/w TKIP MIC.
1459 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1460 * report WMM capable, so it's always safe to turn on
1461 * TKIP MIC in this case.
1462 */
1463 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1464 0, 1, NULL);
1465 }
1466
1467 /*
1468 * Check whether the separate key cache entries
1469 * are required to handle both tx+rx MIC keys.
1470 * With split mic keys the number of stations is limited
1471 * to 27 otherwise 59.
1472 */
1473 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1474 ATH9K_CIPHER_TKIP, NULL)
1475 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1476 ATH9K_CIPHER_MIC, NULL)
1477 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1478 0, NULL))
1479 sc->sc_splitmic = 1;
1480
1481 /* turn on mcast key search if possible */
1482 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1483 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1484 1, NULL);
1485
1486 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1487 sc->sc_config.txpowlimit_override = 0;
1488
1489 /* 11n Capabilities */
1490 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1491 sc->sc_flags |= SC_OP_TXAGGR;
1492 sc->sc_flags |= SC_OP_RXAGGR;
1493 }
1494
1495 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1496 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1497
1498 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1499 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1500
1501 ath9k_hw_getmac(ah, sc->sc_myaddr);
1502 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1503 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1504 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1505 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1506 }
1507
1508 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1509
1510 /* initialize beacon slots */
1511 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1512 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1513
1514 /* save MISC configurations */
1515 sc->sc_config.swBeaconProcess = 1;
1516
1517 /* setup channels and rates */
1518
1519 sc->sbands[IEEE80211_BAND_2GHZ].channels =
1520 sc->channels[IEEE80211_BAND_2GHZ];
1521 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1522 sc->rates[IEEE80211_BAND_2GHZ];
1523 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1524
1525 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1526 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1527 sc->channels[IEEE80211_BAND_5GHZ];
1528 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1529 sc->rates[IEEE80211_BAND_5GHZ];
1530 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1531 }
1532
1533 return 0;
1534 bad2:
1535 /* cleanup tx queues */
1536 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1537 if (ATH_TXQ_SETUP(sc, i))
1538 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1539 bad:
1540 if (ah)
1541 ath9k_hw_detach(ah);
1542 ath9k_exit_debug(sc);
1543
1544 return error;
1545 }
1546
ath_attach(u16 devid,struct ath_softc * sc)1547 static int ath_attach(u16 devid, struct ath_softc *sc)
1548 {
1549 struct ieee80211_hw *hw = sc->hw;
1550 int error = 0, i;
1551
1552 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1553
1554 error = ath_init(devid, sc);
1555 if (error != 0)
1556 return error;
1557
1558 /* get mac address from hardware and set in mac80211 */
1559
1560 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1561
1562 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1563 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1564 IEEE80211_HW_SIGNAL_DBM |
1565 IEEE80211_HW_AMPDU_AGGREGATION;
1566
1567 hw->wiphy->interface_modes =
1568 BIT(NL80211_IFTYPE_AP) |
1569 BIT(NL80211_IFTYPE_STATION) |
1570 BIT(NL80211_IFTYPE_ADHOC);
1571
1572 hw->queues = 4;
1573 hw->max_rates = 4;
1574 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1575 hw->sta_data_size = sizeof(struct ath_node);
1576 hw->vif_data_size = sizeof(struct ath_vap);
1577
1578 hw->rate_control_algorithm = "ath9k_rate_control";
1579
1580 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1581 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1582 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1583 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1584 }
1585
1586 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1587 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1588 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1589 &sc->sbands[IEEE80211_BAND_5GHZ];
1590
1591 /* initialize tx/rx engine */
1592 error = ath_tx_init(sc, ATH_TXBUF);
1593 if (error != 0)
1594 goto error_attach;
1595
1596 error = ath_rx_init(sc, ATH_RXBUF);
1597 if (error != 0)
1598 goto error_attach;
1599
1600 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1601 /* Initialze h/w Rfkill */
1602 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1603 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1604
1605 /* Initialize s/w rfkill */
1606 error = ath_init_sw_rfkill(sc);
1607 if (error)
1608 goto error_attach;
1609 #endif
1610
1611 error = ieee80211_register_hw(hw);
1612
1613 /* Initialize LED control */
1614 ath_init_leds(sc);
1615
1616 return 0;
1617
1618 error_attach:
1619 /* cleanup tx queues */
1620 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1621 if (ATH_TXQ_SETUP(sc, i))
1622 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1623
1624 ath9k_hw_detach(sc->sc_ah);
1625 ath9k_exit_debug(sc);
1626
1627 return error;
1628 }
1629
ath_reset(struct ath_softc * sc,bool retry_tx)1630 int ath_reset(struct ath_softc *sc, bool retry_tx)
1631 {
1632 struct ath_hal *ah = sc->sc_ah;
1633 int status;
1634 int error = 0;
1635
1636 ath9k_hw_set_interrupts(ah, 0);
1637 ath_draintxq(sc, retry_tx);
1638 ath_stoprecv(sc);
1639 ath_flushrecv(sc);
1640
1641 spin_lock_bh(&sc->sc_resetlock);
1642 if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1643 sc->tx_chan_width,
1644 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1645 sc->sc_ht_extprotspacing, false, &status)) {
1646 DPRINTF(sc, ATH_DBG_FATAL,
1647 "Unable to reset hardware; hal status %u\n", status);
1648 error = -EIO;
1649 }
1650 spin_unlock_bh(&sc->sc_resetlock);
1651
1652 if (ath_startrecv(sc) != 0)
1653 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1654
1655 /*
1656 * We may be doing a reset in response to a request
1657 * that changes the channel so update any state that
1658 * might change as a result.
1659 */
1660 ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1661
1662 ath_update_txpow(sc);
1663
1664 if (sc->sc_flags & SC_OP_BEACONS)
1665 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1666
1667 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1668
1669 if (retry_tx) {
1670 int i;
1671 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1672 if (ATH_TXQ_SETUP(sc, i)) {
1673 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1674 ath_txq_schedule(sc, &sc->tx.txq[i]);
1675 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1676 }
1677 }
1678 }
1679
1680 return error;
1681 }
1682
1683 /*
1684 * This function will allocate both the DMA descriptor structure, and the
1685 * buffers it contains. These are used to contain the descriptors used
1686 * by the system.
1687 */
ath_descdma_setup(struct ath_softc * sc,struct ath_descdma * dd,struct list_head * head,const char * name,int nbuf,int ndesc)1688 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1689 struct list_head *head, const char *name,
1690 int nbuf, int ndesc)
1691 {
1692 #define DS2PHYS(_dd, _ds) \
1693 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1694 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1695 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1696
1697 struct ath_desc *ds;
1698 struct ath_buf *bf;
1699 int i, bsize, error;
1700
1701 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1702 name, nbuf, ndesc);
1703
1704 /* ath_desc must be a multiple of DWORDs */
1705 if ((sizeof(struct ath_desc) % 4) != 0) {
1706 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1707 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1708 error = -ENOMEM;
1709 goto fail;
1710 }
1711
1712 dd->dd_name = name;
1713 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1714
1715 /*
1716 * Need additional DMA memory because we can't use
1717 * descriptors that cross the 4K page boundary. Assume
1718 * one skipped descriptor per 4K page.
1719 */
1720 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1721 u32 ndesc_skipped =
1722 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1723 u32 dma_len;
1724
1725 while (ndesc_skipped) {
1726 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1727 dd->dd_desc_len += dma_len;
1728
1729 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1730 };
1731 }
1732
1733 /* allocate descriptors */
1734 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1735 dd->dd_desc_len,
1736 &dd->dd_desc_paddr);
1737 if (dd->dd_desc == NULL) {
1738 error = -ENOMEM;
1739 goto fail;
1740 }
1741 ds = dd->dd_desc;
1742 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1743 dd->dd_name, ds, (u32) dd->dd_desc_len,
1744 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1745
1746 /* allocate buffers */
1747 bsize = sizeof(struct ath_buf) * nbuf;
1748 bf = kmalloc(bsize, GFP_KERNEL);
1749 if (bf == NULL) {
1750 error = -ENOMEM;
1751 goto fail2;
1752 }
1753 memset(bf, 0, bsize);
1754 dd->dd_bufptr = bf;
1755
1756 INIT_LIST_HEAD(head);
1757 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1758 bf->bf_desc = ds;
1759 bf->bf_daddr = DS2PHYS(dd, ds);
1760
1761 if (!(sc->sc_ah->ah_caps.hw_caps &
1762 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1763 /*
1764 * Skip descriptor addresses which can cause 4KB
1765 * boundary crossing (addr + length) with a 32 dword
1766 * descriptor fetch.
1767 */
1768 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1769 ASSERT((caddr_t) bf->bf_desc <
1770 ((caddr_t) dd->dd_desc +
1771 dd->dd_desc_len));
1772
1773 ds += ndesc;
1774 bf->bf_desc = ds;
1775 bf->bf_daddr = DS2PHYS(dd, ds);
1776 }
1777 }
1778 list_add_tail(&bf->list, head);
1779 }
1780 return 0;
1781 fail2:
1782 pci_free_consistent(sc->pdev,
1783 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1784 fail:
1785 memset(dd, 0, sizeof(*dd));
1786 return error;
1787 #undef ATH_DESC_4KB_BOUND_CHECK
1788 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1789 #undef DS2PHYS
1790 }
1791
ath_descdma_cleanup(struct ath_softc * sc,struct ath_descdma * dd,struct list_head * head)1792 void ath_descdma_cleanup(struct ath_softc *sc,
1793 struct ath_descdma *dd,
1794 struct list_head *head)
1795 {
1796 pci_free_consistent(sc->pdev,
1797 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1798
1799 INIT_LIST_HEAD(head);
1800 kfree(dd->dd_bufptr);
1801 memset(dd, 0, sizeof(*dd));
1802 }
1803
ath_get_hal_qnum(u16 queue,struct ath_softc * sc)1804 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1805 {
1806 int qnum;
1807
1808 switch (queue) {
1809 case 0:
1810 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1811 break;
1812 case 1:
1813 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1814 break;
1815 case 2:
1816 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1817 break;
1818 case 3:
1819 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1820 break;
1821 default:
1822 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1823 break;
1824 }
1825
1826 return qnum;
1827 }
1828
ath_get_mac80211_qnum(u32 queue,struct ath_softc * sc)1829 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1830 {
1831 int qnum;
1832
1833 switch (queue) {
1834 case ATH9K_WME_AC_VO:
1835 qnum = 0;
1836 break;
1837 case ATH9K_WME_AC_VI:
1838 qnum = 1;
1839 break;
1840 case ATH9K_WME_AC_BE:
1841 qnum = 2;
1842 break;
1843 case ATH9K_WME_AC_BK:
1844 qnum = 3;
1845 break;
1846 default:
1847 qnum = -1;
1848 break;
1849 }
1850
1851 return qnum;
1852 }
1853
1854 /**********************/
1855 /* mac80211 callbacks */
1856 /**********************/
1857
ath9k_start(struct ieee80211_hw * hw)1858 static int ath9k_start(struct ieee80211_hw *hw)
1859 {
1860 struct ath_softc *sc = hw->priv;
1861 struct ieee80211_channel *curchan = hw->conf.channel;
1862 struct ath9k_channel *init_channel;
1863 int error = 0, pos, status;
1864
1865 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1866 "initial channel: %d MHz\n", curchan->center_freq);
1867
1868 /* setup initial channel */
1869
1870 pos = ath_get_channel(sc, curchan);
1871 if (pos == -1) {
1872 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1873 error = -EINVAL;
1874 goto error;
1875 }
1876
1877 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1878 sc->sc_ah->ah_channels[pos].chanmode =
1879 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1880 init_channel = &sc->sc_ah->ah_channels[pos];
1881
1882 /* Reset SERDES registers */
1883 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1884
1885 /*
1886 * The basic interface to setting the hardware in a good
1887 * state is ``reset''. On return the hardware is known to
1888 * be powered up and with interrupts disabled. This must
1889 * be followed by initialization of the appropriate bits
1890 * and then setup of the interrupt mask.
1891 */
1892 spin_lock_bh(&sc->sc_resetlock);
1893 if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1894 sc->tx_chan_width,
1895 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1896 sc->sc_ht_extprotspacing, false, &status)) {
1897 DPRINTF(sc, ATH_DBG_FATAL,
1898 "Unable to reset hardware; hal status %u "
1899 "(freq %u flags 0x%x)\n", status,
1900 init_channel->channel, init_channel->channelFlags);
1901 error = -EIO;
1902 spin_unlock_bh(&sc->sc_resetlock);
1903 goto error;
1904 }
1905 spin_unlock_bh(&sc->sc_resetlock);
1906
1907 /*
1908 * This is needed only to setup initial state
1909 * but it's best done after a reset.
1910 */
1911 ath_update_txpow(sc);
1912
1913 /*
1914 * Setup the hardware after reset:
1915 * The receive engine is set going.
1916 * Frame transmit is handled entirely
1917 * in the frame output path; there's nothing to do
1918 * here except setup the interrupt mask.
1919 */
1920 if (ath_startrecv(sc) != 0) {
1921 DPRINTF(sc, ATH_DBG_FATAL,
1922 "Unable to start recv logic\n");
1923 error = -EIO;
1924 goto error;
1925 }
1926
1927 /* Setup our intr mask. */
1928 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1929 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1930 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1931
1932 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1933 sc->sc_imask |= ATH9K_INT_GTT;
1934
1935 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1936 sc->sc_imask |= ATH9K_INT_CST;
1937
1938 /*
1939 * Enable MIB interrupts when there are hardware phy counters.
1940 * Note we only do this (at the moment) for station mode.
1941 */
1942 if (ath9k_hw_phycounters(sc->sc_ah) &&
1943 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1944 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1945 sc->sc_imask |= ATH9K_INT_MIB;
1946 /*
1947 * Some hardware processes the TIM IE and fires an
1948 * interrupt when the TIM bit is set. For hardware
1949 * that does, if not overridden by configuration,
1950 * enable the TIM interrupt when operating as station.
1951 */
1952 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1953 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1954 !sc->sc_config.swBeaconProcess)
1955 sc->sc_imask |= ATH9K_INT_TIM;
1956
1957 ath_setcurmode(sc, ath_chan2mode(init_channel));
1958
1959 sc->sc_flags &= ~SC_OP_INVALID;
1960
1961 /* Disable BMISS interrupt when we're not associated */
1962 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1963 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1964
1965 ieee80211_wake_queues(sc->hw);
1966
1967 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1968 error = ath_start_rfkill_poll(sc);
1969 #endif
1970
1971 error:
1972 return error;
1973 }
1974
ath9k_tx(struct ieee80211_hw * hw,struct sk_buff * skb)1975 static int ath9k_tx(struct ieee80211_hw *hw,
1976 struct sk_buff *skb)
1977 {
1978 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1979 struct ath_softc *sc = hw->priv;
1980 struct ath_tx_control txctl;
1981 int hdrlen, padsize;
1982
1983 memset(&txctl, 0, sizeof(struct ath_tx_control));
1984
1985 /*
1986 * As a temporary workaround, assign seq# here; this will likely need
1987 * to be cleaned up to work better with Beacon transmission and virtual
1988 * BSSes.
1989 */
1990 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1991 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1992 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1993 sc->tx.seq_no += 0x10;
1994 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1995 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1996 }
1997
1998 /* Add the padding after the header if this is not already done */
1999 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2000 if (hdrlen & 3) {
2001 padsize = hdrlen % 4;
2002 if (skb_headroom(skb) < padsize)
2003 return -1;
2004 skb_push(skb, padsize);
2005 memmove(skb->data, skb->data + padsize, hdrlen);
2006 }
2007
2008 /* Check if a tx queue is available */
2009
2010 txctl.txq = ath_test_get_txq(sc, skb);
2011 if (!txctl.txq)
2012 goto exit;
2013
2014 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2015
2016 if (ath_tx_start(sc, skb, &txctl) != 0) {
2017 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2018 goto exit;
2019 }
2020
2021 return 0;
2022 exit:
2023 dev_kfree_skb_any(skb);
2024 return 0;
2025 }
2026
ath9k_stop(struct ieee80211_hw * hw)2027 static void ath9k_stop(struct ieee80211_hw *hw)
2028 {
2029 struct ath_softc *sc = hw->priv;
2030
2031 if (sc->sc_flags & SC_OP_INVALID) {
2032 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2033 return;
2034 }
2035
2036 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2037
2038 ieee80211_stop_queues(sc->hw);
2039
2040 /* make sure h/w will not generate any interrupt
2041 * before setting the invalid flag. */
2042 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2043
2044 if (!(sc->sc_flags & SC_OP_INVALID)) {
2045 ath_draintxq(sc, false);
2046 ath_stoprecv(sc);
2047 ath9k_hw_phy_disable(sc->sc_ah);
2048 } else
2049 sc->rx.rxlink = NULL;
2050
2051 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2052 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2053 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2054 #endif
2055 /* disable HAL and put h/w to sleep */
2056 ath9k_hw_disable(sc->sc_ah);
2057 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2058
2059 sc->sc_flags |= SC_OP_INVALID;
2060
2061 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2062 }
2063
ath9k_add_interface(struct ieee80211_hw * hw,struct ieee80211_if_init_conf * conf)2064 static int ath9k_add_interface(struct ieee80211_hw *hw,
2065 struct ieee80211_if_init_conf *conf)
2066 {
2067 struct ath_softc *sc = hw->priv;
2068 struct ath_vap *avp = (void *)conf->vif->drv_priv;
2069 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2070
2071 /* Support only vap for now */
2072
2073 if (sc->sc_nvaps)
2074 return -ENOBUFS;
2075
2076 switch (conf->type) {
2077 case NL80211_IFTYPE_STATION:
2078 ic_opmode = NL80211_IFTYPE_STATION;
2079 break;
2080 case NL80211_IFTYPE_ADHOC:
2081 ic_opmode = NL80211_IFTYPE_ADHOC;
2082 break;
2083 case NL80211_IFTYPE_AP:
2084 ic_opmode = NL80211_IFTYPE_AP;
2085 break;
2086 default:
2087 DPRINTF(sc, ATH_DBG_FATAL,
2088 "Interface type %d not yet supported\n", conf->type);
2089 return -EOPNOTSUPP;
2090 }
2091
2092 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2093
2094 /* Set the VAP opmode */
2095 avp->av_opmode = ic_opmode;
2096 avp->av_bslot = -1;
2097
2098 if (ic_opmode == NL80211_IFTYPE_AP)
2099 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2100
2101 sc->sc_vaps[0] = conf->vif;
2102 sc->sc_nvaps++;
2103
2104 /* Set the device opmode */
2105 sc->sc_ah->ah_opmode = ic_opmode;
2106
2107 if (conf->type == NL80211_IFTYPE_AP) {
2108 /* TODO: is this a suitable place to start ANI for AP mode? */
2109 /* Start ANI */
2110 mod_timer(&sc->sc_ani.timer,
2111 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2112 }
2113
2114 return 0;
2115 }
2116
ath9k_remove_interface(struct ieee80211_hw * hw,struct ieee80211_if_init_conf * conf)2117 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2118 struct ieee80211_if_init_conf *conf)
2119 {
2120 struct ath_softc *sc = hw->priv;
2121 struct ath_vap *avp = (void *)conf->vif->drv_priv;
2122
2123 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2124
2125 /* Stop ANI */
2126 del_timer_sync(&sc->sc_ani.timer);
2127
2128 /* Reclaim beacon resources */
2129 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2130 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2131 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2132 ath_beacon_return(sc, avp);
2133 }
2134
2135 sc->sc_flags &= ~SC_OP_BEACONS;
2136
2137 sc->sc_vaps[0] = NULL;
2138 sc->sc_nvaps--;
2139 }
2140
ath9k_config(struct ieee80211_hw * hw,u32 changed)2141 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2142 {
2143 struct ath_softc *sc = hw->priv;
2144 struct ieee80211_conf *conf = &hw->conf;
2145
2146 mutex_lock(&sc->mutex);
2147 if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
2148 IEEE80211_CONF_CHANGE_HT)) {
2149 struct ieee80211_channel *curchan = hw->conf.channel;
2150 int pos;
2151
2152 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2153 curchan->center_freq);
2154
2155 pos = ath_get_channel(sc, curchan);
2156 if (pos == -1) {
2157 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2158 curchan->center_freq);
2159 mutex_unlock(&sc->mutex);
2160 return -EINVAL;
2161 }
2162
2163 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2164 sc->sc_ah->ah_channels[pos].chanmode =
2165 (curchan->band == IEEE80211_BAND_2GHZ) ?
2166 CHANNEL_G : CHANNEL_A;
2167
2168 if (conf->ht.enabled) {
2169 if (conf->ht.channel_type == NL80211_CHAN_HT40PLUS ||
2170 conf->ht.channel_type == NL80211_CHAN_HT40MINUS)
2171 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2172
2173 sc->sc_ah->ah_channels[pos].chanmode =
2174 ath_get_extchanmode(sc, curchan,
2175 conf->ht.channel_type);
2176 }
2177
2178 ath_update_chainmask(sc, conf->ht.enabled);
2179
2180 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2181 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2182 mutex_unlock(&sc->mutex);
2183 return -EINVAL;
2184 }
2185 }
2186
2187 if (changed & IEEE80211_CONF_CHANGE_POWER)
2188 sc->sc_config.txpowlimit = 2 * conf->power_level;
2189
2190 mutex_unlock(&sc->mutex);
2191 return 0;
2192 }
2193
ath9k_config_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_if_conf * conf)2194 static int ath9k_config_interface(struct ieee80211_hw *hw,
2195 struct ieee80211_vif *vif,
2196 struct ieee80211_if_conf *conf)
2197 {
2198 struct ath_softc *sc = hw->priv;
2199 struct ath_hal *ah = sc->sc_ah;
2200 struct ath_vap *avp = (void *)vif->drv_priv;
2201 u32 rfilt = 0;
2202 int error, i;
2203
2204 /* TODO: Need to decide which hw opmode to use for multi-interface
2205 * cases */
2206 if (vif->type == NL80211_IFTYPE_AP &&
2207 ah->ah_opmode != NL80211_IFTYPE_AP) {
2208 ah->ah_opmode = NL80211_IFTYPE_STATION;
2209 ath9k_hw_setopmode(ah);
2210 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2211 /* Request full reset to get hw opmode changed properly */
2212 sc->sc_flags |= SC_OP_FULL_RESET;
2213 }
2214
2215 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2216 !is_zero_ether_addr(conf->bssid)) {
2217 switch (vif->type) {
2218 case NL80211_IFTYPE_STATION:
2219 case NL80211_IFTYPE_ADHOC:
2220 /* Set BSSID */
2221 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2222 sc->sc_curaid = 0;
2223 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2224 sc->sc_curaid);
2225
2226 /* Set aggregation protection mode parameters */
2227 sc->sc_config.ath_aggr_prot = 0;
2228
2229 DPRINTF(sc, ATH_DBG_CONFIG,
2230 "RX filter 0x%x bssid %pM aid 0x%x\n",
2231 rfilt, sc->sc_curbssid, sc->sc_curaid);
2232
2233 /* need to reconfigure the beacon */
2234 sc->sc_flags &= ~SC_OP_BEACONS ;
2235
2236 break;
2237 default:
2238 break;
2239 }
2240 }
2241
2242 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2243 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2244 (vif->type == NL80211_IFTYPE_AP))) {
2245 /*
2246 * Allocate and setup the beacon frame.
2247 *
2248 * Stop any previous beacon DMA. This may be
2249 * necessary, for example, when an ibss merge
2250 * causes reconfiguration; we may be called
2251 * with beacon transmission active.
2252 */
2253 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2254
2255 error = ath_beacon_alloc(sc, 0);
2256 if (error != 0)
2257 return error;
2258
2259 ath_beacon_sync(sc, 0);
2260 }
2261
2262 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2263 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2264 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2265 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2266 ath9k_hw_keysetmac(sc->sc_ah,
2267 (u16)i,
2268 sc->sc_curbssid);
2269 }
2270
2271 /* Only legacy IBSS for now */
2272 if (vif->type == NL80211_IFTYPE_ADHOC)
2273 ath_update_chainmask(sc, 0);
2274
2275 return 0;
2276 }
2277
2278 #define SUPPORTED_FILTERS \
2279 (FIF_PROMISC_IN_BSS | \
2280 FIF_ALLMULTI | \
2281 FIF_CONTROL | \
2282 FIF_OTHER_BSS | \
2283 FIF_BCN_PRBRESP_PROMISC | \
2284 FIF_FCSFAIL)
2285
2286 /* FIXME: sc->sc_full_reset ? */
ath9k_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,int mc_count,struct dev_mc_list * mclist)2287 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2288 unsigned int changed_flags,
2289 unsigned int *total_flags,
2290 int mc_count,
2291 struct dev_mc_list *mclist)
2292 {
2293 struct ath_softc *sc = hw->priv;
2294 u32 rfilt;
2295
2296 changed_flags &= SUPPORTED_FILTERS;
2297 *total_flags &= SUPPORTED_FILTERS;
2298
2299 sc->rx.rxfilter = *total_flags;
2300 rfilt = ath_calcrxfilter(sc);
2301 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2302
2303 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2304 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2305 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2306 }
2307
2308 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2309 }
2310
ath9k_sta_notify(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum sta_notify_cmd cmd,struct ieee80211_sta * sta)2311 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2312 struct ieee80211_vif *vif,
2313 enum sta_notify_cmd cmd,
2314 struct ieee80211_sta *sta)
2315 {
2316 struct ath_softc *sc = hw->priv;
2317
2318 switch (cmd) {
2319 case STA_NOTIFY_ADD:
2320 ath_node_attach(sc, sta);
2321 break;
2322 case STA_NOTIFY_REMOVE:
2323 ath_node_detach(sc, sta);
2324 break;
2325 default:
2326 break;
2327 }
2328 }
2329
ath9k_conf_tx(struct ieee80211_hw * hw,u16 queue,const struct ieee80211_tx_queue_params * params)2330 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2331 u16 queue,
2332 const struct ieee80211_tx_queue_params *params)
2333 {
2334 struct ath_softc *sc = hw->priv;
2335 struct ath9k_tx_queue_info qi;
2336 int ret = 0, qnum;
2337
2338 if (queue >= WME_NUM_AC)
2339 return 0;
2340
2341 qi.tqi_aifs = params->aifs;
2342 qi.tqi_cwmin = params->cw_min;
2343 qi.tqi_cwmax = params->cw_max;
2344 qi.tqi_burstTime = params->txop;
2345 qnum = ath_get_hal_qnum(queue, sc);
2346
2347 DPRINTF(sc, ATH_DBG_CONFIG,
2348 "Configure tx [queue/halq] [%d/%d], "
2349 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2350 queue, qnum, params->aifs, params->cw_min,
2351 params->cw_max, params->txop);
2352
2353 ret = ath_txq_update(sc, qnum, &qi);
2354 if (ret)
2355 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2356
2357 return ret;
2358 }
2359
ath9k_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,const u8 * local_addr,const u8 * addr,struct ieee80211_key_conf * key)2360 static int ath9k_set_key(struct ieee80211_hw *hw,
2361 enum set_key_cmd cmd,
2362 const u8 *local_addr,
2363 const u8 *addr,
2364 struct ieee80211_key_conf *key)
2365 {
2366 struct ath_softc *sc = hw->priv;
2367 int ret = 0;
2368
2369 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2370
2371 switch (cmd) {
2372 case SET_KEY:
2373 ret = ath_key_config(sc, addr, key);
2374 if (ret >= 0) {
2375 key->hw_key_idx = ret;
2376 /* push IV and Michael MIC generation to stack */
2377 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2378 if (key->alg == ALG_TKIP)
2379 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2380 ret = 0;
2381 }
2382 break;
2383 case DISABLE_KEY:
2384 ath_key_delete(sc, key);
2385 break;
2386 default:
2387 ret = -EINVAL;
2388 }
2389
2390 return ret;
2391 }
2392
ath9k_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u32 changed)2393 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2394 struct ieee80211_vif *vif,
2395 struct ieee80211_bss_conf *bss_conf,
2396 u32 changed)
2397 {
2398 struct ath_softc *sc = hw->priv;
2399
2400 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2401 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2402 bss_conf->use_short_preamble);
2403 if (bss_conf->use_short_preamble)
2404 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2405 else
2406 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2407 }
2408
2409 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2410 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2411 bss_conf->use_cts_prot);
2412 if (bss_conf->use_cts_prot &&
2413 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2414 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2415 else
2416 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2417 }
2418
2419 if (changed & BSS_CHANGED_ASSOC) {
2420 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2421 bss_conf->assoc);
2422 ath9k_bss_assoc_info(sc, vif, bss_conf);
2423 }
2424 }
2425
ath9k_get_tsf(struct ieee80211_hw * hw)2426 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2427 {
2428 u64 tsf;
2429 struct ath_softc *sc = hw->priv;
2430 struct ath_hal *ah = sc->sc_ah;
2431
2432 tsf = ath9k_hw_gettsf64(ah);
2433
2434 return tsf;
2435 }
2436
ath9k_reset_tsf(struct ieee80211_hw * hw)2437 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2438 {
2439 struct ath_softc *sc = hw->priv;
2440 struct ath_hal *ah = sc->sc_ah;
2441
2442 ath9k_hw_reset_tsf(ah);
2443 }
2444
ath9k_ampdu_action(struct ieee80211_hw * hw,enum ieee80211_ampdu_mlme_action action,struct ieee80211_sta * sta,u16 tid,u16 * ssn)2445 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2446 enum ieee80211_ampdu_mlme_action action,
2447 struct ieee80211_sta *sta,
2448 u16 tid, u16 *ssn)
2449 {
2450 struct ath_softc *sc = hw->priv;
2451 int ret = 0;
2452
2453 switch (action) {
2454 case IEEE80211_AMPDU_RX_START:
2455 if (!(sc->sc_flags & SC_OP_RXAGGR))
2456 ret = -ENOTSUPP;
2457 break;
2458 case IEEE80211_AMPDU_RX_STOP:
2459 break;
2460 case IEEE80211_AMPDU_TX_START:
2461 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2462 if (ret < 0)
2463 DPRINTF(sc, ATH_DBG_FATAL,
2464 "Unable to start TX aggregation\n");
2465 else
2466 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2467 break;
2468 case IEEE80211_AMPDU_TX_STOP:
2469 ret = ath_tx_aggr_stop(sc, sta, tid);
2470 if (ret < 0)
2471 DPRINTF(sc, ATH_DBG_FATAL,
2472 "Unable to stop TX aggregation\n");
2473
2474 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2475 break;
2476 case IEEE80211_AMPDU_TX_RESUME:
2477 ath_tx_aggr_resume(sc, sta, tid);
2478 break;
2479 default:
2480 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2481 }
2482
2483 return ret;
2484 }
2485
2486 static struct ieee80211_ops ath9k_ops = {
2487 .tx = ath9k_tx,
2488 .start = ath9k_start,
2489 .stop = ath9k_stop,
2490 .add_interface = ath9k_add_interface,
2491 .remove_interface = ath9k_remove_interface,
2492 .config = ath9k_config,
2493 .config_interface = ath9k_config_interface,
2494 .configure_filter = ath9k_configure_filter,
2495 .sta_notify = ath9k_sta_notify,
2496 .conf_tx = ath9k_conf_tx,
2497 .bss_info_changed = ath9k_bss_info_changed,
2498 .set_key = ath9k_set_key,
2499 .get_tsf = ath9k_get_tsf,
2500 .reset_tsf = ath9k_reset_tsf,
2501 .ampdu_action = ath9k_ampdu_action,
2502 };
2503
2504 static struct {
2505 u32 version;
2506 const char * name;
2507 } ath_mac_bb_names[] = {
2508 { AR_SREV_VERSION_5416_PCI, "5416" },
2509 { AR_SREV_VERSION_5416_PCIE, "5418" },
2510 { AR_SREV_VERSION_9100, "9100" },
2511 { AR_SREV_VERSION_9160, "9160" },
2512 { AR_SREV_VERSION_9280, "9280" },
2513 { AR_SREV_VERSION_9285, "9285" }
2514 };
2515
2516 static struct {
2517 u16 version;
2518 const char * name;
2519 } ath_rf_names[] = {
2520 { 0, "5133" },
2521 { AR_RAD5133_SREV_MAJOR, "5133" },
2522 { AR_RAD5122_SREV_MAJOR, "5122" },
2523 { AR_RAD2133_SREV_MAJOR, "2133" },
2524 { AR_RAD2122_SREV_MAJOR, "2122" }
2525 };
2526
2527 /*
2528 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2529 */
2530 static const char *
ath_mac_bb_name(u32 mac_bb_version)2531 ath_mac_bb_name(u32 mac_bb_version)
2532 {
2533 int i;
2534
2535 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2536 if (ath_mac_bb_names[i].version == mac_bb_version) {
2537 return ath_mac_bb_names[i].name;
2538 }
2539 }
2540
2541 return "????";
2542 }
2543
2544 /*
2545 * Return the RF name. "????" is returned if the RF is unknown.
2546 */
2547 static const char *
ath_rf_name(u16 rf_version)2548 ath_rf_name(u16 rf_version)
2549 {
2550 int i;
2551
2552 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2553 if (ath_rf_names[i].version == rf_version) {
2554 return ath_rf_names[i].name;
2555 }
2556 }
2557
2558 return "????";
2559 }
2560
ath_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2561 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2562 {
2563 void __iomem *mem;
2564 struct ath_softc *sc;
2565 struct ieee80211_hw *hw;
2566 u8 csz;
2567 u32 val;
2568 int ret = 0;
2569 struct ath_hal *ah;
2570
2571 if (pci_enable_device(pdev))
2572 return -EIO;
2573
2574 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2575
2576 if (ret) {
2577 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2578 goto bad;
2579 }
2580
2581 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2582
2583 if (ret) {
2584 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2585 "DMA enable failed\n");
2586 goto bad;
2587 }
2588
2589 /*
2590 * Cache line size is used to size and align various
2591 * structures used to communicate with the hardware.
2592 */
2593 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2594 if (csz == 0) {
2595 /*
2596 * Linux 2.4.18 (at least) writes the cache line size
2597 * register as a 16-bit wide register which is wrong.
2598 * We must have this setup properly for rx buffer
2599 * DMA to work so force a reasonable value here if it
2600 * comes up zero.
2601 */
2602 csz = L1_CACHE_BYTES / sizeof(u32);
2603 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2604 }
2605 /*
2606 * The default setting of latency timer yields poor results,
2607 * set it to the value used by other systems. It may be worth
2608 * tweaking this setting more.
2609 */
2610 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2611
2612 pci_set_master(pdev);
2613
2614 /*
2615 * Disable the RETRY_TIMEOUT register (0x41) to keep
2616 * PCI Tx retries from interfering with C3 CPU state.
2617 */
2618 pci_read_config_dword(pdev, 0x40, &val);
2619 if ((val & 0x0000ff00) != 0)
2620 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2621
2622 ret = pci_request_region(pdev, 0, "ath9k");
2623 if (ret) {
2624 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2625 ret = -ENODEV;
2626 goto bad;
2627 }
2628
2629 mem = pci_iomap(pdev, 0, 0);
2630 if (!mem) {
2631 printk(KERN_ERR "PCI memory map error\n") ;
2632 ret = -EIO;
2633 goto bad1;
2634 }
2635
2636 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2637 if (hw == NULL) {
2638 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2639 goto bad2;
2640 }
2641
2642 SET_IEEE80211_DEV(hw, &pdev->dev);
2643 pci_set_drvdata(pdev, hw);
2644
2645 sc = hw->priv;
2646 sc->hw = hw;
2647 sc->pdev = pdev;
2648 sc->mem = mem;
2649
2650 if (ath_attach(id->device, sc) != 0) {
2651 ret = -ENODEV;
2652 goto bad3;
2653 }
2654
2655 /* setup interrupt service routine */
2656
2657 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2658 printk(KERN_ERR "%s: request_irq failed\n",
2659 wiphy_name(hw->wiphy));
2660 ret = -EIO;
2661 goto bad4;
2662 }
2663
2664 ah = sc->sc_ah;
2665 printk(KERN_INFO
2666 "%s: Atheros AR%s MAC/BB Rev:%x "
2667 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2668 wiphy_name(hw->wiphy),
2669 ath_mac_bb_name(ah->ah_macVersion),
2670 ah->ah_macRev,
2671 ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2672 ah->ah_phyRev,
2673 (unsigned long)mem, pdev->irq);
2674
2675 return 0;
2676 bad4:
2677 ath_detach(sc);
2678 bad3:
2679 ieee80211_free_hw(hw);
2680 bad2:
2681 pci_iounmap(pdev, mem);
2682 bad1:
2683 pci_release_region(pdev, 0);
2684 bad:
2685 pci_disable_device(pdev);
2686 return ret;
2687 }
2688
ath_pci_remove(struct pci_dev * pdev)2689 static void ath_pci_remove(struct pci_dev *pdev)
2690 {
2691 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2692 struct ath_softc *sc = hw->priv;
2693
2694 ath_detach(sc);
2695 if (pdev->irq)
2696 free_irq(pdev->irq, sc);
2697 pci_iounmap(pdev, sc->mem);
2698 pci_release_region(pdev, 0);
2699 pci_disable_device(pdev);
2700 ieee80211_free_hw(hw);
2701 }
2702
2703 #ifdef CONFIG_PM
2704
ath_pci_suspend(struct pci_dev * pdev,pm_message_t state)2705 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2706 {
2707 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2708 struct ath_softc *sc = hw->priv;
2709
2710 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2711
2712 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2713 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2714 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2715 #endif
2716
2717 pci_save_state(pdev);
2718 pci_disable_device(pdev);
2719 pci_set_power_state(pdev, 3);
2720
2721 return 0;
2722 }
2723
ath_pci_resume(struct pci_dev * pdev)2724 static int ath_pci_resume(struct pci_dev *pdev)
2725 {
2726 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2727 struct ath_softc *sc = hw->priv;
2728 u32 val;
2729 int err;
2730
2731 err = pci_enable_device(pdev);
2732 if (err)
2733 return err;
2734 pci_restore_state(pdev);
2735 /*
2736 * Suspend/Resume resets the PCI configuration space, so we have to
2737 * re-disable the RETRY_TIMEOUT register (0x41) to keep
2738 * PCI Tx retries from interfering with C3 CPU state
2739 */
2740 pci_read_config_dword(pdev, 0x40, &val);
2741 if ((val & 0x0000ff00) != 0)
2742 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2743
2744 /* Enable LED */
2745 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2746 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2747 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2748
2749 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2750 /*
2751 * check the h/w rfkill state on resume
2752 * and start the rfkill poll timer
2753 */
2754 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2755 queue_delayed_work(sc->hw->workqueue,
2756 &sc->rf_kill.rfkill_poll, 0);
2757 #endif
2758
2759 return 0;
2760 }
2761
2762 #endif /* CONFIG_PM */
2763
2764 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2765
2766 static struct pci_driver ath_pci_driver = {
2767 .name = "ath9k",
2768 .id_table = ath_pci_id_table,
2769 .probe = ath_pci_probe,
2770 .remove = ath_pci_remove,
2771 #ifdef CONFIG_PM
2772 .suspend = ath_pci_suspend,
2773 .resume = ath_pci_resume,
2774 #endif /* CONFIG_PM */
2775 };
2776
init_ath_pci(void)2777 static int __init init_ath_pci(void)
2778 {
2779 int error;
2780
2781 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2782
2783 /* Register rate control algorithm */
2784 error = ath_rate_control_register();
2785 if (error != 0) {
2786 printk(KERN_ERR
2787 "Unable to register rate control algorithm: %d\n",
2788 error);
2789 ath_rate_control_unregister();
2790 return error;
2791 }
2792
2793 if (pci_register_driver(&ath_pci_driver) < 0) {
2794 printk(KERN_ERR
2795 "ath_pci: No devices found, driver not installed.\n");
2796 ath_rate_control_unregister();
2797 pci_unregister_driver(&ath_pci_driver);
2798 return -ENODEV;
2799 }
2800
2801 return 0;
2802 }
2803 module_init(init_ath_pci);
2804
exit_ath_pci(void)2805 static void __exit exit_ath_pci(void)
2806 {
2807 ath_rate_control_unregister();
2808 pci_unregister_driver(&ath_pci_driver);
2809 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2810 }
2811 module_exit(exit_ath_pci);
2812