1 #ifndef P54COMMON_H 2 #define P54COMMON_H 3 4 /* 5 * Common code specific definitions for mac80211 Prism54 drivers 6 * 7 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net> 8 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de> 9 * 10 * Based on: 11 * - the islsm (softmac prism54) driver, which is: 12 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al. 13 * 14 * - LMAC API interface header file for STLC4560 (lmac_longbow.h) 15 * Copyright (C) 2007 Conexant Systems, Inc. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 */ 21 22 struct bootrec { 23 __le32 code; 24 __le32 len; 25 u32 data[10]; 26 } __attribute__((packed)); 27 28 #define PDR_SYNTH_FRONTEND_MASK 0x0007 29 #define PDR_SYNTH_IQ_CAL_MASK 0x0018 30 #define PDR_SYNTH_IQ_CAL_PA_DETECTOR 0x0000 31 #define PDR_SYNTH_IQ_CAL_DISABLED 0x0008 32 #define PDR_SYNTH_IQ_CAL_ZIF 0x0010 33 #define PDR_SYNTH_FAA_SWITCH_MASK 0x0020 34 #define PDR_SYNTH_FAA_SWITCH_ENABLED 0x0001 35 #define PDR_SYNTH_24_GHZ_MASK 0x0040 36 #define PDR_SYNTH_24_GHZ_DISABLED 0x0040 37 #define PDR_SYNTH_5_GHZ_MASK 0x0080 38 #define PDR_SYNTH_5_GHZ_DISABLED 0x0080 39 #define PDR_SYNTH_RX_DIV_MASK 0x0100 40 #define PDR_SYNTH_RX_DIV_SUPPORTED 0x0100 41 #define PDR_SYNTH_TX_DIV_MASK 0x0200 42 #define PDR_SYNTH_TX_DIV_SUPPORTED 0x0200 43 44 struct bootrec_exp_if { 45 __le16 role; 46 __le16 if_id; 47 __le16 variant; 48 __le16 btm_compat; 49 __le16 top_compat; 50 } __attribute__((packed)); 51 52 #define BR_DESC_PRIV_CAP_WEP BIT(0) 53 #define BR_DESC_PRIV_CAP_TKIP BIT(1) 54 #define BR_DESC_PRIV_CAP_MICHAEL BIT(2) 55 #define BR_DESC_PRIV_CAP_CCX_CP BIT(3) 56 #define BR_DESC_PRIV_CAP_CCX_MIC BIT(4) 57 #define BR_DESC_PRIV_CAP_AESCCMP BIT(5) 58 59 struct bootrec_desc { 60 __le16 modes; 61 __le16 flags; 62 __le32 rx_start; 63 __le32 rx_end; 64 u8 headroom; 65 u8 tailroom; 66 u8 tx_queues; 67 u8 tx_depth; 68 u8 privacy_caps; 69 u8 rx_keycache_size; 70 u8 time_size; 71 u8 padding; 72 u8 rates[16]; 73 u8 padding2[4]; 74 __le16 rx_mtu; 75 } __attribute__((packed)); 76 77 #define BR_CODE_MIN 0x80000000 78 #define BR_CODE_COMPONENT_ID 0x80000001 79 #define BR_CODE_COMPONENT_VERSION 0x80000002 80 #define BR_CODE_DEPENDENT_IF 0x80000003 81 #define BR_CODE_EXPOSED_IF 0x80000004 82 #define BR_CODE_DESCR 0x80000101 83 #define BR_CODE_MAX 0x8FFFFFFF 84 #define BR_CODE_END_OF_BRA 0xFF0000FF 85 #define LEGACY_BR_CODE_END_OF_BRA 0xFFFFFFFF 86 87 #define P54_HDR_FLAG_DATA_ALIGN BIT(14) 88 #define P54_HDR_FLAG_DATA_OUT_PROMISC BIT(0) 89 #define P54_HDR_FLAG_DATA_OUT_TIMESTAMP BIT(1) 90 #define P54_HDR_FLAG_DATA_OUT_SEQNR BIT(2) 91 #define P54_HDR_FLAG_DATA_OUT_BIT3 BIT(3) 92 #define P54_HDR_FLAG_DATA_OUT_BURST BIT(4) 93 #define P54_HDR_FLAG_DATA_OUT_NOCANCEL BIT(5) 94 #define P54_HDR_FLAG_DATA_OUT_CLEARTIM BIT(6) 95 #define P54_HDR_FLAG_DATA_OUT_HITCHHIKE BIT(7) 96 #define P54_HDR_FLAG_DATA_OUT_COMPRESS BIT(8) 97 #define P54_HDR_FLAG_DATA_OUT_CONCAT BIT(9) 98 #define P54_HDR_FLAG_DATA_OUT_PCS_ACCEPT BIT(10) 99 #define P54_HDR_FLAG_DATA_OUT_WAITEOSP BIT(11) 100 101 #define P54_HDR_FLAG_DATA_IN_FCS_GOOD BIT(0) 102 #define P54_HDR_FLAG_DATA_IN_MATCH_MAC BIT(1) 103 #define P54_HDR_FLAG_DATA_IN_MCBC BIT(2) 104 #define P54_HDR_FLAG_DATA_IN_BEACON BIT(3) 105 #define P54_HDR_FLAG_DATA_IN_MATCH_BSS BIT(4) 106 #define P54_HDR_FLAG_DATA_IN_BCAST_BSS BIT(5) 107 #define P54_HDR_FLAG_DATA_IN_DATA BIT(6) 108 #define P54_HDR_FLAG_DATA_IN_TRUNCATED BIT(7) 109 #define P54_HDR_FLAG_DATA_IN_BIT8 BIT(8) 110 #define P54_HDR_FLAG_DATA_IN_TRANSPARENT BIT(9) 111 112 /* PDA defines are Copyright (C) 2005 Nokia Corporation (taken from islsm_pda.h) */ 113 114 struct pda_entry { 115 __le16 len; /* includes both code and data */ 116 __le16 code; 117 u8 data[0]; 118 } __attribute__ ((packed)); 119 120 struct eeprom_pda_wrap { 121 __le32 magic; 122 __le16 pad; 123 __le16 len; 124 __le32 arm_opcode; 125 u8 data[0]; 126 } __attribute__ ((packed)); 127 128 struct pda_iq_autocal_entry { 129 __le16 freq; 130 __le16 iq_param[4]; 131 } __attribute__ ((packed)); 132 133 struct pda_channel_output_limit { 134 __le16 freq; 135 u8 val_bpsk; 136 u8 val_qpsk; 137 u8 val_16qam; 138 u8 val_64qam; 139 u8 rate_set_mask; 140 u8 rate_set_size; 141 } __attribute__ ((packed)); 142 143 struct pda_pa_curve_data_sample_rev0 { 144 u8 rf_power; 145 u8 pa_detector; 146 u8 pcv; 147 } __attribute__ ((packed)); 148 149 struct pda_pa_curve_data_sample_rev1 { 150 u8 rf_power; 151 u8 pa_detector; 152 u8 data_barker; 153 u8 data_bpsk; 154 u8 data_qpsk; 155 u8 data_16qam; 156 u8 data_64qam; 157 } __attribute__ ((packed)); 158 159 struct p54_pa_curve_data_sample { 160 u8 rf_power; 161 u8 pa_detector; 162 u8 data_barker; 163 u8 data_bpsk; 164 u8 data_qpsk; 165 u8 data_16qam; 166 u8 data_64qam; 167 u8 padding; 168 } __attribute__ ((packed)); 169 170 struct pda_pa_curve_data { 171 u8 cal_method_rev; 172 u8 channels; 173 u8 points_per_channel; 174 u8 padding; 175 u8 data[0]; 176 } __attribute__ ((packed)); 177 178 struct pda_rssi_cal_entry { 179 __le16 mul; 180 __le16 add; 181 } __attribute__ ((packed)); 182 183 /* 184 * this defines the PDR codes used to build PDAs as defined in document 185 * number 553155. The current implementation mirrors version 1.1 of the 186 * document and lists only PDRs supported by the ARM platform. 187 */ 188 189 /* common and choice range (0x0000 - 0x0fff) */ 190 #define PDR_END 0x0000 191 #define PDR_MANUFACTURING_PART_NUMBER 0x0001 192 #define PDR_PDA_VERSION 0x0002 193 #define PDR_NIC_SERIAL_NUMBER 0x0003 194 195 #define PDR_MAC_ADDRESS 0x0101 196 #define PDR_REGULATORY_DOMAIN_LIST 0x0103 197 #define PDR_TEMPERATURE_TYPE 0x0107 198 199 #define PDR_PRISM_PCI_IDENTIFIER 0x0402 200 201 /* ARM range (0x1000 - 0x1fff) */ 202 #define PDR_COUNTRY_INFORMATION 0x1000 203 #define PDR_INTERFACE_LIST 0x1001 204 #define PDR_HARDWARE_PLATFORM_COMPONENT_ID 0x1002 205 #define PDR_OEM_NAME 0x1003 206 #define PDR_PRODUCT_NAME 0x1004 207 #define PDR_UTF8_OEM_NAME 0x1005 208 #define PDR_UTF8_PRODUCT_NAME 0x1006 209 #define PDR_COUNTRY_LIST 0x1007 210 #define PDR_DEFAULT_COUNTRY 0x1008 211 212 #define PDR_ANTENNA_GAIN 0x1100 213 214 #define PDR_PRISM_INDIGO_PA_CALIBRATION_DATA 0x1901 215 #define PDR_RSSI_LINEAR_APPROXIMATION 0x1902 216 #define PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS 0x1903 217 #define PDR_PRISM_PA_CAL_CURVE_DATA 0x1904 218 #define PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND 0x1905 219 #define PDR_PRISM_ZIF_TX_IQ_CALIBRATION 0x1906 220 #define PDR_REGULATORY_POWER_LIMITS 0x1907 221 #define PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED 0x1908 222 #define PDR_RADIATED_TRANSMISSION_CORRECTION 0x1909 223 #define PDR_PRISM_TX_IQ_CALIBRATION 0x190a 224 225 /* reserved range (0x2000 - 0x7fff) */ 226 227 /* customer range (0x8000 - 0xffff) */ 228 #define PDR_BASEBAND_REGISTERS 0x8000 229 #define PDR_PER_CHANNEL_BASEBAND_REGISTERS 0x8001 230 231 /* PDR definitions for default country & country list */ 232 #define PDR_COUNTRY_CERT_CODE 0x80 233 #define PDR_COUNTRY_CERT_CODE_REAL 0x00 234 #define PDR_COUNTRY_CERT_CODE_PSEUDO 0x80 235 #define PDR_COUNTRY_CERT_BAND 0x40 236 #define PDR_COUNTRY_CERT_BAND_2GHZ 0x00 237 #define PDR_COUNTRY_CERT_BAND_5GHZ 0x40 238 #define PDR_COUNTRY_CERT_IODOOR 0x30 239 #define PDR_COUNTRY_CERT_IODOOR_BOTH 0x00 240 #define PDR_COUNTRY_CERT_IODOOR_INDOOR 0x20 241 #define PDR_COUNTRY_CERT_IODOOR_OUTDOOR 0x30 242 #define PDR_COUNTRY_CERT_INDEX 0x0F 243 244 /* stored in skb->cb */ 245 struct memrecord { 246 u32 start_addr; 247 u32 end_addr; 248 }; 249 250 struct p54_eeprom_lm86 { 251 union { 252 struct { 253 __le16 offset; 254 __le16 len; 255 u8 data[0]; 256 } v1; 257 struct { 258 __le32 offset; 259 __le16 len; 260 u8 magic2; 261 u8 pad; 262 u8 magic[4]; 263 u8 data[0]; 264 } v2; 265 } __attribute__ ((packed)); 266 } __attribute__ ((packed)); 267 268 enum p54_rx_decrypt_status { 269 P54_DECRYPT_NONE = 0, 270 P54_DECRYPT_OK, 271 P54_DECRYPT_NOKEY, 272 P54_DECRYPT_NOMICHAEL, 273 P54_DECRYPT_NOCKIPMIC, 274 P54_DECRYPT_FAIL_WEP, 275 P54_DECRYPT_FAIL_TKIP, 276 P54_DECRYPT_FAIL_MICHAEL, 277 P54_DECRYPT_FAIL_CKIPKP, 278 P54_DECRYPT_FAIL_CKIPMIC, 279 P54_DECRYPT_FAIL_AESCCMP 280 }; 281 282 struct p54_rx_data { 283 __le16 flags; 284 __le16 len; 285 __le16 freq; 286 u8 antenna; 287 u8 rate; 288 u8 rssi; 289 u8 quality; 290 u8 decrypt_status; 291 u8 rssi_raw; 292 __le32 tsf32; 293 __le32 unalloc0; 294 u8 align[0]; 295 } __attribute__ ((packed)); 296 297 enum p54_trap_type { 298 P54_TRAP_SCAN = 0, 299 P54_TRAP_TIMER, 300 P54_TRAP_BEACON_TX, 301 P54_TRAP_FAA_RADIO_ON, 302 P54_TRAP_FAA_RADIO_OFF, 303 P54_TRAP_RADAR, 304 P54_TRAP_NO_BEACON, 305 P54_TRAP_TBTT, 306 P54_TRAP_SCO_ENTER, 307 P54_TRAP_SCO_EXIT 308 }; 309 310 struct p54_trap { 311 __le16 event; 312 __le16 frequency; 313 } __attribute__ ((packed)); 314 315 enum p54_frame_sent_status { 316 P54_TX_OK = 0, 317 P54_TX_FAILED, 318 P54_TX_PSM, 319 P54_TX_PSM_CANCELLED = 4 320 }; 321 322 struct p54_frame_sent { 323 u8 status; 324 u8 tries; 325 u8 ack_rssi; 326 u8 quality; 327 __le16 seq; 328 u8 antenna; 329 u8 padding; 330 } __attribute__ ((packed)); 331 332 enum p54_tx_data_crypt { 333 P54_CRYPTO_NONE = 0, 334 P54_CRYPTO_WEP, 335 P54_CRYPTO_TKIP, 336 P54_CRYPTO_TKIPMICHAEL, 337 P54_CRYPTO_CCX_WEPMIC, 338 P54_CRYPTO_CCX_KPMIC, 339 P54_CRYPTO_CCX_KP, 340 P54_CRYPTO_AESCCMP 341 }; 342 343 struct p54_tx_data { 344 u8 rateset[8]; 345 u8 rts_rate_idx; 346 u8 crypt_offset; 347 u8 key_type; 348 u8 key_len; 349 u8 key[16]; 350 u8 hw_queue; 351 u8 backlog; 352 __le16 durations[4]; 353 u8 tx_antenna; 354 u8 output_power; 355 u8 cts_rate; 356 u8 unalloc2[3]; 357 u8 align[0]; 358 } __attribute__ ((packed)); 359 360 /* unit is ms */ 361 #define P54_TX_FRAME_LIFETIME 2000 362 #define P54_TX_TIMEOUT 4000 363 #define P54_STATISTICS_UPDATE 5000 364 365 #define P54_FILTER_TYPE_NONE 0 366 #define P54_FILTER_TYPE_STATION BIT(0) 367 #define P54_FILTER_TYPE_IBSS BIT(1) 368 #define P54_FILTER_TYPE_AP BIT(2) 369 #define P54_FILTER_TYPE_TRANSPARENT BIT(3) 370 #define P54_FILTER_TYPE_PROMISCUOUS BIT(4) 371 #define P54_FILTER_TYPE_HIBERNATE BIT(5) 372 #define P54_FILTER_TYPE_NOACK BIT(6) 373 #define P54_FILTER_TYPE_RX_DISABLED BIT(7) 374 375 struct p54_setup_mac { 376 __le16 mac_mode; 377 u8 mac_addr[ETH_ALEN]; 378 u8 bssid[ETH_ALEN]; 379 u8 rx_antenna; 380 u8 rx_align; 381 union { 382 struct { 383 __le32 basic_rate_mask; 384 u8 rts_rates[8]; 385 __le32 rx_addr; 386 __le16 max_rx; 387 __le16 rxhw; 388 __le16 wakeup_timer; 389 __le16 unalloc0; 390 } v1 __attribute__ ((packed)); 391 struct { 392 __le32 rx_addr; 393 __le16 max_rx; 394 __le16 rxhw; 395 __le16 timer; 396 __le16 truncate; 397 __le32 basic_rate_mask; 398 u8 sbss_offset; 399 u8 mcast_window; 400 u8 rx_rssi_threshold; 401 u8 rx_ed_threshold; 402 __le32 ref_clock; 403 __le16 lpf_bandwidth; 404 __le16 osc_start_delay; 405 } v2 __attribute__ ((packed)); 406 } __attribute__ ((packed)); 407 } __attribute__ ((packed)); 408 409 #define P54_SETUP_V1_LEN 40 410 #define P54_SETUP_V2_LEN (sizeof(struct p54_setup_mac)) 411 412 #define P54_SCAN_EXIT BIT(0) 413 #define P54_SCAN_TRAP BIT(1) 414 #define P54_SCAN_ACTIVE BIT(2) 415 #define P54_SCAN_FILTER BIT(3) 416 417 struct p54_scan { 418 __le16 mode; 419 __le16 dwell; 420 u8 padding1[20]; 421 struct pda_iq_autocal_entry iq_autocal; 422 u8 pa_points_per_curve; 423 u8 val_barker; 424 u8 val_bpsk; 425 u8 val_qpsk; 426 u8 val_16qam; 427 u8 val_64qam; 428 struct p54_pa_curve_data_sample curve_data[8]; 429 u8 dup_bpsk; 430 u8 dup_qpsk; 431 u8 dup_16qam; 432 u8 dup_64qam; 433 union { 434 struct pda_rssi_cal_entry v1_rssi; 435 436 struct { 437 __le32 basic_rate_mask; 438 u8 rts_rates[8]; 439 struct pda_rssi_cal_entry rssi; 440 } v2 __attribute__ ((packed)); 441 } __attribute__ ((packed)); 442 } __attribute__ ((packed)); 443 444 #define P54_SCAN_V1_LEN 0x70 445 #define P54_SCAN_V2_LEN 0x7c 446 447 struct p54_led { 448 __le16 mode; 449 __le16 led_temporary; 450 __le16 led_permanent; 451 __le16 duration; 452 } __attribute__ ((packed)); 453 454 struct p54_edcf { 455 u8 flags; 456 u8 slottime; 457 u8 sifs; 458 u8 eofpad; 459 struct p54_edcf_queue_param queue[8]; 460 u8 mapping[4]; 461 __le16 frameburst; 462 __le16 round_trip_delay; 463 } __attribute__ ((packed)); 464 465 struct p54_statistics { 466 __le32 rx_success; 467 __le32 rx_bad_fcs; 468 __le32 rx_abort; 469 __le32 rx_abort_phy; 470 __le32 rts_success; 471 __le32 rts_fail; 472 __le32 tsf32; 473 __le32 airtime; 474 __le32 noise; 475 __le32 sample_noise[8]; 476 __le32 sample_cca; 477 __le32 sample_tx; 478 } __attribute__ ((packed)); 479 480 struct p54_xbow_synth { 481 __le16 magic1; 482 __le16 magic2; 483 __le16 freq; 484 u32 padding[5]; 485 } __attribute__ ((packed)); 486 487 struct p54_timer { 488 __le32 interval; 489 } __attribute__ ((packed)); 490 491 struct p54_keycache { 492 u8 entry; 493 u8 key_id; 494 u8 mac[ETH_ALEN]; 495 u8 padding[2]; 496 u8 key_type; 497 u8 key_len; 498 u8 key[24]; 499 } __attribute__ ((packed)); 500 501 struct p54_burst { 502 u8 flags; 503 u8 queue; 504 u8 backlog; 505 u8 pad; 506 __le16 durations[32]; 507 } __attribute__ ((packed)); 508 509 struct p54_psm_interval { 510 __le16 interval; 511 __le16 periods; 512 } __attribute__ ((packed)); 513 514 #define P54_PSM BIT(0) 515 #define P54_PSM_DTIM BIT(1) 516 #define P54_PSM_MCBC BIT(2) 517 #define P54_PSM_CHECKSUM BIT(3) 518 #define P54_PSM_SKIP_MORE_DATA BIT(4) 519 #define P54_PSM_BEACON_TIMEOUT BIT(5) 520 #define P54_PSM_HFOSLEEP BIT(6) 521 #define P54_PSM_AUTOSWITCH_SLEEP BIT(7) 522 #define P54_PSM_LPIT BIT(8) 523 #define P54_PSM_BF_UCAST_SKIP BIT(9) 524 #define P54_PSM_BF_MCAST_SKIP BIT(10) 525 526 struct p54_psm { 527 __le16 mode; 528 __le16 aid; 529 struct p54_psm_interval intervals[4]; 530 u8 beacon_rssi_skip_max; 531 u8 rssi_delta_threshold; 532 u8 nr; 533 u8 exclude[1]; 534 } __attribute__ ((packed)); 535 536 #define MC_FILTER_ADDRESS_NUM 4 537 538 struct p54_group_address_table { 539 __le16 filter_enable; 540 __le16 num_address; 541 u8 mac_list[MC_FILTER_ADDRESS_NUM][ETH_ALEN]; 542 } __attribute__ ((packed)); 543 544 struct p54_txcancel { 545 __le32 req_id; 546 } __attribute__ ((packed)); 547 548 struct p54_sta_unlock { 549 u8 addr[ETH_ALEN]; 550 u16 padding; 551 } __attribute__ ((packed)); 552 553 #define P54_TIM_CLEAR BIT(15) 554 struct p54_tim { 555 u8 count; 556 u8 padding[3]; 557 __le16 entry[8]; 558 } __attribute__ ((packed)); 559 560 struct p54_cce_quiet { 561 __le32 period; 562 } __attribute__ ((packed)); 563 564 struct p54_bt_balancer { 565 __le16 prio_thresh; 566 __le16 acl_thresh; 567 } __attribute__ ((packed)); 568 569 struct p54_arp_table { 570 __le16 filter_enable; 571 u8 ipv4_addr[4]; 572 } __attribute__ ((packed)); 573 574 #endif /* P54COMMON_H */ 575