1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 */
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
25
26 #include <asm/byteorder.h>
27 #include <asm/io.h>
28
29 #include "8250.h"
30
31 #undef SERIAL_DEBUG_PCI
32
33 /*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39 struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_port *, int);
48 void (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59 };
60
moan_device(const char * str,struct pci_dev * dev)61 static void moan_device(const char *str, struct pci_dev *dev)
62 {
63 printk(KERN_WARNING "%s: %s\n"
64 KERN_WARNING "Please send the output of lspci -vv, this\n"
65 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
66 KERN_WARNING "manufacturer and name of serial board or\n"
67 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
68 pci_name(dev), str, dev->vendor, dev->device,
69 dev->subsystem_vendor, dev->subsystem_device);
70 }
71
72 static int
setup_port(struct serial_private * priv,struct uart_port * port,int bar,int offset,int regshift)73 setup_port(struct serial_private *priv, struct uart_port *port,
74 int bar, int offset, int regshift)
75 {
76 struct pci_dev *dev = priv->dev;
77 unsigned long base, len;
78
79 if (bar >= PCI_NUM_BAR_RESOURCES)
80 return -EINVAL;
81
82 base = pci_resource_start(dev, bar);
83
84 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
85 len = pci_resource_len(dev, bar);
86
87 if (!priv->remapped_bar[bar])
88 priv->remapped_bar[bar] = ioremap_nocache(base, len);
89 if (!priv->remapped_bar[bar])
90 return -ENOMEM;
91
92 port->iotype = UPIO_MEM;
93 port->iobase = 0;
94 port->mapbase = base + offset;
95 port->membase = priv->remapped_bar[bar] + offset;
96 port->regshift = regshift;
97 } else {
98 port->iotype = UPIO_PORT;
99 port->iobase = base + offset;
100 port->mapbase = 0;
101 port->membase = NULL;
102 port->regshift = 0;
103 }
104 return 0;
105 }
106
107 /*
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_port * port,int idx)110 static int addidata_apci7800_setup(struct serial_private *priv,
111 const struct pciserial_board *board,
112 struct uart_port *port, int idx)
113 {
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
116
117 if (idx < 2) {
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
120 bar += 1;
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
123 bar += 2;
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
126 bar += 3;
127 offset += ((idx - 6) * board->uart_offset);
128 }
129
130 return setup_port(priv, port, bar, offset, board->reg_shift);
131 }
132
133 /*
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
136 */
137 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_port * port,int idx)138 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
139 struct uart_port *port, int idx)
140 {
141 unsigned int bar, offset = board->first_offset;
142
143 bar = FL_GET_BASE(board->flags);
144 if (idx < 4)
145 bar += idx;
146 else {
147 bar = 4;
148 offset += (idx - 4) * board->uart_offset;
149 }
150
151 return setup_port(priv, port, bar, offset, board->reg_shift);
152 }
153
154 /*
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
160 */
pci_hp_diva_init(struct pci_dev * dev)161 static int pci_hp_diva_init(struct pci_dev *dev)
162 {
163 int rc = 0;
164
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
170 rc = 3;
171 break;
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
173 rc = 2;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 rc = 4;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
180 rc = 1;
181 break;
182 }
183
184 return rc;
185 }
186
187 /*
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
190 */
191 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_port * port,int idx)192 pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
194 struct uart_port *port, int idx)
195 {
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
199 switch (priv->dev->subsystem_device) {
200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
216 return setup_port(priv, port, bar, offset, board->reg_shift);
217 }
218
219 /*
220 * Added for EKF Intel i960 serial boards
221 */
pci_inteli960ni_init(struct pci_dev * dev)222 static int pci_inteli960ni_init(struct pci_dev *dev)
223 {
224 unsigned long oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
232 printk(KERN_DEBUG "Local i960 firmware missing");
233 return -ENODEV;
234 }
235 return 0;
236 }
237
238 /*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
pci_plx9050_init(struct pci_dev * dev)244 static int pci_plx9050_init(struct pci_dev *dev)
245 {
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
257 irq_config = 0x43;
258
259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
261 /*
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
267 * deep FIFOs
268 */
269 irq_config = 0x5b;
270 /*
271 * enable/disable interrupts
272 */
273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285 }
286
pci_plx9050_exit(struct pci_dev * dev)287 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
288 {
289 u8 __iomem *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307 }
308
309 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
310 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_port * port,int idx)311 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
312 struct uart_port *port, int idx)
313 {
314 unsigned int bar, offset = board->first_offset;
315
316 bar = 0;
317
318 if (idx < 4) {
319 /* first four channels map to 0, 0x100, 0x200, 0x300 */
320 offset += idx * board->uart_offset;
321 } else if (idx < 8) {
322 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
323 offset += idx * board->uart_offset + 0xC00;
324 } else /* we have only 8 ports on PMC-OCTALPRO */
325 return 1;
326
327 return setup_port(priv, port, bar, offset, board->reg_shift);
328 }
329
330 /*
331 * This does initialization for PMC OCTALPRO cards:
332 * maps the device memory, resets the UARTs (needed, bc
333 * if the module is removed and inserted again, the card
334 * is in the sleep mode) and enables global interrupt.
335 */
336
337 /* global control register offset for SBS PMC-OctalPro */
338 #define OCT_REG_CR_OFF 0x500
339
sbs_init(struct pci_dev * dev)340 static int sbs_init(struct pci_dev *dev)
341 {
342 u8 __iomem *p;
343
344 p = ioremap_nocache(pci_resource_start(dev, 0),
345 pci_resource_len(dev, 0));
346
347 if (p == NULL)
348 return -ENOMEM;
349 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
350 writeb(0x10, p + OCT_REG_CR_OFF);
351 udelay(50);
352 writeb(0x0, p + OCT_REG_CR_OFF);
353
354 /* Set bit-2 (INTENABLE) of Control Register */
355 writeb(0x4, p + OCT_REG_CR_OFF);
356 iounmap(p);
357
358 return 0;
359 }
360
361 /*
362 * Disables the global interrupt of PMC-OctalPro
363 */
364
sbs_exit(struct pci_dev * dev)365 static void __devexit sbs_exit(struct pci_dev *dev)
366 {
367 u8 __iomem *p;
368
369 p = ioremap_nocache(pci_resource_start(dev, 0),
370 pci_resource_len(dev, 0));
371 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
372 if (p != NULL)
373 writeb(0, p + OCT_REG_CR_OFF);
374 iounmap(p);
375 }
376
377 /*
378 * SIIG serial cards have an PCI interface chip which also controls
379 * the UART clocking frequency. Each UART can be clocked independently
380 * (except cards equiped with 4 UARTs) and initial clocking settings
381 * are stored in the EEPROM chip. It can cause problems because this
382 * version of serial driver doesn't support differently clocked UART's
383 * on single PCI card. To prevent this, initialization functions set
384 * high frequency clocking for all UART's on given card. It is safe (I
385 * hope) because it doesn't touch EEPROM settings to prevent conflicts
386 * with other OSes (like M$ DOS).
387 *
388 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
389 *
390 * There is two family of SIIG serial cards with different PCI
391 * interface chip and different configuration methods:
392 * - 10x cards have control registers in IO and/or memory space;
393 * - 20x cards have control registers in standard PCI configuration space.
394 *
395 * Note: all 10x cards have PCI device ids 0x10..
396 * all 20x cards have PCI device ids 0x20..
397 *
398 * There are also Quartet Serial cards which use Oxford Semiconductor
399 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
400 *
401 * Note: some SIIG cards are probed by the parport_serial object.
402 */
403
404 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
405 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
406
pci_siig10x_init(struct pci_dev * dev)407 static int pci_siig10x_init(struct pci_dev *dev)
408 {
409 u16 data;
410 void __iomem *p;
411
412 switch (dev->device & 0xfff8) {
413 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
414 data = 0xffdf;
415 break;
416 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
417 data = 0xf7ff;
418 break;
419 default: /* 1S1P, 4S */
420 data = 0xfffb;
421 break;
422 }
423
424 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
425 if (p == NULL)
426 return -ENOMEM;
427
428 writew(readw(p + 0x28) & data, p + 0x28);
429 readw(p + 0x28);
430 iounmap(p);
431 return 0;
432 }
433
434 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
435 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
436
pci_siig20x_init(struct pci_dev * dev)437 static int pci_siig20x_init(struct pci_dev *dev)
438 {
439 u8 data;
440
441 /* Change clock frequency for the first UART. */
442 pci_read_config_byte(dev, 0x6f, &data);
443 pci_write_config_byte(dev, 0x6f, data & 0xef);
444
445 /* If this card has 2 UART, we have to do the same with second UART. */
446 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
447 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
448 pci_read_config_byte(dev, 0x73, &data);
449 pci_write_config_byte(dev, 0x73, data & 0xef);
450 }
451 return 0;
452 }
453
pci_siig_init(struct pci_dev * dev)454 static int pci_siig_init(struct pci_dev *dev)
455 {
456 unsigned int type = dev->device & 0xff00;
457
458 if (type == 0x1000)
459 return pci_siig10x_init(dev);
460 else if (type == 0x2000)
461 return pci_siig20x_init(dev);
462
463 moan_device("Unknown SIIG card", dev);
464 return -ENODEV;
465 }
466
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_port * port,int idx)467 static int pci_siig_setup(struct serial_private *priv,
468 const struct pciserial_board *board,
469 struct uart_port *port, int idx)
470 {
471 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
472
473 if (idx > 3) {
474 bar = 4;
475 offset = (idx - 4) * 8;
476 }
477
478 return setup_port(priv, port, bar, offset, 0);
479 }
480
481 /*
482 * Timedia has an explosion of boards, and to avoid the PCI table from
483 * growing *huge*, we use this function to collapse some 70 entries
484 * in the PCI table into one, for sanity's and compactness's sake.
485 */
486 static const unsigned short timedia_single_port[] = {
487 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
488 };
489
490 static const unsigned short timedia_dual_port[] = {
491 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
492 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
493 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
494 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
495 0xD079, 0
496 };
497
498 static const unsigned short timedia_quad_port[] = {
499 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
500 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
501 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
502 0xB157, 0
503 };
504
505 static const unsigned short timedia_eight_port[] = {
506 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
507 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
508 };
509
510 static const struct timedia_struct {
511 int num;
512 const unsigned short *ids;
513 } timedia_data[] = {
514 { 1, timedia_single_port },
515 { 2, timedia_dual_port },
516 { 4, timedia_quad_port },
517 { 8, timedia_eight_port }
518 };
519
pci_timedia_init(struct pci_dev * dev)520 static int pci_timedia_init(struct pci_dev *dev)
521 {
522 const unsigned short *ids;
523 int i, j;
524
525 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
526 ids = timedia_data[i].ids;
527 for (j = 0; ids[j]; j++)
528 if (dev->subsystem_device == ids[j])
529 return timedia_data[i].num;
530 }
531 return 0;
532 }
533
534 /*
535 * Timedia/SUNIX uses a mixture of BARs and offsets
536 * Ugh, this is ugly as all hell --- TYT
537 */
538 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_port * port,int idx)539 pci_timedia_setup(struct serial_private *priv,
540 const struct pciserial_board *board,
541 struct uart_port *port, int idx)
542 {
543 unsigned int bar = 0, offset = board->first_offset;
544
545 switch (idx) {
546 case 0:
547 bar = 0;
548 break;
549 case 1:
550 offset = board->uart_offset;
551 bar = 0;
552 break;
553 case 2:
554 bar = 1;
555 break;
556 case 3:
557 offset = board->uart_offset;
558 /* FALLTHROUGH */
559 case 4: /* BAR 2 */
560 case 5: /* BAR 3 */
561 case 6: /* BAR 4 */
562 case 7: /* BAR 5 */
563 bar = idx - 2;
564 }
565
566 return setup_port(priv, port, bar, offset, board->reg_shift);
567 }
568
569 /*
570 * Some Titan cards are also a little weird
571 */
572 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_port * port,int idx)573 titan_400l_800l_setup(struct serial_private *priv,
574 const struct pciserial_board *board,
575 struct uart_port *port, int idx)
576 {
577 unsigned int bar, offset = board->first_offset;
578
579 switch (idx) {
580 case 0:
581 bar = 1;
582 break;
583 case 1:
584 bar = 2;
585 break;
586 default:
587 bar = 4;
588 offset = (idx - 2) * board->uart_offset;
589 }
590
591 return setup_port(priv, port, bar, offset, board->reg_shift);
592 }
593
pci_xircom_init(struct pci_dev * dev)594 static int pci_xircom_init(struct pci_dev *dev)
595 {
596 msleep(100);
597 return 0;
598 }
599
pci_netmos_init(struct pci_dev * dev)600 static int pci_netmos_init(struct pci_dev *dev)
601 {
602 /* subdevice 0x00PS means <P> parallel, <S> serial */
603 unsigned int num_serial = dev->subsystem_device & 0xf;
604
605 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
606 dev->subsystem_device == 0x0299)
607 return 0;
608
609 if (num_serial == 0)
610 return -ENODEV;
611 return num_serial;
612 }
613
614 /*
615 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
616 *
617 * These chips are available with optionally one parallel port and up to
618 * two serial ports. Unfortunately they all have the same product id.
619 *
620 * Basic configuration is done over a region of 32 I/O ports. The base
621 * ioport is called INTA or INTC, depending on docs/other drivers.
622 *
623 * The region of the 32 I/O ports is configured in POSIO0R...
624 */
625
626 /* registers */
627 #define ITE_887x_MISCR 0x9c
628 #define ITE_887x_INTCBAR 0x78
629 #define ITE_887x_UARTBAR 0x7c
630 #define ITE_887x_PS0BAR 0x10
631 #define ITE_887x_POSIO0 0x60
632
633 /* I/O space size */
634 #define ITE_887x_IOSIZE 32
635 /* I/O space size (bits 26-24; 8 bytes = 011b) */
636 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
637 /* I/O space size (bits 26-24; 32 bytes = 101b) */
638 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
639 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
640 #define ITE_887x_POSIO_SPEED (3 << 29)
641 /* enable IO_Space bit */
642 #define ITE_887x_POSIO_ENABLE (1 << 31)
643
pci_ite887x_init(struct pci_dev * dev)644 static int pci_ite887x_init(struct pci_dev *dev)
645 {
646 /* inta_addr are the configuration addresses of the ITE */
647 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
648 0x200, 0x280, 0 };
649 int ret, i, type;
650 struct resource *iobase = NULL;
651 u32 miscr, uartbar, ioport;
652
653 /* search for the base-ioport */
654 i = 0;
655 while (inta_addr[i] && iobase == NULL) {
656 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
657 "ite887x");
658 if (iobase != NULL) {
659 /* write POSIO0R - speed | size | ioport */
660 pci_write_config_dword(dev, ITE_887x_POSIO0,
661 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
662 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
663 /* write INTCBAR - ioport */
664 pci_write_config_dword(dev, ITE_887x_INTCBAR,
665 inta_addr[i]);
666 ret = inb(inta_addr[i]);
667 if (ret != 0xff) {
668 /* ioport connected */
669 break;
670 }
671 release_region(iobase->start, ITE_887x_IOSIZE);
672 iobase = NULL;
673 }
674 i++;
675 }
676
677 if (!inta_addr[i]) {
678 printk(KERN_ERR "ite887x: could not find iobase\n");
679 return -ENODEV;
680 }
681
682 /* start of undocumented type checking (see parport_pc.c) */
683 type = inb(iobase->start + 0x18) & 0x0f;
684
685 switch (type) {
686 case 0x2: /* ITE8871 (1P) */
687 case 0xa: /* ITE8875 (1P) */
688 ret = 0;
689 break;
690 case 0xe: /* ITE8872 (2S1P) */
691 ret = 2;
692 break;
693 case 0x6: /* ITE8873 (1S) */
694 ret = 1;
695 break;
696 case 0x8: /* ITE8874 (2S) */
697 ret = 2;
698 break;
699 default:
700 moan_device("Unknown ITE887x", dev);
701 ret = -ENODEV;
702 }
703
704 /* configure all serial ports */
705 for (i = 0; i < ret; i++) {
706 /* read the I/O port from the device */
707 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
708 &ioport);
709 ioport &= 0x0000FF00; /* the actual base address */
710 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
711 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
712 ITE_887x_POSIO_IOSIZE_8 | ioport);
713
714 /* write the ioport to the UARTBAR */
715 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
716 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
717 uartbar |= (ioport << (16 * i)); /* set the ioport */
718 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
719
720 /* get current config */
721 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
722 /* disable interrupts (UARTx_Routing[3:0]) */
723 miscr &= ~(0xf << (12 - 4 * i));
724 /* activate the UART (UARTx_En) */
725 miscr |= 1 << (23 - i);
726 /* write new config with activated UART */
727 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
728 }
729
730 if (ret <= 0) {
731 /* the device has no UARTs if we get here */
732 release_region(iobase->start, ITE_887x_IOSIZE);
733 }
734
735 return ret;
736 }
737
pci_ite887x_exit(struct pci_dev * dev)738 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
739 {
740 u32 ioport;
741 /* the ioport is bit 0-15 in POSIO0R */
742 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
743 ioport &= 0xffff;
744 release_region(ioport, ITE_887x_IOSIZE);
745 }
746
747 /*
748 * Oxford Semiconductor Inc.
749 * Check that device is part of the Tornado range of devices, then determine
750 * the number of ports available on the device.
751 */
pci_oxsemi_tornado_init(struct pci_dev * dev)752 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
753 {
754 u8 __iomem *p;
755 unsigned long deviceID;
756 unsigned int number_uarts = 0;
757
758 /* OxSemi Tornado devices are all 0xCxxx */
759 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
760 (dev->device & 0xF000) != 0xC000)
761 return 0;
762
763 p = pci_iomap(dev, 0, 5);
764 if (p == NULL)
765 return -ENOMEM;
766
767 deviceID = ioread32(p);
768 /* Tornado device */
769 if (deviceID == 0x07000200) {
770 number_uarts = ioread8(p + 4);
771 printk(KERN_DEBUG
772 "%d ports detected on Oxford PCI Express device\n",
773 number_uarts);
774 }
775 pci_iounmap(dev, p);
776 return number_uarts;
777 }
778
779 static int
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_port * port,int idx)780 pci_default_setup(struct serial_private *priv,
781 const struct pciserial_board *board,
782 struct uart_port *port, int idx)
783 {
784 unsigned int bar, offset = board->first_offset, maxnr;
785
786 bar = FL_GET_BASE(board->flags);
787 if (board->flags & FL_BASE_BARS)
788 bar += idx;
789 else
790 offset += idx * board->uart_offset;
791
792 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
793 (board->reg_shift + 3);
794
795 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
796 return 1;
797
798 return setup_port(priv, port, bar, offset, board->reg_shift);
799 }
800
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_port * port,int idx)801 static int skip_tx_en_setup(struct serial_private *priv,
802 const struct pciserial_board *board,
803 struct uart_port *port, int idx)
804 {
805 port->flags |= UPF_NO_TXEN_TEST;
806 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
807 "[%04x:%04x] subsystem [%04x:%04x]\n",
808 priv->dev->vendor,
809 priv->dev->device,
810 priv->dev->subsystem_vendor,
811 priv->dev->subsystem_device);
812
813 return pci_default_setup(priv, board, port, idx);
814 }
815
816 /* This should be in linux/pci_ids.h */
817 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
818 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
819 #define PCI_DEVICE_ID_OCTPRO 0x0001
820 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
821 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
822 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
823 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
824 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
825 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
826
827 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
828 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
829
830 /*
831 * Master list of serial port init/setup/exit quirks.
832 * This does not describe the general nature of the port.
833 * (ie, baud base, number and location of ports, etc)
834 *
835 * This list is ordered alphabetically by vendor then device.
836 * Specific entries must come before more generic entries.
837 */
838 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
839 /*
840 * ADDI-DATA GmbH communication cards <info@addi-data.com>
841 */
842 {
843 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
844 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
845 .subvendor = PCI_ANY_ID,
846 .subdevice = PCI_ANY_ID,
847 .setup = addidata_apci7800_setup,
848 },
849 /*
850 * AFAVLAB cards - these may be called via parport_serial
851 * It is not clear whether this applies to all products.
852 */
853 {
854 .vendor = PCI_VENDOR_ID_AFAVLAB,
855 .device = PCI_ANY_ID,
856 .subvendor = PCI_ANY_ID,
857 .subdevice = PCI_ANY_ID,
858 .setup = afavlab_setup,
859 },
860 /*
861 * HP Diva
862 */
863 {
864 .vendor = PCI_VENDOR_ID_HP,
865 .device = PCI_DEVICE_ID_HP_DIVA,
866 .subvendor = PCI_ANY_ID,
867 .subdevice = PCI_ANY_ID,
868 .init = pci_hp_diva_init,
869 .setup = pci_hp_diva_setup,
870 },
871 /*
872 * Intel
873 */
874 {
875 .vendor = PCI_VENDOR_ID_INTEL,
876 .device = PCI_DEVICE_ID_INTEL_80960_RP,
877 .subvendor = 0xe4bf,
878 .subdevice = PCI_ANY_ID,
879 .init = pci_inteli960ni_init,
880 .setup = pci_default_setup,
881 },
882 {
883 .vendor = PCI_VENDOR_ID_INTEL,
884 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
885 .subvendor = PCI_ANY_ID,
886 .subdevice = PCI_ANY_ID,
887 .setup = skip_tx_en_setup,
888 },
889 {
890 .vendor = PCI_VENDOR_ID_INTEL,
891 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
892 .subvendor = PCI_ANY_ID,
893 .subdevice = PCI_ANY_ID,
894 .setup = skip_tx_en_setup,
895 },
896 {
897 .vendor = PCI_VENDOR_ID_INTEL,
898 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
899 .subvendor = PCI_ANY_ID,
900 .subdevice = PCI_ANY_ID,
901 .setup = skip_tx_en_setup,
902 },
903 /*
904 * ITE
905 */
906 {
907 .vendor = PCI_VENDOR_ID_ITE,
908 .device = PCI_DEVICE_ID_ITE_8872,
909 .subvendor = PCI_ANY_ID,
910 .subdevice = PCI_ANY_ID,
911 .init = pci_ite887x_init,
912 .setup = pci_default_setup,
913 .exit = __devexit_p(pci_ite887x_exit),
914 },
915 /*
916 * Panacom
917 */
918 {
919 .vendor = PCI_VENDOR_ID_PANACOM,
920 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
921 .subvendor = PCI_ANY_ID,
922 .subdevice = PCI_ANY_ID,
923 .init = pci_plx9050_init,
924 .setup = pci_default_setup,
925 .exit = __devexit_p(pci_plx9050_exit),
926 },
927 {
928 .vendor = PCI_VENDOR_ID_PANACOM,
929 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
930 .subvendor = PCI_ANY_ID,
931 .subdevice = PCI_ANY_ID,
932 .init = pci_plx9050_init,
933 .setup = pci_default_setup,
934 .exit = __devexit_p(pci_plx9050_exit),
935 },
936 /*
937 * PLX
938 */
939 {
940 .vendor = PCI_VENDOR_ID_PLX,
941 .device = PCI_DEVICE_ID_PLX_9030,
942 .subvendor = PCI_SUBVENDOR_ID_PERLE,
943 .subdevice = PCI_ANY_ID,
944 .setup = pci_default_setup,
945 },
946 {
947 .vendor = PCI_VENDOR_ID_PLX,
948 .device = PCI_DEVICE_ID_PLX_9050,
949 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
950 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
951 .init = pci_plx9050_init,
952 .setup = pci_default_setup,
953 .exit = __devexit_p(pci_plx9050_exit),
954 },
955 {
956 .vendor = PCI_VENDOR_ID_PLX,
957 .device = PCI_DEVICE_ID_PLX_9050,
958 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
959 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
960 .init = pci_plx9050_init,
961 .setup = pci_default_setup,
962 .exit = __devexit_p(pci_plx9050_exit),
963 },
964 {
965 .vendor = PCI_VENDOR_ID_PLX,
966 .device = PCI_DEVICE_ID_PLX_9050,
967 .subvendor = PCI_VENDOR_ID_PLX,
968 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
969 .init = pci_plx9050_init,
970 .setup = pci_default_setup,
971 .exit = __devexit_p(pci_plx9050_exit),
972 },
973 {
974 .vendor = PCI_VENDOR_ID_PLX,
975 .device = PCI_DEVICE_ID_PLX_ROMULUS,
976 .subvendor = PCI_VENDOR_ID_PLX,
977 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
978 .init = pci_plx9050_init,
979 .setup = pci_default_setup,
980 .exit = __devexit_p(pci_plx9050_exit),
981 },
982 /*
983 * SBS Technologies, Inc., PMC-OCTALPRO 232
984 */
985 {
986 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
987 .device = PCI_DEVICE_ID_OCTPRO,
988 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
989 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
990 .init = sbs_init,
991 .setup = sbs_setup,
992 .exit = __devexit_p(sbs_exit),
993 },
994 /*
995 * SBS Technologies, Inc., PMC-OCTALPRO 422
996 */
997 {
998 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
999 .device = PCI_DEVICE_ID_OCTPRO,
1000 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1001 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1002 .init = sbs_init,
1003 .setup = sbs_setup,
1004 .exit = __devexit_p(sbs_exit),
1005 },
1006 /*
1007 * SBS Technologies, Inc., P-Octal 232
1008 */
1009 {
1010 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1011 .device = PCI_DEVICE_ID_OCTPRO,
1012 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1013 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1014 .init = sbs_init,
1015 .setup = sbs_setup,
1016 .exit = __devexit_p(sbs_exit),
1017 },
1018 /*
1019 * SBS Technologies, Inc., P-Octal 422
1020 */
1021 {
1022 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1023 .device = PCI_DEVICE_ID_OCTPRO,
1024 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1025 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1026 .init = sbs_init,
1027 .setup = sbs_setup,
1028 .exit = __devexit_p(sbs_exit),
1029 },
1030 /*
1031 * SIIG cards - these may be called via parport_serial
1032 */
1033 {
1034 .vendor = PCI_VENDOR_ID_SIIG,
1035 .device = PCI_ANY_ID,
1036 .subvendor = PCI_ANY_ID,
1037 .subdevice = PCI_ANY_ID,
1038 .init = pci_siig_init,
1039 .setup = pci_siig_setup,
1040 },
1041 /*
1042 * Titan cards
1043 */
1044 {
1045 .vendor = PCI_VENDOR_ID_TITAN,
1046 .device = PCI_DEVICE_ID_TITAN_400L,
1047 .subvendor = PCI_ANY_ID,
1048 .subdevice = PCI_ANY_ID,
1049 .setup = titan_400l_800l_setup,
1050 },
1051 {
1052 .vendor = PCI_VENDOR_ID_TITAN,
1053 .device = PCI_DEVICE_ID_TITAN_800L,
1054 .subvendor = PCI_ANY_ID,
1055 .subdevice = PCI_ANY_ID,
1056 .setup = titan_400l_800l_setup,
1057 },
1058 /*
1059 * Timedia cards
1060 */
1061 {
1062 .vendor = PCI_VENDOR_ID_TIMEDIA,
1063 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1064 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1065 .subdevice = PCI_ANY_ID,
1066 .init = pci_timedia_init,
1067 .setup = pci_timedia_setup,
1068 },
1069 {
1070 .vendor = PCI_VENDOR_ID_TIMEDIA,
1071 .device = PCI_ANY_ID,
1072 .subvendor = PCI_ANY_ID,
1073 .subdevice = PCI_ANY_ID,
1074 .setup = pci_timedia_setup,
1075 },
1076 /*
1077 * Xircom cards
1078 */
1079 {
1080 .vendor = PCI_VENDOR_ID_XIRCOM,
1081 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1082 .subvendor = PCI_ANY_ID,
1083 .subdevice = PCI_ANY_ID,
1084 .init = pci_xircom_init,
1085 .setup = pci_default_setup,
1086 },
1087 /*
1088 * Netmos cards - these may be called via parport_serial
1089 */
1090 {
1091 .vendor = PCI_VENDOR_ID_NETMOS,
1092 .device = PCI_ANY_ID,
1093 .subvendor = PCI_ANY_ID,
1094 .subdevice = PCI_ANY_ID,
1095 .init = pci_netmos_init,
1096 .setup = pci_default_setup,
1097 },
1098 /*
1099 * For Oxford Semiconductor and Mainpine
1100 */
1101 {
1102 .vendor = PCI_VENDOR_ID_OXSEMI,
1103 .device = PCI_ANY_ID,
1104 .subvendor = PCI_ANY_ID,
1105 .subdevice = PCI_ANY_ID,
1106 .init = pci_oxsemi_tornado_init,
1107 .setup = pci_default_setup,
1108 },
1109 {
1110 .vendor = PCI_VENDOR_ID_MAINPINE,
1111 .device = PCI_ANY_ID,
1112 .subvendor = PCI_ANY_ID,
1113 .subdevice = PCI_ANY_ID,
1114 .init = pci_oxsemi_tornado_init,
1115 .setup = pci_default_setup,
1116 },
1117 /*
1118 * Default "match everything" terminator entry
1119 */
1120 {
1121 .vendor = PCI_ANY_ID,
1122 .device = PCI_ANY_ID,
1123 .subvendor = PCI_ANY_ID,
1124 .subdevice = PCI_ANY_ID,
1125 .setup = pci_default_setup,
1126 }
1127 };
1128
quirk_id_matches(u32 quirk_id,u32 dev_id)1129 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1130 {
1131 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1132 }
1133
find_quirk(struct pci_dev * dev)1134 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1135 {
1136 struct pci_serial_quirk *quirk;
1137
1138 for (quirk = pci_serial_quirks; ; quirk++)
1139 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1140 quirk_id_matches(quirk->device, dev->device) &&
1141 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1142 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1143 break;
1144 return quirk;
1145 }
1146
get_pci_irq(struct pci_dev * dev,const struct pciserial_board * board)1147 static inline int get_pci_irq(struct pci_dev *dev,
1148 const struct pciserial_board *board)
1149 {
1150 if (board->flags & FL_NOIRQ)
1151 return 0;
1152 else
1153 return dev->irq;
1154 }
1155
1156 /*
1157 * This is the configuration table for all of the PCI serial boards
1158 * which we support. It is directly indexed by the pci_board_num_t enum
1159 * value, which is encoded in the pci_device_id PCI probe table's
1160 * driver_data member.
1161 *
1162 * The makeup of these names are:
1163 * pbn_bn{_bt}_n_baud{_offsetinhex}
1164 *
1165 * bn = PCI BAR number
1166 * bt = Index using PCI BARs
1167 * n = number of serial ports
1168 * baud = baud rate
1169 * offsetinhex = offset for each sequential port (in hex)
1170 *
1171 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1172 *
1173 * Please note: in theory if n = 1, _bt infix should make no difference.
1174 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1175 */
1176 enum pci_board_num_t {
1177 pbn_default = 0,
1178
1179 pbn_b0_1_115200,
1180 pbn_b0_2_115200,
1181 pbn_b0_4_115200,
1182 pbn_b0_5_115200,
1183 pbn_b0_8_115200,
1184
1185 pbn_b0_1_921600,
1186 pbn_b0_2_921600,
1187 pbn_b0_4_921600,
1188
1189 pbn_b0_2_1130000,
1190
1191 pbn_b0_4_1152000,
1192
1193 pbn_b0_2_1843200,
1194 pbn_b0_4_1843200,
1195
1196 pbn_b0_2_1843200_200,
1197 pbn_b0_4_1843200_200,
1198 pbn_b0_8_1843200_200,
1199
1200 pbn_b0_1_4000000,
1201
1202 pbn_b0_bt_1_115200,
1203 pbn_b0_bt_2_115200,
1204 pbn_b0_bt_8_115200,
1205
1206 pbn_b0_bt_1_460800,
1207 pbn_b0_bt_2_460800,
1208 pbn_b0_bt_4_460800,
1209
1210 pbn_b0_bt_1_921600,
1211 pbn_b0_bt_2_921600,
1212 pbn_b0_bt_4_921600,
1213 pbn_b0_bt_8_921600,
1214
1215 pbn_b1_1_115200,
1216 pbn_b1_2_115200,
1217 pbn_b1_4_115200,
1218 pbn_b1_8_115200,
1219
1220 pbn_b1_1_921600,
1221 pbn_b1_2_921600,
1222 pbn_b1_4_921600,
1223 pbn_b1_8_921600,
1224
1225 pbn_b1_2_1250000,
1226
1227 pbn_b1_bt_1_115200,
1228 pbn_b1_bt_2_921600,
1229
1230 pbn_b1_1_1382400,
1231 pbn_b1_2_1382400,
1232 pbn_b1_4_1382400,
1233 pbn_b1_8_1382400,
1234
1235 pbn_b2_1_115200,
1236 pbn_b2_2_115200,
1237 pbn_b2_4_115200,
1238 pbn_b2_8_115200,
1239
1240 pbn_b2_1_460800,
1241 pbn_b2_4_460800,
1242 pbn_b2_8_460800,
1243 pbn_b2_16_460800,
1244
1245 pbn_b2_1_921600,
1246 pbn_b2_4_921600,
1247 pbn_b2_8_921600,
1248
1249 pbn_b2_bt_1_115200,
1250 pbn_b2_bt_2_115200,
1251 pbn_b2_bt_4_115200,
1252
1253 pbn_b2_bt_2_921600,
1254 pbn_b2_bt_4_921600,
1255
1256 pbn_b3_2_115200,
1257 pbn_b3_4_115200,
1258 pbn_b3_8_115200,
1259
1260 /*
1261 * Board-specific versions.
1262 */
1263 pbn_panacom,
1264 pbn_panacom2,
1265 pbn_panacom4,
1266 pbn_exsys_4055,
1267 pbn_plx_romulus,
1268 pbn_oxsemi,
1269 pbn_oxsemi_1_4000000,
1270 pbn_oxsemi_2_4000000,
1271 pbn_oxsemi_4_4000000,
1272 pbn_oxsemi_8_4000000,
1273 pbn_intel_i960,
1274 pbn_sgi_ioc3,
1275 pbn_computone_4,
1276 pbn_computone_6,
1277 pbn_computone_8,
1278 pbn_sbsxrsio,
1279 pbn_exar_XR17C152,
1280 pbn_exar_XR17C154,
1281 pbn_exar_XR17C158,
1282 pbn_pasemi_1682M,
1283 };
1284
1285 /*
1286 * uart_offset - the space between channels
1287 * reg_shift - describes how the UART registers are mapped
1288 * to PCI memory by the card.
1289 * For example IER register on SBS, Inc. PMC-OctPro is located at
1290 * offset 0x10 from the UART base, while UART_IER is defined as 1
1291 * in include/linux/serial_reg.h,
1292 * see first lines of serial_in() and serial_out() in 8250.c
1293 */
1294
1295 static struct pciserial_board pci_boards[] __devinitdata = {
1296 [pbn_default] = {
1297 .flags = FL_BASE0,
1298 .num_ports = 1,
1299 .base_baud = 115200,
1300 .uart_offset = 8,
1301 },
1302 [pbn_b0_1_115200] = {
1303 .flags = FL_BASE0,
1304 .num_ports = 1,
1305 .base_baud = 115200,
1306 .uart_offset = 8,
1307 },
1308 [pbn_b0_2_115200] = {
1309 .flags = FL_BASE0,
1310 .num_ports = 2,
1311 .base_baud = 115200,
1312 .uart_offset = 8,
1313 },
1314 [pbn_b0_4_115200] = {
1315 .flags = FL_BASE0,
1316 .num_ports = 4,
1317 .base_baud = 115200,
1318 .uart_offset = 8,
1319 },
1320 [pbn_b0_5_115200] = {
1321 .flags = FL_BASE0,
1322 .num_ports = 5,
1323 .base_baud = 115200,
1324 .uart_offset = 8,
1325 },
1326 [pbn_b0_8_115200] = {
1327 .flags = FL_BASE0,
1328 .num_ports = 8,
1329 .base_baud = 115200,
1330 .uart_offset = 8,
1331 },
1332 [pbn_b0_1_921600] = {
1333 .flags = FL_BASE0,
1334 .num_ports = 1,
1335 .base_baud = 921600,
1336 .uart_offset = 8,
1337 },
1338 [pbn_b0_2_921600] = {
1339 .flags = FL_BASE0,
1340 .num_ports = 2,
1341 .base_baud = 921600,
1342 .uart_offset = 8,
1343 },
1344 [pbn_b0_4_921600] = {
1345 .flags = FL_BASE0,
1346 .num_ports = 4,
1347 .base_baud = 921600,
1348 .uart_offset = 8,
1349 },
1350
1351 [pbn_b0_2_1130000] = {
1352 .flags = FL_BASE0,
1353 .num_ports = 2,
1354 .base_baud = 1130000,
1355 .uart_offset = 8,
1356 },
1357
1358 [pbn_b0_4_1152000] = {
1359 .flags = FL_BASE0,
1360 .num_ports = 4,
1361 .base_baud = 1152000,
1362 .uart_offset = 8,
1363 },
1364
1365 [pbn_b0_2_1843200] = {
1366 .flags = FL_BASE0,
1367 .num_ports = 2,
1368 .base_baud = 1843200,
1369 .uart_offset = 8,
1370 },
1371 [pbn_b0_4_1843200] = {
1372 .flags = FL_BASE0,
1373 .num_ports = 4,
1374 .base_baud = 1843200,
1375 .uart_offset = 8,
1376 },
1377
1378 [pbn_b0_2_1843200_200] = {
1379 .flags = FL_BASE0,
1380 .num_ports = 2,
1381 .base_baud = 1843200,
1382 .uart_offset = 0x200,
1383 },
1384 [pbn_b0_4_1843200_200] = {
1385 .flags = FL_BASE0,
1386 .num_ports = 4,
1387 .base_baud = 1843200,
1388 .uart_offset = 0x200,
1389 },
1390 [pbn_b0_8_1843200_200] = {
1391 .flags = FL_BASE0,
1392 .num_ports = 8,
1393 .base_baud = 1843200,
1394 .uart_offset = 0x200,
1395 },
1396 [pbn_b0_1_4000000] = {
1397 .flags = FL_BASE0,
1398 .num_ports = 1,
1399 .base_baud = 4000000,
1400 .uart_offset = 8,
1401 },
1402
1403 [pbn_b0_bt_1_115200] = {
1404 .flags = FL_BASE0|FL_BASE_BARS,
1405 .num_ports = 1,
1406 .base_baud = 115200,
1407 .uart_offset = 8,
1408 },
1409 [pbn_b0_bt_2_115200] = {
1410 .flags = FL_BASE0|FL_BASE_BARS,
1411 .num_ports = 2,
1412 .base_baud = 115200,
1413 .uart_offset = 8,
1414 },
1415 [pbn_b0_bt_8_115200] = {
1416 .flags = FL_BASE0|FL_BASE_BARS,
1417 .num_ports = 8,
1418 .base_baud = 115200,
1419 .uart_offset = 8,
1420 },
1421
1422 [pbn_b0_bt_1_460800] = {
1423 .flags = FL_BASE0|FL_BASE_BARS,
1424 .num_ports = 1,
1425 .base_baud = 460800,
1426 .uart_offset = 8,
1427 },
1428 [pbn_b0_bt_2_460800] = {
1429 .flags = FL_BASE0|FL_BASE_BARS,
1430 .num_ports = 2,
1431 .base_baud = 460800,
1432 .uart_offset = 8,
1433 },
1434 [pbn_b0_bt_4_460800] = {
1435 .flags = FL_BASE0|FL_BASE_BARS,
1436 .num_ports = 4,
1437 .base_baud = 460800,
1438 .uart_offset = 8,
1439 },
1440
1441 [pbn_b0_bt_1_921600] = {
1442 .flags = FL_BASE0|FL_BASE_BARS,
1443 .num_ports = 1,
1444 .base_baud = 921600,
1445 .uart_offset = 8,
1446 },
1447 [pbn_b0_bt_2_921600] = {
1448 .flags = FL_BASE0|FL_BASE_BARS,
1449 .num_ports = 2,
1450 .base_baud = 921600,
1451 .uart_offset = 8,
1452 },
1453 [pbn_b0_bt_4_921600] = {
1454 .flags = FL_BASE0|FL_BASE_BARS,
1455 .num_ports = 4,
1456 .base_baud = 921600,
1457 .uart_offset = 8,
1458 },
1459 [pbn_b0_bt_8_921600] = {
1460 .flags = FL_BASE0|FL_BASE_BARS,
1461 .num_ports = 8,
1462 .base_baud = 921600,
1463 .uart_offset = 8,
1464 },
1465
1466 [pbn_b1_1_115200] = {
1467 .flags = FL_BASE1,
1468 .num_ports = 1,
1469 .base_baud = 115200,
1470 .uart_offset = 8,
1471 },
1472 [pbn_b1_2_115200] = {
1473 .flags = FL_BASE1,
1474 .num_ports = 2,
1475 .base_baud = 115200,
1476 .uart_offset = 8,
1477 },
1478 [pbn_b1_4_115200] = {
1479 .flags = FL_BASE1,
1480 .num_ports = 4,
1481 .base_baud = 115200,
1482 .uart_offset = 8,
1483 },
1484 [pbn_b1_8_115200] = {
1485 .flags = FL_BASE1,
1486 .num_ports = 8,
1487 .base_baud = 115200,
1488 .uart_offset = 8,
1489 },
1490
1491 [pbn_b1_1_921600] = {
1492 .flags = FL_BASE1,
1493 .num_ports = 1,
1494 .base_baud = 921600,
1495 .uart_offset = 8,
1496 },
1497 [pbn_b1_2_921600] = {
1498 .flags = FL_BASE1,
1499 .num_ports = 2,
1500 .base_baud = 921600,
1501 .uart_offset = 8,
1502 },
1503 [pbn_b1_4_921600] = {
1504 .flags = FL_BASE1,
1505 .num_ports = 4,
1506 .base_baud = 921600,
1507 .uart_offset = 8,
1508 },
1509 [pbn_b1_8_921600] = {
1510 .flags = FL_BASE1,
1511 .num_ports = 8,
1512 .base_baud = 921600,
1513 .uart_offset = 8,
1514 },
1515 [pbn_b1_2_1250000] = {
1516 .flags = FL_BASE1,
1517 .num_ports = 2,
1518 .base_baud = 1250000,
1519 .uart_offset = 8,
1520 },
1521
1522 [pbn_b1_bt_1_115200] = {
1523 .flags = FL_BASE1|FL_BASE_BARS,
1524 .num_ports = 1,
1525 .base_baud = 115200,
1526 .uart_offset = 8,
1527 },
1528
1529 [pbn_b1_bt_2_921600] = {
1530 .flags = FL_BASE1|FL_BASE_BARS,
1531 .num_ports = 2,
1532 .base_baud = 921600,
1533 .uart_offset = 8,
1534 },
1535
1536 [pbn_b1_1_1382400] = {
1537 .flags = FL_BASE1,
1538 .num_ports = 1,
1539 .base_baud = 1382400,
1540 .uart_offset = 8,
1541 },
1542 [pbn_b1_2_1382400] = {
1543 .flags = FL_BASE1,
1544 .num_ports = 2,
1545 .base_baud = 1382400,
1546 .uart_offset = 8,
1547 },
1548 [pbn_b1_4_1382400] = {
1549 .flags = FL_BASE1,
1550 .num_ports = 4,
1551 .base_baud = 1382400,
1552 .uart_offset = 8,
1553 },
1554 [pbn_b1_8_1382400] = {
1555 .flags = FL_BASE1,
1556 .num_ports = 8,
1557 .base_baud = 1382400,
1558 .uart_offset = 8,
1559 },
1560
1561 [pbn_b2_1_115200] = {
1562 .flags = FL_BASE2,
1563 .num_ports = 1,
1564 .base_baud = 115200,
1565 .uart_offset = 8,
1566 },
1567 [pbn_b2_2_115200] = {
1568 .flags = FL_BASE2,
1569 .num_ports = 2,
1570 .base_baud = 115200,
1571 .uart_offset = 8,
1572 },
1573 [pbn_b2_4_115200] = {
1574 .flags = FL_BASE2,
1575 .num_ports = 4,
1576 .base_baud = 115200,
1577 .uart_offset = 8,
1578 },
1579 [pbn_b2_8_115200] = {
1580 .flags = FL_BASE2,
1581 .num_ports = 8,
1582 .base_baud = 115200,
1583 .uart_offset = 8,
1584 },
1585
1586 [pbn_b2_1_460800] = {
1587 .flags = FL_BASE2,
1588 .num_ports = 1,
1589 .base_baud = 460800,
1590 .uart_offset = 8,
1591 },
1592 [pbn_b2_4_460800] = {
1593 .flags = FL_BASE2,
1594 .num_ports = 4,
1595 .base_baud = 460800,
1596 .uart_offset = 8,
1597 },
1598 [pbn_b2_8_460800] = {
1599 .flags = FL_BASE2,
1600 .num_ports = 8,
1601 .base_baud = 460800,
1602 .uart_offset = 8,
1603 },
1604 [pbn_b2_16_460800] = {
1605 .flags = FL_BASE2,
1606 .num_ports = 16,
1607 .base_baud = 460800,
1608 .uart_offset = 8,
1609 },
1610
1611 [pbn_b2_1_921600] = {
1612 .flags = FL_BASE2,
1613 .num_ports = 1,
1614 .base_baud = 921600,
1615 .uart_offset = 8,
1616 },
1617 [pbn_b2_4_921600] = {
1618 .flags = FL_BASE2,
1619 .num_ports = 4,
1620 .base_baud = 921600,
1621 .uart_offset = 8,
1622 },
1623 [pbn_b2_8_921600] = {
1624 .flags = FL_BASE2,
1625 .num_ports = 8,
1626 .base_baud = 921600,
1627 .uart_offset = 8,
1628 },
1629
1630 [pbn_b2_bt_1_115200] = {
1631 .flags = FL_BASE2|FL_BASE_BARS,
1632 .num_ports = 1,
1633 .base_baud = 115200,
1634 .uart_offset = 8,
1635 },
1636 [pbn_b2_bt_2_115200] = {
1637 .flags = FL_BASE2|FL_BASE_BARS,
1638 .num_ports = 2,
1639 .base_baud = 115200,
1640 .uart_offset = 8,
1641 },
1642 [pbn_b2_bt_4_115200] = {
1643 .flags = FL_BASE2|FL_BASE_BARS,
1644 .num_ports = 4,
1645 .base_baud = 115200,
1646 .uart_offset = 8,
1647 },
1648
1649 [pbn_b2_bt_2_921600] = {
1650 .flags = FL_BASE2|FL_BASE_BARS,
1651 .num_ports = 2,
1652 .base_baud = 921600,
1653 .uart_offset = 8,
1654 },
1655 [pbn_b2_bt_4_921600] = {
1656 .flags = FL_BASE2|FL_BASE_BARS,
1657 .num_ports = 4,
1658 .base_baud = 921600,
1659 .uart_offset = 8,
1660 },
1661
1662 [pbn_b3_2_115200] = {
1663 .flags = FL_BASE3,
1664 .num_ports = 2,
1665 .base_baud = 115200,
1666 .uart_offset = 8,
1667 },
1668 [pbn_b3_4_115200] = {
1669 .flags = FL_BASE3,
1670 .num_ports = 4,
1671 .base_baud = 115200,
1672 .uart_offset = 8,
1673 },
1674 [pbn_b3_8_115200] = {
1675 .flags = FL_BASE3,
1676 .num_ports = 8,
1677 .base_baud = 115200,
1678 .uart_offset = 8,
1679 },
1680
1681 /*
1682 * Entries following this are board-specific.
1683 */
1684
1685 /*
1686 * Panacom - IOMEM
1687 */
1688 [pbn_panacom] = {
1689 .flags = FL_BASE2,
1690 .num_ports = 2,
1691 .base_baud = 921600,
1692 .uart_offset = 0x400,
1693 .reg_shift = 7,
1694 },
1695 [pbn_panacom2] = {
1696 .flags = FL_BASE2|FL_BASE_BARS,
1697 .num_ports = 2,
1698 .base_baud = 921600,
1699 .uart_offset = 0x400,
1700 .reg_shift = 7,
1701 },
1702 [pbn_panacom4] = {
1703 .flags = FL_BASE2|FL_BASE_BARS,
1704 .num_ports = 4,
1705 .base_baud = 921600,
1706 .uart_offset = 0x400,
1707 .reg_shift = 7,
1708 },
1709
1710 [pbn_exsys_4055] = {
1711 .flags = FL_BASE2,
1712 .num_ports = 4,
1713 .base_baud = 115200,
1714 .uart_offset = 8,
1715 },
1716
1717 /* I think this entry is broken - the first_offset looks wrong --rmk */
1718 [pbn_plx_romulus] = {
1719 .flags = FL_BASE2,
1720 .num_ports = 4,
1721 .base_baud = 921600,
1722 .uart_offset = 8 << 2,
1723 .reg_shift = 2,
1724 .first_offset = 0x03,
1725 },
1726
1727 /*
1728 * This board uses the size of PCI Base region 0 to
1729 * signal now many ports are available
1730 */
1731 [pbn_oxsemi] = {
1732 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1733 .num_ports = 32,
1734 .base_baud = 115200,
1735 .uart_offset = 8,
1736 },
1737 [pbn_oxsemi_1_4000000] = {
1738 .flags = FL_BASE0,
1739 .num_ports = 1,
1740 .base_baud = 4000000,
1741 .uart_offset = 0x200,
1742 .first_offset = 0x1000,
1743 },
1744 [pbn_oxsemi_2_4000000] = {
1745 .flags = FL_BASE0,
1746 .num_ports = 2,
1747 .base_baud = 4000000,
1748 .uart_offset = 0x200,
1749 .first_offset = 0x1000,
1750 },
1751 [pbn_oxsemi_4_4000000] = {
1752 .flags = FL_BASE0,
1753 .num_ports = 4,
1754 .base_baud = 4000000,
1755 .uart_offset = 0x200,
1756 .first_offset = 0x1000,
1757 },
1758 [pbn_oxsemi_8_4000000] = {
1759 .flags = FL_BASE0,
1760 .num_ports = 8,
1761 .base_baud = 4000000,
1762 .uart_offset = 0x200,
1763 .first_offset = 0x1000,
1764 },
1765
1766
1767 /*
1768 * EKF addition for i960 Boards form EKF with serial port.
1769 * Max 256 ports.
1770 */
1771 [pbn_intel_i960] = {
1772 .flags = FL_BASE0,
1773 .num_ports = 32,
1774 .base_baud = 921600,
1775 .uart_offset = 8 << 2,
1776 .reg_shift = 2,
1777 .first_offset = 0x10000,
1778 },
1779 [pbn_sgi_ioc3] = {
1780 .flags = FL_BASE0|FL_NOIRQ,
1781 .num_ports = 1,
1782 .base_baud = 458333,
1783 .uart_offset = 8,
1784 .reg_shift = 0,
1785 .first_offset = 0x20178,
1786 },
1787
1788 /*
1789 * Computone - uses IOMEM.
1790 */
1791 [pbn_computone_4] = {
1792 .flags = FL_BASE0,
1793 .num_ports = 4,
1794 .base_baud = 921600,
1795 .uart_offset = 0x40,
1796 .reg_shift = 2,
1797 .first_offset = 0x200,
1798 },
1799 [pbn_computone_6] = {
1800 .flags = FL_BASE0,
1801 .num_ports = 6,
1802 .base_baud = 921600,
1803 .uart_offset = 0x40,
1804 .reg_shift = 2,
1805 .first_offset = 0x200,
1806 },
1807 [pbn_computone_8] = {
1808 .flags = FL_BASE0,
1809 .num_ports = 8,
1810 .base_baud = 921600,
1811 .uart_offset = 0x40,
1812 .reg_shift = 2,
1813 .first_offset = 0x200,
1814 },
1815 [pbn_sbsxrsio] = {
1816 .flags = FL_BASE0,
1817 .num_ports = 8,
1818 .base_baud = 460800,
1819 .uart_offset = 256,
1820 .reg_shift = 4,
1821 },
1822 /*
1823 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1824 * Only basic 16550A support.
1825 * XR17C15[24] are not tested, but they should work.
1826 */
1827 [pbn_exar_XR17C152] = {
1828 .flags = FL_BASE0,
1829 .num_ports = 2,
1830 .base_baud = 921600,
1831 .uart_offset = 0x200,
1832 },
1833 [pbn_exar_XR17C154] = {
1834 .flags = FL_BASE0,
1835 .num_ports = 4,
1836 .base_baud = 921600,
1837 .uart_offset = 0x200,
1838 },
1839 [pbn_exar_XR17C158] = {
1840 .flags = FL_BASE0,
1841 .num_ports = 8,
1842 .base_baud = 921600,
1843 .uart_offset = 0x200,
1844 },
1845 /*
1846 * PA Semi PWRficient PA6T-1682M on-chip UART
1847 */
1848 [pbn_pasemi_1682M] = {
1849 .flags = FL_BASE0,
1850 .num_ports = 1,
1851 .base_baud = 8333333,
1852 },
1853 };
1854
1855 static const struct pci_device_id softmodem_blacklist[] = {
1856 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
1857 };
1858
1859 /*
1860 * Given a complete unknown PCI device, try to use some heuristics to
1861 * guess what the configuration might be, based on the pitiful PCI
1862 * serial specs. Returns 0 on success, 1 on failure.
1863 */
1864 static int __devinit
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)1865 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1866 {
1867 const struct pci_device_id *blacklist;
1868 int num_iomem, num_port, first_port = -1, i;
1869
1870 /*
1871 * If it is not a communications device or the programming
1872 * interface is greater than 6, give up.
1873 *
1874 * (Should we try to make guesses for multiport serial devices
1875 * later?)
1876 */
1877 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1878 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1879 (dev->class & 0xff) > 6)
1880 return -ENODEV;
1881
1882 /*
1883 * Do not access blacklisted devices that are known not to
1884 * feature serial ports.
1885 */
1886 for (blacklist = softmodem_blacklist;
1887 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1888 blacklist++) {
1889 if (dev->vendor == blacklist->vendor &&
1890 dev->device == blacklist->device)
1891 return -ENODEV;
1892 }
1893
1894 num_iomem = num_port = 0;
1895 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1896 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1897 num_port++;
1898 if (first_port == -1)
1899 first_port = i;
1900 }
1901 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1902 num_iomem++;
1903 }
1904
1905 /*
1906 * If there is 1 or 0 iomem regions, and exactly one port,
1907 * use it. We guess the number of ports based on the IO
1908 * region size.
1909 */
1910 if (num_iomem <= 1 && num_port == 1) {
1911 board->flags = first_port;
1912 board->num_ports = pci_resource_len(dev, first_port) / 8;
1913 return 0;
1914 }
1915
1916 /*
1917 * Now guess if we've got a board which indexes by BARs.
1918 * Each IO BAR should be 8 bytes, and they should follow
1919 * consecutively.
1920 */
1921 first_port = -1;
1922 num_port = 0;
1923 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1924 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1925 pci_resource_len(dev, i) == 8 &&
1926 (first_port == -1 || (first_port + num_port) == i)) {
1927 num_port++;
1928 if (first_port == -1)
1929 first_port = i;
1930 }
1931 }
1932
1933 if (num_port > 1) {
1934 board->flags = first_port | FL_BASE_BARS;
1935 board->num_ports = num_port;
1936 return 0;
1937 }
1938
1939 return -ENODEV;
1940 }
1941
1942 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)1943 serial_pci_matches(const struct pciserial_board *board,
1944 const struct pciserial_board *guessed)
1945 {
1946 return
1947 board->num_ports == guessed->num_ports &&
1948 board->base_baud == guessed->base_baud &&
1949 board->uart_offset == guessed->uart_offset &&
1950 board->reg_shift == guessed->reg_shift &&
1951 board->first_offset == guessed->first_offset;
1952 }
1953
1954 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)1955 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1956 {
1957 struct uart_port serial_port;
1958 struct serial_private *priv;
1959 struct pci_serial_quirk *quirk;
1960 int rc, nr_ports, i;
1961
1962 nr_ports = board->num_ports;
1963
1964 /*
1965 * Find an init and setup quirks.
1966 */
1967 quirk = find_quirk(dev);
1968
1969 /*
1970 * Run the new-style initialization function.
1971 * The initialization function returns:
1972 * <0 - error
1973 * 0 - use board->num_ports
1974 * >0 - number of ports
1975 */
1976 if (quirk->init) {
1977 rc = quirk->init(dev);
1978 if (rc < 0) {
1979 priv = ERR_PTR(rc);
1980 goto err_out;
1981 }
1982 if (rc)
1983 nr_ports = rc;
1984 }
1985
1986 priv = kzalloc(sizeof(struct serial_private) +
1987 sizeof(unsigned int) * nr_ports,
1988 GFP_KERNEL);
1989 if (!priv) {
1990 priv = ERR_PTR(-ENOMEM);
1991 goto err_deinit;
1992 }
1993
1994 priv->dev = dev;
1995 priv->quirk = quirk;
1996
1997 memset(&serial_port, 0, sizeof(struct uart_port));
1998 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1999 serial_port.uartclk = board->base_baud * 16;
2000 serial_port.irq = get_pci_irq(dev, board);
2001 serial_port.dev = &dev->dev;
2002
2003 for (i = 0; i < nr_ports; i++) {
2004 if (quirk->setup(priv, board, &serial_port, i))
2005 break;
2006
2007 #ifdef SERIAL_DEBUG_PCI
2008 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
2009 serial_port.iobase, serial_port.irq, serial_port.iotype);
2010 #endif
2011
2012 priv->line[i] = serial8250_register_port(&serial_port);
2013 if (priv->line[i] < 0) {
2014 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2015 break;
2016 }
2017 }
2018 priv->nr = i;
2019 return priv;
2020
2021 err_deinit:
2022 if (quirk->exit)
2023 quirk->exit(dev);
2024 err_out:
2025 return priv;
2026 }
2027 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2028
pciserial_remove_ports(struct serial_private * priv)2029 void pciserial_remove_ports(struct serial_private *priv)
2030 {
2031 struct pci_serial_quirk *quirk;
2032 int i;
2033
2034 for (i = 0; i < priv->nr; i++)
2035 serial8250_unregister_port(priv->line[i]);
2036
2037 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2038 if (priv->remapped_bar[i])
2039 iounmap(priv->remapped_bar[i]);
2040 priv->remapped_bar[i] = NULL;
2041 }
2042
2043 /*
2044 * Find the exit quirks.
2045 */
2046 quirk = find_quirk(priv->dev);
2047 if (quirk->exit)
2048 quirk->exit(priv->dev);
2049
2050 kfree(priv);
2051 }
2052 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2053
pciserial_suspend_ports(struct serial_private * priv)2054 void pciserial_suspend_ports(struct serial_private *priv)
2055 {
2056 int i;
2057
2058 for (i = 0; i < priv->nr; i++)
2059 if (priv->line[i] >= 0)
2060 serial8250_suspend_port(priv->line[i]);
2061 }
2062 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2063
pciserial_resume_ports(struct serial_private * priv)2064 void pciserial_resume_ports(struct serial_private *priv)
2065 {
2066 int i;
2067
2068 /*
2069 * Ensure that the board is correctly configured.
2070 */
2071 if (priv->quirk->init)
2072 priv->quirk->init(priv->dev);
2073
2074 for (i = 0; i < priv->nr; i++)
2075 if (priv->line[i] >= 0)
2076 serial8250_resume_port(priv->line[i]);
2077 }
2078 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2079
2080 /*
2081 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2082 * to the arrangement of serial ports on a PCI card.
2083 */
2084 static int __devinit
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)2085 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2086 {
2087 struct serial_private *priv;
2088 const struct pciserial_board *board;
2089 struct pciserial_board tmp;
2090 int rc;
2091
2092 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2093 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2094 ent->driver_data);
2095 return -EINVAL;
2096 }
2097
2098 board = &pci_boards[ent->driver_data];
2099
2100 rc = pci_enable_device(dev);
2101 if (rc)
2102 return rc;
2103
2104 if (ent->driver_data == pbn_default) {
2105 /*
2106 * Use a copy of the pci_board entry for this;
2107 * avoid changing entries in the table.
2108 */
2109 memcpy(&tmp, board, sizeof(struct pciserial_board));
2110 board = &tmp;
2111
2112 /*
2113 * We matched one of our class entries. Try to
2114 * determine the parameters of this board.
2115 */
2116 rc = serial_pci_guess_board(dev, &tmp);
2117 if (rc)
2118 goto disable;
2119 } else {
2120 /*
2121 * We matched an explicit entry. If we are able to
2122 * detect this boards settings with our heuristic,
2123 * then we no longer need this entry.
2124 */
2125 memcpy(&tmp, &pci_boards[pbn_default],
2126 sizeof(struct pciserial_board));
2127 rc = serial_pci_guess_board(dev, &tmp);
2128 if (rc == 0 && serial_pci_matches(board, &tmp))
2129 moan_device("Redundant entry in serial pci_table.",
2130 dev);
2131 }
2132
2133 priv = pciserial_init_ports(dev, board);
2134 if (!IS_ERR(priv)) {
2135 pci_set_drvdata(dev, priv);
2136 return 0;
2137 }
2138
2139 rc = PTR_ERR(priv);
2140
2141 disable:
2142 pci_disable_device(dev);
2143 return rc;
2144 }
2145
pciserial_remove_one(struct pci_dev * dev)2146 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2147 {
2148 struct serial_private *priv = pci_get_drvdata(dev);
2149
2150 pci_set_drvdata(dev, NULL);
2151
2152 pciserial_remove_ports(priv);
2153
2154 pci_disable_device(dev);
2155 }
2156
2157 #ifdef CONFIG_PM
pciserial_suspend_one(struct pci_dev * dev,pm_message_t state)2158 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2159 {
2160 struct serial_private *priv = pci_get_drvdata(dev);
2161
2162 if (priv)
2163 pciserial_suspend_ports(priv);
2164
2165 pci_save_state(dev);
2166 pci_set_power_state(dev, pci_choose_state(dev, state));
2167 return 0;
2168 }
2169
pciserial_resume_one(struct pci_dev * dev)2170 static int pciserial_resume_one(struct pci_dev *dev)
2171 {
2172 int err;
2173 struct serial_private *priv = pci_get_drvdata(dev);
2174
2175 pci_set_power_state(dev, PCI_D0);
2176 pci_restore_state(dev);
2177
2178 if (priv) {
2179 /*
2180 * The device may have been disabled. Re-enable it.
2181 */
2182 err = pci_enable_device(dev);
2183 /* FIXME: We cannot simply error out here */
2184 if (err)
2185 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2186 pciserial_resume_ports(priv);
2187 }
2188 return 0;
2189 }
2190 #endif
2191
2192 static struct pci_device_id serial_pci_tbl[] = {
2193 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2194 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2195 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2196 pbn_b2_8_921600 },
2197 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2198 PCI_SUBVENDOR_ID_CONNECT_TECH,
2199 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2200 pbn_b1_8_1382400 },
2201 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2202 PCI_SUBVENDOR_ID_CONNECT_TECH,
2203 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2204 pbn_b1_4_1382400 },
2205 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2206 PCI_SUBVENDOR_ID_CONNECT_TECH,
2207 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2208 pbn_b1_2_1382400 },
2209 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2210 PCI_SUBVENDOR_ID_CONNECT_TECH,
2211 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2212 pbn_b1_8_1382400 },
2213 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2214 PCI_SUBVENDOR_ID_CONNECT_TECH,
2215 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2216 pbn_b1_4_1382400 },
2217 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2218 PCI_SUBVENDOR_ID_CONNECT_TECH,
2219 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2220 pbn_b1_2_1382400 },
2221 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2222 PCI_SUBVENDOR_ID_CONNECT_TECH,
2223 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2224 pbn_b1_8_921600 },
2225 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2226 PCI_SUBVENDOR_ID_CONNECT_TECH,
2227 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2228 pbn_b1_8_921600 },
2229 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2230 PCI_SUBVENDOR_ID_CONNECT_TECH,
2231 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2232 pbn_b1_4_921600 },
2233 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2234 PCI_SUBVENDOR_ID_CONNECT_TECH,
2235 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2236 pbn_b1_4_921600 },
2237 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2238 PCI_SUBVENDOR_ID_CONNECT_TECH,
2239 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2240 pbn_b1_2_921600 },
2241 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2242 PCI_SUBVENDOR_ID_CONNECT_TECH,
2243 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2244 pbn_b1_8_921600 },
2245 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2246 PCI_SUBVENDOR_ID_CONNECT_TECH,
2247 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2248 pbn_b1_8_921600 },
2249 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2250 PCI_SUBVENDOR_ID_CONNECT_TECH,
2251 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2252 pbn_b1_4_921600 },
2253 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2254 PCI_SUBVENDOR_ID_CONNECT_TECH,
2255 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2256 pbn_b1_2_1250000 },
2257 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2258 PCI_SUBVENDOR_ID_CONNECT_TECH,
2259 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2260 pbn_b0_2_1843200 },
2261 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2262 PCI_SUBVENDOR_ID_CONNECT_TECH,
2263 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2264 pbn_b0_4_1843200 },
2265 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2266 PCI_VENDOR_ID_AFAVLAB,
2267 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2268 pbn_b0_4_1152000 },
2269 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2270 PCI_SUBVENDOR_ID_CONNECT_TECH,
2271 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2272 pbn_b0_2_1843200_200 },
2273 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2274 PCI_SUBVENDOR_ID_CONNECT_TECH,
2275 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2276 pbn_b0_4_1843200_200 },
2277 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2278 PCI_SUBVENDOR_ID_CONNECT_TECH,
2279 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2280 pbn_b0_8_1843200_200 },
2281 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2282 PCI_SUBVENDOR_ID_CONNECT_TECH,
2283 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2284 pbn_b0_2_1843200_200 },
2285 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2286 PCI_SUBVENDOR_ID_CONNECT_TECH,
2287 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2288 pbn_b0_4_1843200_200 },
2289 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2290 PCI_SUBVENDOR_ID_CONNECT_TECH,
2291 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2292 pbn_b0_8_1843200_200 },
2293 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2294 PCI_SUBVENDOR_ID_CONNECT_TECH,
2295 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2296 pbn_b0_2_1843200_200 },
2297 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2298 PCI_SUBVENDOR_ID_CONNECT_TECH,
2299 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2300 pbn_b0_4_1843200_200 },
2301 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2302 PCI_SUBVENDOR_ID_CONNECT_TECH,
2303 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2304 pbn_b0_8_1843200_200 },
2305 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2306 PCI_SUBVENDOR_ID_CONNECT_TECH,
2307 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2308 pbn_b0_2_1843200_200 },
2309 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2310 PCI_SUBVENDOR_ID_CONNECT_TECH,
2311 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2312 pbn_b0_4_1843200_200 },
2313 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2314 PCI_SUBVENDOR_ID_CONNECT_TECH,
2315 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2316 pbn_b0_8_1843200_200 },
2317
2318 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2320 pbn_b2_bt_1_115200 },
2321 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2323 pbn_b2_bt_2_115200 },
2324 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2326 pbn_b2_bt_4_115200 },
2327 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2329 pbn_b2_bt_2_115200 },
2330 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2332 pbn_b2_bt_4_115200 },
2333 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2335 pbn_b2_8_115200 },
2336 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2338 pbn_b2_8_460800 },
2339 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2341 pbn_b2_8_115200 },
2342
2343 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2345 pbn_b2_bt_2_115200 },
2346 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2348 pbn_b2_bt_2_921600 },
2349 /*
2350 * VScom SPCOM800, from sl@s.pl
2351 */
2352 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2354 pbn_b2_8_921600 },
2355 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2357 pbn_b2_4_921600 },
2358 /* Unknown card - subdevice 0x1584 */
2359 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2360 PCI_VENDOR_ID_PLX,
2361 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2362 pbn_b0_4_115200 },
2363 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2364 PCI_SUBVENDOR_ID_KEYSPAN,
2365 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2366 pbn_panacom },
2367 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2369 pbn_panacom4 },
2370 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2372 pbn_panacom2 },
2373 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2374 PCI_VENDOR_ID_ESDGMBH,
2375 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2376 pbn_b2_4_115200 },
2377 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2378 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2379 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2380 pbn_b2_4_460800 },
2381 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2382 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2383 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2384 pbn_b2_8_460800 },
2385 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2386 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2387 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2388 pbn_b2_16_460800 },
2389 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2390 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2391 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2392 pbn_b2_16_460800 },
2393 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2394 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2395 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2396 pbn_b2_4_460800 },
2397 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2398 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2399 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2400 pbn_b2_8_460800 },
2401 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2402 PCI_SUBVENDOR_ID_EXSYS,
2403 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2404 pbn_exsys_4055 },
2405 /*
2406 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2407 * (Exoray@isys.ca)
2408 */
2409 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2410 0x10b5, 0x106a, 0, 0,
2411 pbn_plx_romulus },
2412 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2414 pbn_b1_4_115200 },
2415 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2417 pbn_b1_2_115200 },
2418 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2420 pbn_b1_8_115200 },
2421 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2423 pbn_b1_8_115200 },
2424 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2425 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2426 0, 0,
2427 pbn_b0_4_921600 },
2428 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2429 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2430 0, 0,
2431 pbn_b0_4_1152000 },
2432
2433 /*
2434 * The below card is a little controversial since it is the
2435 * subject of a PCI vendor/device ID clash. (See
2436 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2437 * For now just used the hex ID 0x950a.
2438 */
2439 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2440 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2441 pbn_b0_2_115200 },
2442 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2444 pbn_b0_2_1130000 },
2445 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2447 pbn_b0_4_115200 },
2448 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2450 pbn_b0_bt_2_921600 },
2451
2452 /*
2453 * Oxford Semiconductor Inc. Tornado PCI express device range.
2454 */
2455 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2457 pbn_b0_1_4000000 },
2458 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2460 pbn_b0_1_4000000 },
2461 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2463 pbn_oxsemi_1_4000000 },
2464 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2466 pbn_oxsemi_1_4000000 },
2467 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2469 pbn_b0_1_4000000 },
2470 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2472 pbn_b0_1_4000000 },
2473 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2475 pbn_oxsemi_1_4000000 },
2476 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2478 pbn_oxsemi_1_4000000 },
2479 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2481 pbn_b0_1_4000000 },
2482 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2484 pbn_b0_1_4000000 },
2485 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2487 pbn_b0_1_4000000 },
2488 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2490 pbn_b0_1_4000000 },
2491 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2493 pbn_oxsemi_2_4000000 },
2494 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2496 pbn_oxsemi_2_4000000 },
2497 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2499 pbn_oxsemi_4_4000000 },
2500 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2502 pbn_oxsemi_4_4000000 },
2503 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2505 pbn_oxsemi_8_4000000 },
2506 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2508 pbn_oxsemi_8_4000000 },
2509 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2511 pbn_oxsemi_1_4000000 },
2512 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2514 pbn_oxsemi_1_4000000 },
2515 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2517 pbn_oxsemi_1_4000000 },
2518 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2520 pbn_oxsemi_1_4000000 },
2521 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2523 pbn_oxsemi_1_4000000 },
2524 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2526 pbn_oxsemi_1_4000000 },
2527 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2529 pbn_oxsemi_1_4000000 },
2530 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2532 pbn_oxsemi_1_4000000 },
2533 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2535 pbn_oxsemi_1_4000000 },
2536 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2538 pbn_oxsemi_1_4000000 },
2539 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2541 pbn_oxsemi_1_4000000 },
2542 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2544 pbn_oxsemi_1_4000000 },
2545 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2547 pbn_oxsemi_1_4000000 },
2548 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2550 pbn_oxsemi_1_4000000 },
2551 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2553 pbn_oxsemi_1_4000000 },
2554 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2556 pbn_oxsemi_1_4000000 },
2557 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2559 pbn_oxsemi_1_4000000 },
2560 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2562 pbn_oxsemi_1_4000000 },
2563 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2565 pbn_oxsemi_1_4000000 },
2566 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2568 pbn_oxsemi_1_4000000 },
2569 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2571 pbn_oxsemi_1_4000000 },
2572 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2574 pbn_oxsemi_1_4000000 },
2575 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2577 pbn_oxsemi_1_4000000 },
2578 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2580 pbn_oxsemi_1_4000000 },
2581 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2583 pbn_oxsemi_1_4000000 },
2584 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2586 pbn_oxsemi_1_4000000 },
2587 /*
2588 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2589 */
2590 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2591 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2592 pbn_oxsemi_1_4000000 },
2593 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2594 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2595 pbn_oxsemi_2_4000000 },
2596 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2597 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2598 pbn_oxsemi_4_4000000 },
2599 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2600 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2601 pbn_oxsemi_8_4000000 },
2602 /*
2603 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2604 * from skokodyn@yahoo.com
2605 */
2606 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2607 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2608 pbn_sbsxrsio },
2609 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2610 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2611 pbn_sbsxrsio },
2612 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2613 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2614 pbn_sbsxrsio },
2615 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2616 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2617 pbn_sbsxrsio },
2618
2619 /*
2620 * Digitan DS560-558, from jimd@esoft.com
2621 */
2622 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2624 pbn_b1_1_115200 },
2625
2626 /*
2627 * Titan Electronic cards
2628 * The 400L and 800L have a custom setup quirk.
2629 */
2630 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2632 pbn_b0_1_921600 },
2633 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2635 pbn_b0_2_921600 },
2636 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2638 pbn_b0_4_921600 },
2639 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2641 pbn_b0_4_921600 },
2642 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2644 pbn_b1_1_921600 },
2645 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2647 pbn_b1_bt_2_921600 },
2648 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2650 pbn_b0_bt_4_921600 },
2651 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2653 pbn_b0_bt_8_921600 },
2654
2655 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2657 pbn_b2_1_460800 },
2658 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2660 pbn_b2_1_460800 },
2661 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2663 pbn_b2_1_460800 },
2664 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2666 pbn_b2_bt_2_921600 },
2667 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2669 pbn_b2_bt_2_921600 },
2670 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2672 pbn_b2_bt_2_921600 },
2673 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2675 pbn_b2_bt_4_921600 },
2676 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2678 pbn_b2_bt_4_921600 },
2679 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2681 pbn_b2_bt_4_921600 },
2682 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2684 pbn_b0_1_921600 },
2685 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2687 pbn_b0_1_921600 },
2688 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2690 pbn_b0_1_921600 },
2691 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2693 pbn_b0_bt_2_921600 },
2694 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2696 pbn_b0_bt_2_921600 },
2697 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2699 pbn_b0_bt_2_921600 },
2700 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2702 pbn_b0_bt_4_921600 },
2703 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2705 pbn_b0_bt_4_921600 },
2706 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2708 pbn_b0_bt_4_921600 },
2709 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2711 pbn_b0_bt_8_921600 },
2712 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2714 pbn_b0_bt_8_921600 },
2715 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2717 pbn_b0_bt_8_921600 },
2718
2719 /*
2720 * Computone devices submitted by Doug McNash dmcnash@computone.com
2721 */
2722 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2723 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2724 0, 0, pbn_computone_4 },
2725 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2726 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2727 0, 0, pbn_computone_8 },
2728 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2729 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2730 0, 0, pbn_computone_6 },
2731
2732 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2734 pbn_oxsemi },
2735 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2736 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2737 pbn_b0_bt_1_921600 },
2738
2739 /*
2740 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2741 */
2742 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2743 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2744 pbn_b0_bt_8_115200 },
2745 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2747 pbn_b0_bt_8_115200 },
2748
2749 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2751 pbn_b0_bt_2_115200 },
2752 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2754 pbn_b0_bt_2_115200 },
2755 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2757 pbn_b0_bt_2_115200 },
2758 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2760 pbn_b0_bt_4_460800 },
2761 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2763 pbn_b0_bt_4_460800 },
2764 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2766 pbn_b0_bt_2_460800 },
2767 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2769 pbn_b0_bt_2_460800 },
2770 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2772 pbn_b0_bt_2_460800 },
2773 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2775 pbn_b0_bt_1_115200 },
2776 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2778 pbn_b0_bt_1_460800 },
2779
2780 /*
2781 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2782 * Cards are identified by their subsystem vendor IDs, which
2783 * (in hex) match the model number.
2784 *
2785 * Note that JC140x are RS422/485 cards which require ox950
2786 * ACR = 0x10, and as such are not currently fully supported.
2787 */
2788 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2789 0x1204, 0x0004, 0, 0,
2790 pbn_b0_4_921600 },
2791 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2792 0x1208, 0x0004, 0, 0,
2793 pbn_b0_4_921600 },
2794 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2795 0x1402, 0x0002, 0, 0,
2796 pbn_b0_2_921600 }, */
2797 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2798 0x1404, 0x0004, 0, 0,
2799 pbn_b0_4_921600 }, */
2800 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2801 0x1208, 0x0004, 0, 0,
2802 pbn_b0_4_921600 },
2803
2804 /*
2805 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2806 */
2807 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2809 pbn_b1_1_1382400 },
2810
2811 /*
2812 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2813 */
2814 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2816 pbn_b1_1_1382400 },
2817
2818 /*
2819 * RAStel 2 port modem, gerg@moreton.com.au
2820 */
2821 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2823 pbn_b2_bt_2_115200 },
2824
2825 /*
2826 * EKF addition for i960 Boards form EKF with serial port
2827 */
2828 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2829 0xE4BF, PCI_ANY_ID, 0, 0,
2830 pbn_intel_i960 },
2831
2832 /*
2833 * Xircom Cardbus/Ethernet combos
2834 */
2835 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2837 pbn_b0_1_115200 },
2838 /*
2839 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2840 */
2841 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2843 pbn_b0_1_115200 },
2844
2845 /*
2846 * Untested PCI modems, sent in from various folks...
2847 */
2848
2849 /*
2850 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2851 */
2852 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2853 0x1048, 0x1500, 0, 0,
2854 pbn_b1_1_115200 },
2855
2856 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2857 0xFF00, 0, 0, 0,
2858 pbn_sgi_ioc3 },
2859
2860 /*
2861 * HP Diva card
2862 */
2863 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2864 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2865 pbn_b1_1_115200 },
2866 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2868 pbn_b0_5_115200 },
2869 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2871 pbn_b2_1_115200 },
2872
2873 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2875 pbn_b3_2_115200 },
2876 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2878 pbn_b3_4_115200 },
2879 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2881 pbn_b3_8_115200 },
2882
2883 /*
2884 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2885 */
2886 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2887 PCI_ANY_ID, PCI_ANY_ID,
2888 0,
2889 0, pbn_exar_XR17C152 },
2890 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2891 PCI_ANY_ID, PCI_ANY_ID,
2892 0,
2893 0, pbn_exar_XR17C154 },
2894 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2895 PCI_ANY_ID, PCI_ANY_ID,
2896 0,
2897 0, pbn_exar_XR17C158 },
2898
2899 /*
2900 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2901 */
2902 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2904 pbn_b0_1_115200 },
2905 /*
2906 * ITE
2907 */
2908 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2909 PCI_ANY_ID, PCI_ANY_ID,
2910 0, 0,
2911 pbn_b1_bt_1_115200 },
2912
2913 /*
2914 * IntaShield IS-200
2915 */
2916 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2917 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2918 pbn_b2_2_115200 },
2919 /*
2920 * IntaShield IS-400
2921 */
2922 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
2923 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
2924 pbn_b2_4_115200 },
2925 /*
2926 * Perle PCI-RAS cards
2927 */
2928 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2929 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2930 0, 0, pbn_b2_4_921600 },
2931 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2932 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2933 0, 0, pbn_b2_8_921600 },
2934
2935 /*
2936 * Mainpine series cards: Fairly standard layout but fools
2937 * parts of the autodetect in some cases and uses otherwise
2938 * unmatched communications subclasses in the PCI Express case
2939 */
2940
2941 { /* RockForceDUO */
2942 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2943 PCI_VENDOR_ID_MAINPINE, 0x0200,
2944 0, 0, pbn_b0_2_115200 },
2945 { /* RockForceQUATRO */
2946 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2947 PCI_VENDOR_ID_MAINPINE, 0x0300,
2948 0, 0, pbn_b0_4_115200 },
2949 { /* RockForceDUO+ */
2950 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2951 PCI_VENDOR_ID_MAINPINE, 0x0400,
2952 0, 0, pbn_b0_2_115200 },
2953 { /* RockForceQUATRO+ */
2954 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2955 PCI_VENDOR_ID_MAINPINE, 0x0500,
2956 0, 0, pbn_b0_4_115200 },
2957 { /* RockForce+ */
2958 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2959 PCI_VENDOR_ID_MAINPINE, 0x0600,
2960 0, 0, pbn_b0_2_115200 },
2961 { /* RockForce+ */
2962 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2963 PCI_VENDOR_ID_MAINPINE, 0x0700,
2964 0, 0, pbn_b0_4_115200 },
2965 { /* RockForceOCTO+ */
2966 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2967 PCI_VENDOR_ID_MAINPINE, 0x0800,
2968 0, 0, pbn_b0_8_115200 },
2969 { /* RockForceDUO+ */
2970 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2971 PCI_VENDOR_ID_MAINPINE, 0x0C00,
2972 0, 0, pbn_b0_2_115200 },
2973 { /* RockForceQUARTRO+ */
2974 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2975 PCI_VENDOR_ID_MAINPINE, 0x0D00,
2976 0, 0, pbn_b0_4_115200 },
2977 { /* RockForceOCTO+ */
2978 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2979 PCI_VENDOR_ID_MAINPINE, 0x1D00,
2980 0, 0, pbn_b0_8_115200 },
2981 { /* RockForceD1 */
2982 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2983 PCI_VENDOR_ID_MAINPINE, 0x2000,
2984 0, 0, pbn_b0_1_115200 },
2985 { /* RockForceF1 */
2986 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2987 PCI_VENDOR_ID_MAINPINE, 0x2100,
2988 0, 0, pbn_b0_1_115200 },
2989 { /* RockForceD2 */
2990 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2991 PCI_VENDOR_ID_MAINPINE, 0x2200,
2992 0, 0, pbn_b0_2_115200 },
2993 { /* RockForceF2 */
2994 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2995 PCI_VENDOR_ID_MAINPINE, 0x2300,
2996 0, 0, pbn_b0_2_115200 },
2997 { /* RockForceD4 */
2998 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2999 PCI_VENDOR_ID_MAINPINE, 0x2400,
3000 0, 0, pbn_b0_4_115200 },
3001 { /* RockForceF4 */
3002 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3003 PCI_VENDOR_ID_MAINPINE, 0x2500,
3004 0, 0, pbn_b0_4_115200 },
3005 { /* RockForceD8 */
3006 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3007 PCI_VENDOR_ID_MAINPINE, 0x2600,
3008 0, 0, pbn_b0_8_115200 },
3009 { /* RockForceF8 */
3010 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3011 PCI_VENDOR_ID_MAINPINE, 0x2700,
3012 0, 0, pbn_b0_8_115200 },
3013 { /* IQ Express D1 */
3014 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3015 PCI_VENDOR_ID_MAINPINE, 0x3000,
3016 0, 0, pbn_b0_1_115200 },
3017 { /* IQ Express F1 */
3018 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3019 PCI_VENDOR_ID_MAINPINE, 0x3100,
3020 0, 0, pbn_b0_1_115200 },
3021 { /* IQ Express D2 */
3022 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3023 PCI_VENDOR_ID_MAINPINE, 0x3200,
3024 0, 0, pbn_b0_2_115200 },
3025 { /* IQ Express F2 */
3026 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3027 PCI_VENDOR_ID_MAINPINE, 0x3300,
3028 0, 0, pbn_b0_2_115200 },
3029 { /* IQ Express D4 */
3030 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3031 PCI_VENDOR_ID_MAINPINE, 0x3400,
3032 0, 0, pbn_b0_4_115200 },
3033 { /* IQ Express F4 */
3034 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3035 PCI_VENDOR_ID_MAINPINE, 0x3500,
3036 0, 0, pbn_b0_4_115200 },
3037 { /* IQ Express D8 */
3038 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3039 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3040 0, 0, pbn_b0_8_115200 },
3041 { /* IQ Express F8 */
3042 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3043 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3044 0, 0, pbn_b0_8_115200 },
3045
3046
3047 /*
3048 * PA Semi PA6T-1682M on-chip UART
3049 */
3050 { PCI_VENDOR_ID_PASEMI, 0xa004,
3051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3052 pbn_pasemi_1682M },
3053
3054 /*
3055 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3056 */
3057 { PCI_VENDOR_ID_ADDIDATA,
3058 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3059 PCI_ANY_ID,
3060 PCI_ANY_ID,
3061 0,
3062 0,
3063 pbn_b0_4_115200 },
3064
3065 { PCI_VENDOR_ID_ADDIDATA,
3066 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3067 PCI_ANY_ID,
3068 PCI_ANY_ID,
3069 0,
3070 0,
3071 pbn_b0_2_115200 },
3072
3073 { PCI_VENDOR_ID_ADDIDATA,
3074 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3075 PCI_ANY_ID,
3076 PCI_ANY_ID,
3077 0,
3078 0,
3079 pbn_b0_1_115200 },
3080
3081 { PCI_VENDOR_ID_ADDIDATA_OLD,
3082 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3083 PCI_ANY_ID,
3084 PCI_ANY_ID,
3085 0,
3086 0,
3087 pbn_b1_8_115200 },
3088
3089 { PCI_VENDOR_ID_ADDIDATA,
3090 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3091 PCI_ANY_ID,
3092 PCI_ANY_ID,
3093 0,
3094 0,
3095 pbn_b0_4_115200 },
3096
3097 { PCI_VENDOR_ID_ADDIDATA,
3098 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3099 PCI_ANY_ID,
3100 PCI_ANY_ID,
3101 0,
3102 0,
3103 pbn_b0_2_115200 },
3104
3105 { PCI_VENDOR_ID_ADDIDATA,
3106 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3107 PCI_ANY_ID,
3108 PCI_ANY_ID,
3109 0,
3110 0,
3111 pbn_b0_1_115200 },
3112
3113 { PCI_VENDOR_ID_ADDIDATA,
3114 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3115 PCI_ANY_ID,
3116 PCI_ANY_ID,
3117 0,
3118 0,
3119 pbn_b0_4_115200 },
3120
3121 { PCI_VENDOR_ID_ADDIDATA,
3122 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3123 PCI_ANY_ID,
3124 PCI_ANY_ID,
3125 0,
3126 0,
3127 pbn_b0_2_115200 },
3128
3129 { PCI_VENDOR_ID_ADDIDATA,
3130 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3131 PCI_ANY_ID,
3132 PCI_ANY_ID,
3133 0,
3134 0,
3135 pbn_b0_1_115200 },
3136
3137 { PCI_VENDOR_ID_ADDIDATA,
3138 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3139 PCI_ANY_ID,
3140 PCI_ANY_ID,
3141 0,
3142 0,
3143 pbn_b0_8_115200 },
3144
3145 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3146 PCI_VENDOR_ID_IBM, 0x0299,
3147 0, 0, pbn_b0_bt_2_115200 },
3148
3149 /*
3150 * These entries match devices with class COMMUNICATION_SERIAL,
3151 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3152 */
3153 { PCI_ANY_ID, PCI_ANY_ID,
3154 PCI_ANY_ID, PCI_ANY_ID,
3155 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3156 0xffff00, pbn_default },
3157 { PCI_ANY_ID, PCI_ANY_ID,
3158 PCI_ANY_ID, PCI_ANY_ID,
3159 PCI_CLASS_COMMUNICATION_MODEM << 8,
3160 0xffff00, pbn_default },
3161 { PCI_ANY_ID, PCI_ANY_ID,
3162 PCI_ANY_ID, PCI_ANY_ID,
3163 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3164 0xffff00, pbn_default },
3165 { 0, }
3166 };
3167
3168 static struct pci_driver serial_pci_driver = {
3169 .name = "serial",
3170 .probe = pciserial_init_one,
3171 .remove = __devexit_p(pciserial_remove_one),
3172 #ifdef CONFIG_PM
3173 .suspend = pciserial_suspend_one,
3174 .resume = pciserial_resume_one,
3175 #endif
3176 .id_table = serial_pci_tbl,
3177 };
3178
serial8250_pci_init(void)3179 static int __init serial8250_pci_init(void)
3180 {
3181 return pci_register_driver(&serial_pci_driver);
3182 }
3183
serial8250_pci_exit(void)3184 static void __exit serial8250_pci_exit(void)
3185 {
3186 pci_unregister_driver(&serial_pci_driver);
3187 }
3188
3189 module_init(serial8250_pci_init);
3190 module_exit(serial8250_pci_exit);
3191
3192 MODULE_LICENSE("GPL");
3193 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3194 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
3195