1 /*
2 * au1550_spi.c - au1550 psc spi controller driver
3 * may work also with au1200, au1210, au1250
4 * will not work on au1000, au1100 and au1500 (no full spi controller there)
5 *
6 * Copyright (c) 2006 ATRON electronic GmbH
7 * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/errno.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/resource.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/completion.h>
34 #include <asm/mach-au1x00/au1000.h>
35 #include <asm/mach-au1x00/au1xxx_psc.h>
36 #include <asm/mach-au1x00/au1xxx_dbdma.h>
37
38 #include <asm/mach-au1x00/au1550_spi.h>
39
40 static unsigned usedma = 1;
41 module_param(usedma, uint, 0644);
42
43 /*
44 #define AU1550_SPI_DEBUG_LOOPBACK
45 */
46
47
48 #define AU1550_SPI_DBDMA_DESCRIPTORS 1
49 #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
50
51 struct au1550_spi {
52 struct spi_bitbang bitbang;
53
54 volatile psc_spi_t __iomem *regs;
55 int irq;
56 unsigned freq_max;
57 unsigned freq_min;
58
59 unsigned len;
60 unsigned tx_count;
61 unsigned rx_count;
62 const u8 *tx;
63 u8 *rx;
64
65 void (*rx_word)(struct au1550_spi *hw);
66 void (*tx_word)(struct au1550_spi *hw);
67 int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
68 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
69
70 struct completion master_done;
71
72 unsigned usedma;
73 u32 dma_tx_id;
74 u32 dma_rx_id;
75 u32 dma_tx_ch;
76 u32 dma_rx_ch;
77
78 u8 *dma_rx_tmpbuf;
79 unsigned dma_rx_tmpbuf_size;
80 u32 dma_rx_tmpbuf_addr;
81
82 struct spi_master *master;
83 struct device *dev;
84 struct au1550_spi_info *pdata;
85 struct resource *ioarea;
86 };
87
88
89 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
90 static dbdev_tab_t au1550_spi_mem_dbdev =
91 {
92 .dev_id = DBDMA_MEM_CHAN,
93 .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
94 .dev_tsize = 0,
95 .dev_devwidth = 8,
96 .dev_physaddr = 0x00000000,
97 .dev_intlevel = 0,
98 .dev_intpolarity = 0
99 };
100
101 static int ddma_memid; /* id to above mem dma device */
102
103 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
104
105
106 /*
107 * compute BRG and DIV bits to setup spi clock based on main input clock rate
108 * that was specified in platform data structure
109 * according to au1550 datasheet:
110 * psc_tempclk = psc_mainclk / (2 << DIV)
111 * spiclk = psc_tempclk / (2 * (BRG + 1))
112 * BRG valid range is 4..63
113 * DIV valid range is 0..3
114 */
au1550_spi_baudcfg(struct au1550_spi * hw,unsigned speed_hz)115 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
116 {
117 u32 mainclk_hz = hw->pdata->mainclk_hz;
118 u32 div, brg;
119
120 for (div = 0; div < 4; div++) {
121 brg = mainclk_hz / speed_hz / (4 << div);
122 /* now we have BRG+1 in brg, so count with that */
123 if (brg < (4 + 1)) {
124 brg = (4 + 1); /* speed_hz too big */
125 break; /* set lowest brg (div is == 0) */
126 }
127 if (brg <= (63 + 1))
128 break; /* we have valid brg and div */
129 }
130 if (div == 4) {
131 div = 3; /* speed_hz too small */
132 brg = (63 + 1); /* set highest brg and div */
133 }
134 brg--;
135 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
136 }
137
au1550_spi_mask_ack_all(struct au1550_spi * hw)138 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
139 {
140 hw->regs->psc_spimsk =
141 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
142 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
143 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
144 au_sync();
145
146 hw->regs->psc_spievent =
147 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
148 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
149 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
150 au_sync();
151 }
152
au1550_spi_reset_fifos(struct au1550_spi * hw)153 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
154 {
155 u32 pcr;
156
157 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
158 au_sync();
159 do {
160 pcr = hw->regs->psc_spipcr;
161 au_sync();
162 } while (pcr != 0);
163 }
164
165 /*
166 * dma transfers are used for the most common spi word size of 8-bits
167 * we cannot easily change already set up dma channels' width, so if we wanted
168 * dma support for more than 8-bit words (up to 24 bits), we would need to
169 * setup dma channels from scratch on each spi transfer, based on bits_per_word
170 * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
171 * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
172 * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
173 */
au1550_spi_chipsel(struct spi_device * spi,int value)174 static void au1550_spi_chipsel(struct spi_device *spi, int value)
175 {
176 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
177 unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
178 u32 cfg, stat;
179
180 switch (value) {
181 case BITBANG_CS_INACTIVE:
182 if (hw->pdata->deactivate_cs)
183 hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
184 cspol);
185 break;
186
187 case BITBANG_CS_ACTIVE:
188 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
189
190 cfg = hw->regs->psc_spicfg;
191 au_sync();
192 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
193 au_sync();
194
195 if (spi->mode & SPI_CPOL)
196 cfg |= PSC_SPICFG_BI;
197 else
198 cfg &= ~PSC_SPICFG_BI;
199 if (spi->mode & SPI_CPHA)
200 cfg &= ~PSC_SPICFG_CDE;
201 else
202 cfg |= PSC_SPICFG_CDE;
203
204 if (spi->mode & SPI_LSB_FIRST)
205 cfg |= PSC_SPICFG_MLF;
206 else
207 cfg &= ~PSC_SPICFG_MLF;
208
209 if (hw->usedma && spi->bits_per_word <= 8)
210 cfg &= ~PSC_SPICFG_DD_DISABLE;
211 else
212 cfg |= PSC_SPICFG_DD_DISABLE;
213 cfg = PSC_SPICFG_CLR_LEN(cfg);
214 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
215
216 cfg = PSC_SPICFG_CLR_BAUD(cfg);
217 cfg &= ~PSC_SPICFG_SET_DIV(3);
218 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
219
220 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
221 au_sync();
222 do {
223 stat = hw->regs->psc_spistat;
224 au_sync();
225 } while ((stat & PSC_SPISTAT_DR) == 0);
226
227 if (hw->pdata->activate_cs)
228 hw->pdata->activate_cs(hw->pdata, spi->chip_select,
229 cspol);
230 break;
231 }
232 }
233
au1550_spi_setupxfer(struct spi_device * spi,struct spi_transfer * t)234 static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
235 {
236 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
237 unsigned bpw, hz;
238 u32 cfg, stat;
239
240 bpw = t ? t->bits_per_word : spi->bits_per_word;
241 hz = t ? t->speed_hz : spi->max_speed_hz;
242
243 if (bpw < 4 || bpw > 24) {
244 dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
245 bpw);
246 return -EINVAL;
247 }
248 if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
249 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
250 hz);
251 return -EINVAL;
252 }
253
254 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
255
256 cfg = hw->regs->psc_spicfg;
257 au_sync();
258 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
259 au_sync();
260
261 if (hw->usedma && bpw <= 8)
262 cfg &= ~PSC_SPICFG_DD_DISABLE;
263 else
264 cfg |= PSC_SPICFG_DD_DISABLE;
265 cfg = PSC_SPICFG_CLR_LEN(cfg);
266 cfg |= PSC_SPICFG_SET_LEN(bpw);
267
268 cfg = PSC_SPICFG_CLR_BAUD(cfg);
269 cfg &= ~PSC_SPICFG_SET_DIV(3);
270 cfg |= au1550_spi_baudcfg(hw, hz);
271
272 hw->regs->psc_spicfg = cfg;
273 au_sync();
274
275 if (cfg & PSC_SPICFG_DE_ENABLE) {
276 do {
277 stat = hw->regs->psc_spistat;
278 au_sync();
279 } while ((stat & PSC_SPISTAT_DR) == 0);
280 }
281
282 au1550_spi_reset_fifos(hw);
283 au1550_spi_mask_ack_all(hw);
284 return 0;
285 }
286
287 /* the spi->mode bits understood by this driver: */
288 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST)
289
au1550_spi_setup(struct spi_device * spi)290 static int au1550_spi_setup(struct spi_device *spi)
291 {
292 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
293
294 if (spi->bits_per_word == 0)
295 spi->bits_per_word = 8;
296 if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
297 dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
298 spi->bits_per_word);
299 return -EINVAL;
300 }
301
302 if (spi->mode & ~MODEBITS) {
303 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
304 spi->mode & ~MODEBITS);
305 return -EINVAL;
306 }
307
308 if (spi->max_speed_hz == 0)
309 spi->max_speed_hz = hw->freq_max;
310 if (spi->max_speed_hz > hw->freq_max
311 || spi->max_speed_hz < hw->freq_min)
312 return -EINVAL;
313 /*
314 * NOTE: cannot change speed and other hw settings immediately,
315 * otherwise sharing of spi bus is not possible,
316 * so do not call setupxfer(spi, NULL) here
317 */
318 return 0;
319 }
320
321 /*
322 * for dma spi transfers, we have to setup rx channel, otherwise there is
323 * no reliable way how to recognize that spi transfer is done
324 * dma complete callbacks are called before real spi transfer is finished
325 * and if only tx dma channel is set up (and rx fifo overflow event masked)
326 * spi master done event irq is not generated unless rx fifo is empty (emptied)
327 * so we need rx tmp buffer to use for rx dma if user does not provide one
328 */
au1550_spi_dma_rxtmp_alloc(struct au1550_spi * hw,unsigned size)329 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
330 {
331 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
332 if (!hw->dma_rx_tmpbuf)
333 return -ENOMEM;
334 hw->dma_rx_tmpbuf_size = size;
335 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
336 size, DMA_FROM_DEVICE);
337 if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
338 kfree(hw->dma_rx_tmpbuf);
339 hw->dma_rx_tmpbuf = 0;
340 hw->dma_rx_tmpbuf_size = 0;
341 return -EFAULT;
342 }
343 return 0;
344 }
345
au1550_spi_dma_rxtmp_free(struct au1550_spi * hw)346 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
347 {
348 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
349 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
350 kfree(hw->dma_rx_tmpbuf);
351 hw->dma_rx_tmpbuf = 0;
352 hw->dma_rx_tmpbuf_size = 0;
353 }
354
au1550_spi_dma_txrxb(struct spi_device * spi,struct spi_transfer * t)355 static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
356 {
357 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
358 dma_addr_t dma_tx_addr;
359 dma_addr_t dma_rx_addr;
360 u32 res;
361
362 hw->len = t->len;
363 hw->tx_count = 0;
364 hw->rx_count = 0;
365
366 hw->tx = t->tx_buf;
367 hw->rx = t->rx_buf;
368 dma_tx_addr = t->tx_dma;
369 dma_rx_addr = t->rx_dma;
370
371 /*
372 * check if buffers are already dma mapped, map them otherwise:
373 * - first map the TX buffer, so cache data gets written to memory
374 * - then map the RX buffer, so that cache entries (with
375 * soon-to-be-stale data) get removed
376 * use rx buffer in place of tx if tx buffer was not provided
377 * use temp rx buffer (preallocated or realloc to fit) for rx dma
378 */
379 if (t->tx_buf) {
380 if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
381 dma_tx_addr = dma_map_single(hw->dev,
382 (void *)t->tx_buf,
383 t->len, DMA_TO_DEVICE);
384 if (dma_mapping_error(hw->dev, dma_tx_addr))
385 dev_err(hw->dev, "tx dma map error\n");
386 }
387 }
388
389 if (t->rx_buf) {
390 if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
391 dma_rx_addr = dma_map_single(hw->dev,
392 (void *)t->rx_buf,
393 t->len, DMA_FROM_DEVICE);
394 if (dma_mapping_error(hw->dev, dma_rx_addr))
395 dev_err(hw->dev, "rx dma map error\n");
396 }
397 } else {
398 if (t->len > hw->dma_rx_tmpbuf_size) {
399 int ret;
400
401 au1550_spi_dma_rxtmp_free(hw);
402 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
403 AU1550_SPI_DMA_RXTMP_MINSIZE));
404 if (ret < 0)
405 return ret;
406 }
407 hw->rx = hw->dma_rx_tmpbuf;
408 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
409 dma_sync_single_for_device(hw->dev, dma_rx_addr,
410 t->len, DMA_FROM_DEVICE);
411 }
412
413 if (!t->tx_buf) {
414 dma_sync_single_for_device(hw->dev, dma_rx_addr,
415 t->len, DMA_BIDIRECTIONAL);
416 hw->tx = hw->rx;
417 }
418
419 /* put buffers on the ring */
420 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len);
421 if (!res)
422 dev_err(hw->dev, "rx dma put dest error\n");
423
424 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len);
425 if (!res)
426 dev_err(hw->dev, "tx dma put source error\n");
427
428 au1xxx_dbdma_start(hw->dma_rx_ch);
429 au1xxx_dbdma_start(hw->dma_tx_ch);
430
431 /* by default enable nearly all events interrupt */
432 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
433 au_sync();
434
435 /* start the transfer */
436 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
437 au_sync();
438
439 wait_for_completion(&hw->master_done);
440
441 au1xxx_dbdma_stop(hw->dma_tx_ch);
442 au1xxx_dbdma_stop(hw->dma_rx_ch);
443
444 if (!t->rx_buf) {
445 /* using the temporal preallocated and premapped buffer */
446 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
447 DMA_FROM_DEVICE);
448 }
449 /* unmap buffers if mapped above */
450 if (t->rx_buf && t->rx_dma == 0 )
451 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
452 DMA_FROM_DEVICE);
453 if (t->tx_buf && t->tx_dma == 0 )
454 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
455 DMA_TO_DEVICE);
456
457 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
458 }
459
au1550_spi_dma_irq_callback(struct au1550_spi * hw)460 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
461 {
462 u32 stat, evnt;
463
464 stat = hw->regs->psc_spistat;
465 evnt = hw->regs->psc_spievent;
466 au_sync();
467 if ((stat & PSC_SPISTAT_DI) == 0) {
468 dev_err(hw->dev, "Unexpected IRQ!\n");
469 return IRQ_NONE;
470 }
471
472 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
473 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
474 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
475 != 0) {
476 /*
477 * due to an spi error we consider transfer as done,
478 * so mask all events until before next transfer start
479 * and stop the possibly running dma immediatelly
480 */
481 au1550_spi_mask_ack_all(hw);
482 au1xxx_dbdma_stop(hw->dma_rx_ch);
483 au1xxx_dbdma_stop(hw->dma_tx_ch);
484
485 /* get number of transfered bytes */
486 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
487 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
488
489 au1xxx_dbdma_reset(hw->dma_rx_ch);
490 au1xxx_dbdma_reset(hw->dma_tx_ch);
491 au1550_spi_reset_fifos(hw);
492
493 if (evnt == PSC_SPIEVNT_RO)
494 dev_err(hw->dev,
495 "dma transfer: receive FIFO overflow!\n");
496 else
497 dev_err(hw->dev,
498 "dma transfer: unexpected SPI error "
499 "(event=0x%x stat=0x%x)!\n", evnt, stat);
500
501 complete(&hw->master_done);
502 return IRQ_HANDLED;
503 }
504
505 if ((evnt & PSC_SPIEVNT_MD) != 0) {
506 /* transfer completed successfully */
507 au1550_spi_mask_ack_all(hw);
508 hw->rx_count = hw->len;
509 hw->tx_count = hw->len;
510 complete(&hw->master_done);
511 }
512 return IRQ_HANDLED;
513 }
514
515
516 /* routines to handle different word sizes in pio mode */
517 #define AU1550_SPI_RX_WORD(size, mask) \
518 static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
519 { \
520 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
521 au_sync(); \
522 if (hw->rx) { \
523 *(u##size *)hw->rx = (u##size)fifoword; \
524 hw->rx += (size) / 8; \
525 } \
526 hw->rx_count += (size) / 8; \
527 }
528
529 #define AU1550_SPI_TX_WORD(size, mask) \
530 static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
531 { \
532 u32 fifoword = 0; \
533 if (hw->tx) { \
534 fifoword = *(u##size *)hw->tx & (u32)(mask); \
535 hw->tx += (size) / 8; \
536 } \
537 hw->tx_count += (size) / 8; \
538 if (hw->tx_count >= hw->len) \
539 fifoword |= PSC_SPITXRX_LC; \
540 hw->regs->psc_spitxrx = fifoword; \
541 au_sync(); \
542 }
543
544 AU1550_SPI_RX_WORD(8,0xff)
545 AU1550_SPI_RX_WORD(16,0xffff)
546 AU1550_SPI_RX_WORD(32,0xffffff)
547 AU1550_SPI_TX_WORD(8,0xff)
548 AU1550_SPI_TX_WORD(16,0xffff)
549 AU1550_SPI_TX_WORD(32,0xffffff)
550
au1550_spi_pio_txrxb(struct spi_device * spi,struct spi_transfer * t)551 static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
552 {
553 u32 stat, mask;
554 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
555
556 hw->tx = t->tx_buf;
557 hw->rx = t->rx_buf;
558 hw->len = t->len;
559 hw->tx_count = 0;
560 hw->rx_count = 0;
561
562 /* by default enable nearly all events after filling tx fifo */
563 mask = PSC_SPIMSK_SD;
564
565 /* fill the transmit FIFO */
566 while (hw->tx_count < hw->len) {
567
568 hw->tx_word(hw);
569
570 if (hw->tx_count >= hw->len) {
571 /* mask tx fifo request interrupt as we are done */
572 mask |= PSC_SPIMSK_TR;
573 }
574
575 stat = hw->regs->psc_spistat;
576 au_sync();
577 if (stat & PSC_SPISTAT_TF)
578 break;
579 }
580
581 /* enable event interrupts */
582 hw->regs->psc_spimsk = mask;
583 au_sync();
584
585 /* start the transfer */
586 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
587 au_sync();
588
589 wait_for_completion(&hw->master_done);
590
591 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
592 }
593
au1550_spi_pio_irq_callback(struct au1550_spi * hw)594 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
595 {
596 int busy;
597 u32 stat, evnt;
598
599 stat = hw->regs->psc_spistat;
600 evnt = hw->regs->psc_spievent;
601 au_sync();
602 if ((stat & PSC_SPISTAT_DI) == 0) {
603 dev_err(hw->dev, "Unexpected IRQ!\n");
604 return IRQ_NONE;
605 }
606
607 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
608 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
609 | PSC_SPIEVNT_SD))
610 != 0) {
611 /*
612 * due to an error we consider transfer as done,
613 * so mask all events until before next transfer start
614 */
615 au1550_spi_mask_ack_all(hw);
616 au1550_spi_reset_fifos(hw);
617 dev_err(hw->dev,
618 "pio transfer: unexpected SPI error "
619 "(event=0x%x stat=0x%x)!\n", evnt, stat);
620 complete(&hw->master_done);
621 return IRQ_HANDLED;
622 }
623
624 /*
625 * while there is something to read from rx fifo
626 * or there is a space to write to tx fifo:
627 */
628 do {
629 busy = 0;
630 stat = hw->regs->psc_spistat;
631 au_sync();
632
633 /*
634 * Take care to not let the Rx FIFO overflow.
635 *
636 * We only write a byte if we have read one at least. Initially,
637 * the write fifo is full, so we should read from the read fifo
638 * first.
639 * In case we miss a word from the read fifo, we should get a
640 * RO event and should back out.
641 */
642 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
643 hw->rx_word(hw);
644 busy = 1;
645
646 if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
647 hw->tx_word(hw);
648 }
649 } while (busy);
650
651 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
652 au_sync();
653
654 /*
655 * Restart the SPI transmission in case of a transmit underflow.
656 * This seems to work despite the notes in the Au1550 data book
657 * of Figure 8-4 with flowchart for SPI master operation:
658 *
659 * """Note 1: An XFR Error Interrupt occurs, unless masked,
660 * for any of the following events: Tx FIFO Underflow,
661 * Rx FIFO Overflow, or Multiple-master Error
662 * Note 2: In case of a Tx Underflow Error, all zeroes are
663 * transmitted."""
664 *
665 * By simply restarting the spi transfer on Tx Underflow Error,
666 * we assume that spi transfer was paused instead of zeroes
667 * transmittion mentioned in the Note 2 of Au1550 data book.
668 */
669 if (evnt & PSC_SPIEVNT_TU) {
670 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
671 au_sync();
672 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
673 au_sync();
674 }
675
676 if (hw->rx_count >= hw->len) {
677 /* transfer completed successfully */
678 au1550_spi_mask_ack_all(hw);
679 complete(&hw->master_done);
680 }
681 return IRQ_HANDLED;
682 }
683
au1550_spi_txrx_bufs(struct spi_device * spi,struct spi_transfer * t)684 static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
685 {
686 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
687 return hw->txrx_bufs(spi, t);
688 }
689
au1550_spi_irq(int irq,void * dev)690 static irqreturn_t au1550_spi_irq(int irq, void *dev)
691 {
692 struct au1550_spi *hw = dev;
693 return hw->irq_callback(hw);
694 }
695
au1550_spi_bits_handlers_set(struct au1550_spi * hw,int bpw)696 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
697 {
698 if (bpw <= 8) {
699 if (hw->usedma) {
700 hw->txrx_bufs = &au1550_spi_dma_txrxb;
701 hw->irq_callback = &au1550_spi_dma_irq_callback;
702 } else {
703 hw->rx_word = &au1550_spi_rx_word_8;
704 hw->tx_word = &au1550_spi_tx_word_8;
705 hw->txrx_bufs = &au1550_spi_pio_txrxb;
706 hw->irq_callback = &au1550_spi_pio_irq_callback;
707 }
708 } else if (bpw <= 16) {
709 hw->rx_word = &au1550_spi_rx_word_16;
710 hw->tx_word = &au1550_spi_tx_word_16;
711 hw->txrx_bufs = &au1550_spi_pio_txrxb;
712 hw->irq_callback = &au1550_spi_pio_irq_callback;
713 } else {
714 hw->rx_word = &au1550_spi_rx_word_32;
715 hw->tx_word = &au1550_spi_tx_word_32;
716 hw->txrx_bufs = &au1550_spi_pio_txrxb;
717 hw->irq_callback = &au1550_spi_pio_irq_callback;
718 }
719 }
720
au1550_spi_setup_psc_as_spi(struct au1550_spi * hw)721 static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
722 {
723 u32 stat, cfg;
724
725 /* set up the PSC for SPI mode */
726 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
727 au_sync();
728 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
729 au_sync();
730
731 hw->regs->psc_spicfg = 0;
732 au_sync();
733
734 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
735 au_sync();
736
737 do {
738 stat = hw->regs->psc_spistat;
739 au_sync();
740 } while ((stat & PSC_SPISTAT_SR) == 0);
741
742
743 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
744 cfg |= PSC_SPICFG_SET_LEN(8);
745 cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
746 /* use minimal allowed brg and div values as initial setting: */
747 cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
748
749 #ifdef AU1550_SPI_DEBUG_LOOPBACK
750 cfg |= PSC_SPICFG_LB;
751 #endif
752
753 hw->regs->psc_spicfg = cfg;
754 au_sync();
755
756 au1550_spi_mask_ack_all(hw);
757
758 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
759 au_sync();
760
761 do {
762 stat = hw->regs->psc_spistat;
763 au_sync();
764 } while ((stat & PSC_SPISTAT_DR) == 0);
765
766 au1550_spi_reset_fifos(hw);
767 }
768
769
au1550_spi_probe(struct platform_device * pdev)770 static int __init au1550_spi_probe(struct platform_device *pdev)
771 {
772 struct au1550_spi *hw;
773 struct spi_master *master;
774 struct resource *r;
775 int err = 0;
776
777 master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
778 if (master == NULL) {
779 dev_err(&pdev->dev, "No memory for spi_master\n");
780 err = -ENOMEM;
781 goto err_nomem;
782 }
783
784 hw = spi_master_get_devdata(master);
785
786 hw->master = spi_master_get(master);
787 hw->pdata = pdev->dev.platform_data;
788 hw->dev = &pdev->dev;
789
790 if (hw->pdata == NULL) {
791 dev_err(&pdev->dev, "No platform data supplied\n");
792 err = -ENOENT;
793 goto err_no_pdata;
794 }
795
796 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
797 if (!r) {
798 dev_err(&pdev->dev, "no IRQ\n");
799 err = -ENODEV;
800 goto err_no_iores;
801 }
802 hw->irq = r->start;
803
804 hw->usedma = 0;
805 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
806 if (r) {
807 hw->dma_tx_id = r->start;
808 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
809 if (r) {
810 hw->dma_rx_id = r->start;
811 if (usedma && ddma_memid) {
812 if (pdev->dev.dma_mask == NULL)
813 dev_warn(&pdev->dev, "no dma mask\n");
814 else
815 hw->usedma = 1;
816 }
817 }
818 }
819
820 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
821 if (!r) {
822 dev_err(&pdev->dev, "no mmio resource\n");
823 err = -ENODEV;
824 goto err_no_iores;
825 }
826
827 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
828 pdev->name);
829 if (!hw->ioarea) {
830 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
831 err = -ENXIO;
832 goto err_no_iores;
833 }
834
835 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
836 if (!hw->regs) {
837 dev_err(&pdev->dev, "cannot ioremap\n");
838 err = -ENXIO;
839 goto err_ioremap;
840 }
841
842 platform_set_drvdata(pdev, hw);
843
844 init_completion(&hw->master_done);
845
846 hw->bitbang.master = hw->master;
847 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
848 hw->bitbang.chipselect = au1550_spi_chipsel;
849 hw->bitbang.master->setup = au1550_spi_setup;
850 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
851
852 if (hw->usedma) {
853 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
854 hw->dma_tx_id, NULL, (void *)hw);
855 if (hw->dma_tx_ch == 0) {
856 dev_err(&pdev->dev,
857 "Cannot allocate tx dma channel\n");
858 err = -ENXIO;
859 goto err_no_txdma;
860 }
861 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
862 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
863 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
864 dev_err(&pdev->dev,
865 "Cannot allocate tx dma descriptors\n");
866 err = -ENXIO;
867 goto err_no_txdma_descr;
868 }
869
870
871 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
872 ddma_memid, NULL, (void *)hw);
873 if (hw->dma_rx_ch == 0) {
874 dev_err(&pdev->dev,
875 "Cannot allocate rx dma channel\n");
876 err = -ENXIO;
877 goto err_no_rxdma;
878 }
879 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
880 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
881 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
882 dev_err(&pdev->dev,
883 "Cannot allocate rx dma descriptors\n");
884 err = -ENXIO;
885 goto err_no_rxdma_descr;
886 }
887
888 err = au1550_spi_dma_rxtmp_alloc(hw,
889 AU1550_SPI_DMA_RXTMP_MINSIZE);
890 if (err < 0) {
891 dev_err(&pdev->dev,
892 "Cannot allocate initial rx dma tmp buffer\n");
893 goto err_dma_rxtmp_alloc;
894 }
895 }
896
897 au1550_spi_bits_handlers_set(hw, 8);
898
899 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
900 if (err) {
901 dev_err(&pdev->dev, "Cannot claim IRQ\n");
902 goto err_no_irq;
903 }
904
905 master->bus_num = pdev->id;
906 master->num_chipselect = hw->pdata->num_chipselect;
907
908 /*
909 * precompute valid range for spi freq - from au1550 datasheet:
910 * psc_tempclk = psc_mainclk / (2 << DIV)
911 * spiclk = psc_tempclk / (2 * (BRG + 1))
912 * BRG valid range is 4..63
913 * DIV valid range is 0..3
914 * round the min and max frequencies to values that would still
915 * produce valid brg and div
916 */
917 {
918 int min_div = (2 << 0) * (2 * (4 + 1));
919 int max_div = (2 << 3) * (2 * (63 + 1));
920 hw->freq_max = hw->pdata->mainclk_hz / min_div;
921 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
922 }
923
924 au1550_spi_setup_psc_as_spi(hw);
925
926 err = spi_bitbang_start(&hw->bitbang);
927 if (err) {
928 dev_err(&pdev->dev, "Failed to register SPI master\n");
929 goto err_register;
930 }
931
932 dev_info(&pdev->dev,
933 "spi master registered: bus_num=%d num_chipselect=%d\n",
934 master->bus_num, master->num_chipselect);
935
936 return 0;
937
938 err_register:
939 free_irq(hw->irq, hw);
940
941 err_no_irq:
942 au1550_spi_dma_rxtmp_free(hw);
943
944 err_dma_rxtmp_alloc:
945 err_no_rxdma_descr:
946 if (hw->usedma)
947 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
948
949 err_no_rxdma:
950 err_no_txdma_descr:
951 if (hw->usedma)
952 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
953
954 err_no_txdma:
955 iounmap((void __iomem *)hw->regs);
956
957 err_ioremap:
958 release_resource(hw->ioarea);
959 kfree(hw->ioarea);
960
961 err_no_iores:
962 err_no_pdata:
963 spi_master_put(hw->master);
964
965 err_nomem:
966 return err;
967 }
968
au1550_spi_remove(struct platform_device * pdev)969 static int __exit au1550_spi_remove(struct platform_device *pdev)
970 {
971 struct au1550_spi *hw = platform_get_drvdata(pdev);
972
973 dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
974 hw->master->bus_num);
975
976 spi_bitbang_stop(&hw->bitbang);
977 free_irq(hw->irq, hw);
978 iounmap((void __iomem *)hw->regs);
979 release_resource(hw->ioarea);
980 kfree(hw->ioarea);
981
982 if (hw->usedma) {
983 au1550_spi_dma_rxtmp_free(hw);
984 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
985 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
986 }
987
988 platform_set_drvdata(pdev, NULL);
989
990 spi_master_put(hw->master);
991 return 0;
992 }
993
994 /* work with hotplug and coldplug */
995 MODULE_ALIAS("platform:au1550-spi");
996
997 static struct platform_driver au1550_spi_drv = {
998 .remove = __exit_p(au1550_spi_remove),
999 .driver = {
1000 .name = "au1550-spi",
1001 .owner = THIS_MODULE,
1002 },
1003 };
1004
au1550_spi_init(void)1005 static int __init au1550_spi_init(void)
1006 {
1007 /*
1008 * create memory device with 8 bits dev_devwidth
1009 * needed for proper byte ordering to spi fifo
1010 */
1011 if (usedma) {
1012 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
1013 if (!ddma_memid)
1014 printk(KERN_ERR "au1550-spi: cannot add memory"
1015 "dbdma device\n");
1016 }
1017 return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
1018 }
1019 module_init(au1550_spi_init);
1020
au1550_spi_exit(void)1021 static void __exit au1550_spi_exit(void)
1022 {
1023 if (usedma && ddma_memid)
1024 au1xxx_ddma_del_device(ddma_memid);
1025 platform_driver_unregister(&au1550_spi_drv);
1026 }
1027 module_exit(au1550_spi_exit);
1028
1029 MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
1030 MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
1031 MODULE_LICENSE("GPL");
1032