1 /*
2 This is part of the rtl8180-sa2400 driver
3 released under the GPL (See file COPYING for details).
4 Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
5
6 This files contains programming code for the rtl8225
7 radio frontend.
8
9 *Many* thanks to Realtek Corp. for their great support!
10
11 */
12
13 #include "r8180_hw.h"
14 #include "r8180_rtl8225.h"
15 #include "r8180_93cx6.h"
16
17 #ifdef ENABLE_DOT11D
18 #include "dot11d.h"
19 #endif
20
21 #ifdef CONFIG_RTL8185B
22
23 extern u8 rtl8225_agc[];
24
25 extern u32 rtl8225_chan[];
26
27 //2005.11.16
28 u8 rtl8225z2_threshold[]={
29 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
30 };
31
32 // 0xd 0x19 0x1b 0x21
33 u8 rtl8225z2_gain_bg[]={
34 0x23, 0x15, 0xa5, // -82-1dbm
35 0x23, 0x15, 0xb5, // -82-2dbm
36 0x23, 0x15, 0xc5, // -82-3dbm
37 0x33, 0x15, 0xc5, // -78dbm
38 0x43, 0x15, 0xc5, // -74dbm
39 0x53, 0x15, 0xc5, // -70dbm
40 0x63, 0x15, 0xc5, // -66dbm
41 };
42
43 u8 rtl8225z2_gain_a[]={
44 0x13,0x27,0x5a,//,0x37,// -82dbm
45 0x23,0x23,0x58,//,0x37,// -82dbm
46 0x33,0x1f,0x56,//,0x37,// -82dbm
47 0x43,0x1b,0x54,//,0x37,// -78dbm
48 0x53,0x17,0x51,//,0x37,// -74dbm
49 0x63,0x24,0x4f,//,0x37,// -70dbm
50 0x73,0x0f,0x4c,//,0x37,// -66dbm
51 };
52 #if 0
53 u32 rtl8225_chan[] = {
54 0, //dummy channel 0
55 0x085c, //1
56 0x08dc, //2
57 0x095c, //3
58 0x09dc, //4
59 0x0a5c, //5
60 0x0adc, //6
61 0x0b5c, //7
62 0x0bdc, //8
63 0x0c5c, //9
64 0x0cdc, //10
65 0x0d5c, //11
66 0x0ddc, //12
67 0x0e5c, //13
68 //0x0f5c, //14
69 0x0f72, // 14
70 };
71 #endif
72
73 //-
74 u16 rtl8225z2_rxgain[]={
75 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
76 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
77 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
78 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
79 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
80 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
81 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
82 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
83 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
84 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
85 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
86 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
87
88 };
89
90 //2005.11.16,
91 u8 ZEBRA2_CCK_OFDM_GAIN_SETTING[]={
92 0x00,0x01,0x02,0x03,0x04,0x05,
93 0x06,0x07,0x08,0x09,0x0a,0x0b,
94 0x0c,0x0d,0x0e,0x0f,0x10,0x11,
95 0x12,0x13,0x14,0x15,0x16,0x17,
96 0x18,0x19,0x1a,0x1b,0x1c,0x1d,
97 0x1e,0x1f,0x20,0x21,0x22,0x23,
98 };
99
100 #if 0
101 //-
102 u8 rtl8225_agc[]={
103 0x9e,0x9e,0x9e,0x9e,0x9e,0x9e,0x9e,0x9e,0x9d,0x9c,0x9b,0x9a,0x99,0x98,0x97,0x96,
104 0x95,0x94,0x93,0x92,0x91,0x90,0x8f,0x8e,0x8d,0x8c,0x8b,0x8a,0x89,0x88,0x87,0x86,
105 0x85,0x84,0x83,0x82,0x81,0x80,0x3f,0x3e,0x3d,0x3c,0x3b,0x3a,0x39,0x38,0x37,0x36,
106 0x35,0x34,0x33,0x32,0x31,0x30,0x2f,0x2e,0x2d,0x2c,0x2b,0x2a,0x29,0x28,0x27,0x26,
107 0x25,0x24,0x23,0x22,0x21,0x20,0x1f,0x1e,0x1d,0x1c,0x1b,0x1a,0x19,0x18,0x17,0x16,
108 0x15,0x14,0x13,0x12,0x11,0x10,0x0f,0x0e,0x0d,0x0c,0x0b,0x0a,0x09,0x08,0x07,0x06,
109 0x05,0x04,0x03,0x02,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
110 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
111 };
112 #endif
113 /*
114 from 0 to 0x23
115 u8 rtl8225_tx_gain_cck_ofdm[]={
116 0x02,0x06,0x0e,0x1e,0x3e,0x7e
117 };
118 */
119
120 //-
121 u8 rtl8225z2_tx_power_ofdm[]={
122 0x42,0x00,0x40,0x00,0x40
123 };
124
125
126 //-
127 u8 rtl8225z2_tx_power_cck_ch14[]={
128 0x36,0x35,0x2e,0x1b,0x00,0x00,0x00,0x00
129 };
130
131
132 //-
133 u8 rtl8225z2_tx_power_cck[]={
134 0x36,0x35,0x2e,0x25,0x1c,0x12,0x09,0x04
135 };
136
137
rtl8225z2_set_gain(struct net_device * dev,short gain)138 void rtl8225z2_set_gain(struct net_device *dev, short gain)
139 {
140 u8* rtl8225_gain;
141 struct r8180_priv *priv = ieee80211_priv(dev);
142
143 u8 mode = priv->ieee80211->mode;
144
145 if(mode == IEEE_B || mode == IEEE_G)
146 rtl8225_gain = rtl8225z2_gain_bg;
147 else
148 rtl8225_gain = rtl8225z2_gain_a;
149
150 //write_phy_ofdm(dev, 0x0d, rtl8225_gain[gain * 3]);
151 //write_phy_ofdm(dev, 0x19, rtl8225_gain[gain * 3 + 1]);
152 //write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 2]);
153 //2005.11.17, by ch-hsu
154 write_phy_ofdm(dev, 0x0b, rtl8225_gain[gain * 3]);
155 write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 1]);
156 write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 3 + 2]);
157 write_phy_ofdm(dev, 0x21, 0x37);
158
159 }
160
161 #if 0
162
163 void rtl8225_set_gain(struct net_device *dev, short gain)
164 {
165 struct r8180_priv *priv = ieee80211_priv(dev);
166
167 rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
168
169 if(priv->card_8185 == 2)
170 write_phy_ofdm(dev, 0x21, 0x27);
171 else
172 write_phy_ofdm(dev, 0x21, 0x37);
173
174 write_phy_ofdm(dev, 0x25, 0x20);
175 write_phy_ofdm(dev, 0x11, 0x6);
176
177 if(priv->card_8185 == 1 && priv->card_8185_Bversion)
178 write_phy_ofdm(dev, 0x27, 0x8);
179 else
180 write_phy_ofdm(dev, 0x27, 0x88);
181
182 write_phy_ofdm(dev, 0x14, 0);
183 write_phy_ofdm(dev, 0x16, 0);
184 write_phy_ofdm(dev, 0x15, 0x40);
185 write_phy_ofdm(dev, 0x17, 0x40);
186
187 write_phy_ofdm(dev, 0x0d, rtl8225_gain[gain * 4]);
188 write_phy_ofdm(dev, 0x23, rtl8225_gain[gain * 4 + 1]);
189 write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 4 + 2]);
190 write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 4 + 3]);
191 //rtl8225_set_gain_usb(dev, gain);
192 }
193 #endif
194
read_rtl8225(struct net_device * dev,u8 adr)195 u32 read_rtl8225(struct net_device *dev, u8 adr)
196 {
197 u32 data2Write = ((u32)(adr & 0x1f)) << 27;
198 u32 dataRead;
199 u32 mask;
200 u16 oval,oval2,oval3,tmp;
201 // ThreeWireReg twreg;
202 // ThreeWireReg tdata;
203 int i;
204 short bit, rw;
205
206 u8 wLength = 6;
207 u8 rLength = 12;
208 u8 low2high = 0;
209
210 oval = read_nic_word(dev, RFPinsOutput);
211 oval2 = read_nic_word(dev, RFPinsEnable);
212 oval3 = read_nic_word(dev, RFPinsSelect);
213
214 write_nic_word(dev, RFPinsEnable, (oval2|0xf));
215 write_nic_word(dev, RFPinsSelect, (oval3|0xf));
216
217 dataRead = 0;
218
219 oval &= ~0xf;
220
221 write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN ); udelay(4);
222
223 write_nic_word(dev, RFPinsOutput, oval ); udelay(5);
224
225 rw = 0;
226
227 mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
228 for(i = 0; i < wLength/2; i++)
229 {
230 bit = ((data2Write&mask) != 0) ? 1 : 0;
231 write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(1);
232
233 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
234 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
235
236 mask = (low2high) ? (mask<<1): (mask>>1);
237
238 if(i == 2)
239 {
240 rw = BB_HOST_BANG_RW;
241 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
242 write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(2);
243 break;
244 }
245
246 bit = ((data2Write&mask) != 0) ? 1: 0;
247
248 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
249 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
250
251 write_nic_word(dev, RFPinsOutput, oval| bit |rw); udelay(1);
252
253 mask = (low2high) ? (mask<<1) : (mask>>1);
254 }
255
256 //twreg.struc.clk = 0;
257 //twreg.struc.data = 0;
258 write_nic_word(dev, RFPinsOutput, rw|oval); udelay(2);
259 mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
260
261 // We must set data pin to HW controled, otherwise RF can't driver it and
262 // value RF register won't be able to read back properly. 2006.06.13, by rcnjko.
263 write_nic_word(dev, RFPinsEnable, (oval2 & (~0x01)));
264
265 for(i = 0; i < rLength; i++)
266 {
267 write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
268
269 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
270 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
271 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
272 tmp = read_nic_word(dev, RFPinsInput);
273
274 dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
275
276 write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
277
278 mask = (low2high) ? (mask<<1) : (mask>>1);
279 }
280
281 write_nic_word(dev, RFPinsOutput, BB_HOST_BANG_EN|BB_HOST_BANG_RW|oval); udelay(2);
282
283 write_nic_word(dev, RFPinsEnable, oval2);
284 write_nic_word(dev, RFPinsSelect, oval3); // Set To SW Switch
285 write_nic_word(dev, RFPinsOutput, 0x3a0);
286
287 return dataRead;
288
289 }
290 #if 0
291 void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
292 {
293 int i;
294 u16 out,select;
295 u8 bit;
296 u32 bangdata = (data << 4) | (adr & 0xf);
297 struct r8180_priv *priv = ieee80211_priv(dev);
298
299 out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
300
301 write_nic_word(dev,RFPinsEnable,
302 (read_nic_word(dev,RFPinsEnable) | 0x7));
303
304 select = read_nic_word(dev, RFPinsSelect);
305
306 write_nic_word(dev, RFPinsSelect, select | 0x7 |
307 ((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
308
309 force_pci_posting(dev);
310 udelay(10);
311
312 write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN );//| 0x1fff);
313
314 force_pci_posting(dev);
315 udelay(2);
316
317 write_nic_word(dev, RFPinsOutput, out);
318
319 force_pci_posting(dev);
320 udelay(10);
321
322
323 for(i=15; i>=0;i--){
324
325 bit = (bangdata & (1<<i)) >> i;
326
327 write_nic_word(dev, RFPinsOutput, bit | out);
328
329 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
330 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
331
332 i--;
333 bit = (bangdata & (1<<i)) >> i;
334
335 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
336 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
337
338 write_nic_word(dev, RFPinsOutput, bit | out);
339
340 }
341
342 write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
343
344 force_pci_posting(dev);
345 udelay(10);
346
347 write_nic_word(dev, RFPinsOutput, out |
348 ((priv->card_type == USB) ? 4 : BB_HOST_BANG_EN));
349
350 write_nic_word(dev, RFPinsSelect, select |
351 ((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
352
353 if(priv->card_type == USB)
354 mdelay(2);
355 else
356 rtl8185_rf_pins_enable(dev);
357 }
358
359 #endif
rtl8225_is_V_z2(struct net_device * dev)360 short rtl8225_is_V_z2(struct net_device *dev)
361 {
362 short vz2 = 1;
363 //int i;
364 /* sw to reg pg 1 */
365 //write_rtl8225(dev, 0, 0x1b7);
366 //write_rtl8225(dev, 0, 0x0b7);
367
368 /* reg 8 pg 1 = 23*/
369 //printk(KERN_WARNING "RF Rigisters:\n");
370 #if 0
371 for(i = 0; i <= 0xf; i++)
372 printk(KERN_WARNING "%08x,", read_rtl8225(dev, i));
373 //printk(KERN_WARNING "reg[9]@pg1 = 0x%x\n", read_rtl8225(dev, 0x0F));
374
375 // printk(KERN_WARNING "RF:\n");
376 #endif
377 if( read_rtl8225(dev, 8) != 0x588)
378 vz2 = 0;
379
380 else /* reg 9 pg 1 = 24 */
381 if( read_rtl8225(dev, 9) != 0x700)
382 vz2 = 0;
383
384 /* sw back to pg 0 */
385 write_rtl8225(dev, 0, 0xb7);
386
387 return vz2;
388
389 }
390
391 #if 0
392 void rtl8225_rf_close(struct net_device *dev)
393 {
394 write_rtl8225(dev, 0x4, 0x1f);
395
396 force_pci_posting(dev);
397 mdelay(1);
398
399 rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_OFF);
400 rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_OFF);
401 }
402 #endif
403 #if 0
404 short rtl8225_rf_set_sens(struct net_device *dev, short sens)
405 {
406 if (sens <0 || sens > 6) return -1;
407
408 if(sens > 4)
409 write_rtl8225(dev, 0x0c, 0x850);
410 else
411 write_rtl8225(dev, 0x0c, 0x50);
412
413 sens= 6-sens;
414 rtl8225_set_gain(dev, sens);
415
416 write_phy_cck(dev, 0x41, rtl8225_threshold[sens]);
417 return 0;
418
419 }
420 #endif
421
422
rtl8225z2_rf_close(struct net_device * dev)423 void rtl8225z2_rf_close(struct net_device *dev)
424 {
425 RF_WriteReg(dev, 0x4, 0x1f);
426
427 force_pci_posting(dev);
428 mdelay(1);
429
430 rtl8180_set_anaparam(dev, RTL8225z2_ANAPARAM_OFF);
431 rtl8185_set_anaparam2(dev, RTL8225z2_ANAPARAM2_OFF);
432 }
433
434 #ifdef ENABLE_DOT11D
435 //
436 // Description:
437 // Map dBm into Tx power index according to
438 // current HW model, for example, RF and PA, and
439 // current wireless mode.
440 //
441 s8
DbmToTxPwrIdx(struct r8180_priv * priv,WIRELESS_MODE WirelessMode,s32 PowerInDbm)442 DbmToTxPwrIdx(
443 struct r8180_priv *priv,
444 WIRELESS_MODE WirelessMode,
445 s32 PowerInDbm
446 )
447 {
448 bool bUseDefault = true;
449 s8 TxPwrIdx = 0;
450
451 #ifdef CONFIG_RTL818X_S
452 //
453 // 071011, SD3 SY:
454 // OFDM Power in dBm = Index * 0.5 + 0
455 // CCK Power in dBm = Index * 0.25 + 13
456 //
457 if(priv->card_8185 >= VERSION_8187S_B)
458 {
459 s32 tmp = 0;
460
461 if(WirelessMode == WIRELESS_MODE_G)
462 {
463 bUseDefault = false;
464 tmp = (2 * PowerInDbm);
465
466 if(tmp < 0)
467 TxPwrIdx = 0;
468 else if(tmp > 40) // 40 means 20 dBm.
469 TxPwrIdx = 40;
470 else
471 TxPwrIdx = (s8)tmp;
472 }
473 else if(WirelessMode == WIRELESS_MODE_B)
474 {
475 bUseDefault = false;
476 tmp = (4 * PowerInDbm) - 52;
477
478 if(tmp < 0)
479 TxPwrIdx = 0;
480 else if(tmp > 28) // 28 means 20 dBm.
481 TxPwrIdx = 28;
482 else
483 TxPwrIdx = (s8)tmp;
484 }
485 }
486 #endif
487
488 //
489 // TRUE if we want to use a default implementation.
490 // We shall set it to FALSE when we have exact translation formular
491 // for target IC. 070622, by rcnjko.
492 //
493 if(bUseDefault)
494 {
495 if(PowerInDbm < 0)
496 TxPwrIdx = 0;
497 else if(PowerInDbm > 35)
498 TxPwrIdx = 35;
499 else
500 TxPwrIdx = (u8)PowerInDbm;
501 }
502
503 return TxPwrIdx;
504 }
505 #endif
506
rtl8225z2_SetTXPowerLevel(struct net_device * dev,short ch)507 void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
508 {
509 struct r8180_priv *priv = ieee80211_priv(dev);
510
511 // int GainIdx;
512 // int GainSetting;
513 //int i;
514 //u8 power;
515 //u8 *cck_power_table;
516 u8 max_cck_power_level;
517 //u8 min_cck_power_level;
518 u8 max_ofdm_power_level;
519 u8 min_ofdm_power_level;
520 // u8 cck_power_level = 0xff & priv->chtxpwr[ch];//-by amy 080312
521 // u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];//-by amy 080312
522 char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);//+by amy 080312
523 char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);//+by amy 080312
524 #if 0
525 //
526 // CCX 2 S31, AP control of client transmit power:
527 // 1. We shall not exceed Cell Power Limit as possible as we can.
528 // 2. Tolerance is +/- 5dB.
529 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
530 //
531 // TODO:
532 // 1. 802.11h power contraint
533 //
534 // 071011, by rcnjko.
535 //
536 if( priv->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
537 priv->bWithCcxCellPwr &&
538 ch == priv->dot11CurrentChannelNumber)
539 {
540 u8 CckCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
541 u8 OfdmCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
542
543 printk("CCX Cell Limit: %d dBm => CCK Tx power index : %d, OFDM Tx power index: %d\n",
544 priv->CcxCellPwr, CckCellPwrIdx, OfdmCellPwrIdx);
545 printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n",
546 channel, CckTxPwrIdx, OfdmTxPwrIdx);
547
548 if(cck_power_level > CckCellPwrIdx)
549 cck_power_level = CckCellPwrIdx;
550 if(ofdm_power_level > OfdmCellPwrIdx)
551 ofdm_power_level = OfdmCellPwrIdx;
552
553 printk("Altered CCK Tx power index : %d, OFDM Tx power index: %d\n",
554 CckTxPwrIdx, OfdmTxPwrIdx);
555 }
556 #endif
557 #ifdef ENABLE_DOT11D
558 if(IS_DOT11D_ENABLE(priv->ieee80211) &&
559 IS_DOT11D_STATE_DONE(priv->ieee80211) )
560 {
561 //PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(priv->ieee80211);
562 u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
563 u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B, MaxTxPwrInDbm);
564 u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G, MaxTxPwrInDbm);
565
566 //printk("Max Tx Power dBm (%d) => CCK Tx power index : %d, OFDM Tx power index: %d\n", MaxTxPwrInDbm, CckMaxPwrIdx, OfdmMaxPwrIdx);
567
568 //printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n",
569 // ch, cck_power_level, ofdm_power_level);
570
571 if(cck_power_level > CckMaxPwrIdx)
572 cck_power_level = CckMaxPwrIdx;
573 if(ofdm_power_level > OfdmMaxPwrIdx)
574 ofdm_power_level = OfdmMaxPwrIdx;
575 }
576
577 //priv->CurrentCckTxPwrIdx = cck_power_level;
578 //priv->CurrentOfdmTxPwrIdx = ofdm_power_level;
579 #endif
580
581 max_cck_power_level = 15;
582 max_ofdm_power_level = 25; // 12 -> 25
583 min_ofdm_power_level = 10;
584
585 #ifdef CONFIG_RTL8185B
586 #ifdef CONFIG_RTL818X_S
587
588 if(cck_power_level > 35)
589 {
590 cck_power_level = 35;
591 }
592 //
593 // Set up CCK TXAGC. suggested by SD3 SY.
594 //
595 write_nic_byte(dev, CCK_TXAGC, (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]) );
596 //printk("CCK TX power is %x\n", (ZEBRA2_CCK_OFDM_GAIN_SETTING[cck_power_level]));
597 force_pci_posting(dev);
598 mdelay(1);
599 #else
600
601 /* CCK power setting */
602 if(cck_power_level > max_cck_power_level)
603 cck_power_level = max_cck_power_level;
604
605 cck_power_level += priv->cck_txpwr_base;
606
607 if(cck_power_level > 35)
608 cck_power_level = 35;
609
610 if(ch == 14)
611 cck_power_table = rtl8225z2_tx_power_cck_ch14;
612 else
613 cck_power_table = rtl8225z2_tx_power_cck;
614
615
616 for(i=0;i<8;i++){
617
618 power = cck_power_table[i];
619 write_phy_cck(dev, 0x44 + i, power);
620 }
621
622 //write_nic_byte(dev, TX_GAIN_CCK, power);
623 //2005.11.17,
624 write_nic_byte(dev, CCK_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]);
625
626 force_pci_posting(dev);
627 mdelay(1);
628 #endif
629 #endif
630 /* OFDM power setting */
631 // Old:
632 // if(ofdm_power_level > max_ofdm_power_level)
633 // ofdm_power_level = 35;
634 // ofdm_power_level += min_ofdm_power_level;
635 // Latest:
636 /* if(ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
637 ofdm_power_level = max_ofdm_power_level;
638 else
639 ofdm_power_level += min_ofdm_power_level;
640
641 ofdm_power_level += priv->ofdm_txpwr_base;
642 */
643 if(ofdm_power_level > 35)
644 ofdm_power_level = 35;
645
646 // rtl8185_set_anaparam2(dev,RTL8225_ANAPARAM2_ON);
647
648 //rtl8185_set_anaparam2(dev, ANAPARM2_ASIC_ON);
649
650 if (priv->up == 0) {
651 //must add these for rtl8185B down, xiong-2006-11-21
652 write_phy_ofdm(dev,2,0x42);
653 write_phy_ofdm(dev,5,0);
654 write_phy_ofdm(dev,6,0x40);
655 write_phy_ofdm(dev,7,0);
656 write_phy_ofdm(dev,8,0x40);
657 }
658
659 //write_nic_byte(dev, TX_GAIN_OFDM, ofdm_power_level);
660 //2005.11.17,
661 #ifdef CONFIG_RTL818X_S
662 write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
663 #else
664 write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]*2);
665 #endif
666 if(ofdm_power_level<=11)
667 {
668 // write_nic_dword(dev,PHY_ADR,0x00005c87);
669 // write_nic_dword(dev,PHY_ADR,0x00005c89);
670 write_phy_ofdm(dev,0x07,0x5c);
671 write_phy_ofdm(dev,0x09,0x5c);
672 }
673 if(ofdm_power_level<=17)
674 {
675 // write_nic_dword(dev,PHY_ADR,0x00005487);
676 // write_nic_dword(dev,PHY_ADR,0x00005489);
677 write_phy_ofdm(dev,0x07,0x54);
678 write_phy_ofdm(dev,0x09,0x54);
679 }
680 else
681 {
682 // write_nic_dword(dev,PHY_ADR,0x00005087);
683 // write_nic_dword(dev,PHY_ADR,0x00005089);
684 write_phy_ofdm(dev,0x07,0x50);
685 write_phy_ofdm(dev,0x09,0x50);
686 }
687 force_pci_posting(dev);
688 mdelay(1);
689
690 }
691 #if 0
692 /* switch between mode B and G */
693 void rtl8225_set_mode(struct net_device *dev, short modeb)
694 {
695 write_phy_ofdm(dev, 0x15, (modeb ? 0x0 : 0x40));
696 write_phy_ofdm(dev, 0x17, (modeb ? 0x0 : 0x40));
697 }
698 #endif
699
rtl8225z2_rf_set_chan(struct net_device * dev,short ch)700 void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
701 {
702 /*
703 short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
704 ieee80211_is_54g(priv->ieee80211->current_network)) ||
705 priv->ieee80211->iw_mode == IW_MODE_MONITOR;
706 */
707 rtl8225z2_SetTXPowerLevel(dev, ch);
708
709 RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
710
711 //YJ,add,080828, if set channel failed, write again
712 if((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
713 {
714 RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
715 }
716
717 mdelay(1);
718
719 force_pci_posting(dev);
720 mdelay(10);
721 //deleted by David : 2006/8/9
722 #if 0
723 write_nic_byte(dev,SIFS,0x22);// SIFS: 0x22
724
725 if(gset)
726 write_nic_byte(dev,DIFS,20); //DIFS: 20
727 else
728 write_nic_byte(dev,DIFS,0x24); //DIFS: 36
729
730 if(priv->ieee80211->state == IEEE80211_LINKED &&
731 ieee80211_is_shortslot(priv->ieee80211->current_network))
732 write_nic_byte(dev,SLOT,0x9); //SLOT: 9
733
734 else
735 write_nic_byte(dev,SLOT,0x14); //SLOT: 20 (0x14)
736
737
738 if(gset){
739 write_nic_byte(dev,EIFS,91 - 20); // EIFS: 91 (0x5B)
740 write_nic_byte(dev,CW_VAL,0x73); //CW VALUE: 0x37
741 //DMESG("using G net params");
742 }else{
743 write_nic_byte(dev,EIFS,91 - 0x24); // EIFS: 91 (0x5B)
744 write_nic_byte(dev,CW_VAL,0xa5); //CW VALUE: 0x37
745 //DMESG("using B net params");
746 }
747 #endif
748
749 }
750 #if 0
751 void rtl8225_host_pci_init(struct net_device *dev)
752 {
753 write_nic_word(dev, RFPinsOutput, 0x480);
754
755 rtl8185_rf_pins_enable(dev);
756
757 //if(priv->card_8185 == 2 && priv->enable_gpio0 ) /* version D */
758 //write_nic_word(dev, RFPinsSelect, 0x88);
759 //else
760 write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO); /* 0x488 | SW_CONTROL_GPIO */
761
762 write_nic_byte(dev, GP_ENABLE, 0);
763
764 force_pci_posting(dev);
765 mdelay(200);
766
767 write_nic_word(dev, GP_ENABLE, 0xff & (~(1<<6))); /* bit 6 is for RF on/off detection */
768
769
770 }
771
772 void rtl8225_host_usb_init(struct net_device *dev)
773 {
774 write_nic_byte(dev,RFPinsSelect+1,0);
775
776 write_nic_byte(dev,GPIO,0);
777
778 write_nic_byte_E(dev,0x53,read_nic_byte_E(dev,0x53) | (1<<7));
779
780 write_nic_byte(dev,RFPinsSelect+1,4);
781
782 write_nic_byte(dev,GPIO,0x20);
783
784 write_nic_byte(dev,GP_ENABLE,0);
785
786
787 /* Config BB & RF */
788 write_nic_word(dev, RFPinsOutput, 0x80);
789
790 write_nic_word(dev, RFPinsSelect, 0x80);
791
792 write_nic_word(dev, RFPinsEnable, 0x80);
793
794
795 mdelay(100);
796
797 mdelay(1000);
798
799 }
800 #endif
rtl8225z2_rf_init(struct net_device * dev)801 void rtl8225z2_rf_init(struct net_device *dev)
802 {
803 struct r8180_priv *priv = ieee80211_priv(dev);
804 int i;
805 short channel = 1;
806 u16 brsr;
807 u32 data,addr;
808
809 priv->chan = channel;
810
811 // rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
812
813
814 if(priv->card_type == USB)
815 rtl8225_host_usb_init(dev);
816 else
817 rtl8225_host_pci_init(dev);
818
819 write_nic_dword(dev, RF_TIMING, 0x000a8008);
820
821 brsr = read_nic_word(dev, BRSR);
822
823 write_nic_word(dev, BRSR, 0xffff);
824
825
826 write_nic_dword(dev, RF_PARA, 0x100044);
827
828 #if 1 //0->1
829 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
830 write_nic_byte(dev, CONFIG3, 0x44);
831 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
832 #endif
833
834
835 rtl8185_rf_pins_enable(dev);
836
837 // mdelay(1000);
838
839 write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
840
841
842 write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
843
844 write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
845
846 write_rtl8225(dev, 0x3, 0x441); mdelay(1);
847
848
849 write_rtl8225(dev, 0x4, 0x8c3);mdelay(1);
850
851
852
853 write_rtl8225(dev, 0x5, 0xc72);mdelay(1);
854 // }
855
856 write_rtl8225(dev, 0x6, 0xe6); mdelay(1);
857
858 write_rtl8225(dev, 0x7, ((priv->card_type == USB)? 0x82a : rtl8225_chan[channel])); mdelay(1);
859
860 write_rtl8225(dev, 0x8, 0x3f); mdelay(1);
861
862 write_rtl8225(dev, 0x9, 0x335); mdelay(1);
863
864 write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
865
866 write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
867
868 write_rtl8225(dev, 0xc, 0x850); mdelay(1);
869
870
871 write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
872
873 write_rtl8225(dev, 0xe, 0x2b); mdelay(1);
874
875 write_rtl8225(dev, 0xf, 0x114);
876
877
878 mdelay(100);
879
880
881 //if(priv->card_type != USB) /* maybe not needed even for 8185 */
882 // write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
883
884 write_rtl8225(dev, 0x0, 0x1b7);
885
886 for(i=0;i<95;i++){
887 write_rtl8225(dev, 0x1, (u8)(i+1));
888
889 #if 0
890 if(priv->phy_ver == 1)
891 /* version A */
892 write_rtl8225(dev, 0x2, rtl8225a_rxgain[i]);
893 else
894 #endif
895 /* version B & C & D*/
896
897 write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
898 }
899 write_rtl8225(dev, 0x3, 0x80);
900 write_rtl8225(dev, 0x5, 0x4);
901
902 write_rtl8225(dev, 0x0, 0xb7);
903
904 write_rtl8225(dev, 0x2, 0xc4d);
905
906 if(priv->card_type == USB){
907 // force_pci_posting(dev);
908 mdelay(200);
909
910 write_rtl8225(dev, 0x2, 0x44d);
911
912 // force_pci_posting(dev);
913 mdelay(100);
914
915 }//End of if(priv->card_type == USB)
916 /* FIXME!! rtl8187 we have to check if calibrarion
917 * is successful and eventually cal. again (repeat
918 * the two write on reg 2)
919 */
920 // Check for calibration status, 2005.11.17,
921 data = read_rtl8225(dev, 6);
922 if (!(data&0x00000080))
923 {
924 write_rtl8225(dev, 0x02, 0x0c4d);
925 force_pci_posting(dev); mdelay(200);
926 write_rtl8225(dev, 0x02, 0x044d);
927 force_pci_posting(dev); mdelay(100);
928 data = read_rtl8225(dev, 6);
929 if (!(data&0x00000080))
930 {
931 DMESGW("RF Calibration Failed!!!!\n");
932 }
933 }
934 //force_pci_posting(dev);
935
936 mdelay(200); //200 for 8187
937
938
939 // //if(priv->card_type != USB){
940 // write_rtl8225(dev, 0x2, 0x44d);
941 // write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
942 // write_rtl8225(dev, 0x2, 0x47d);
943 //
944 // force_pci_posting(dev);
945 // mdelay(100);
946 //
947 // write_rtl8225(dev, 0x2, 0x44d);
948 // //}
949
950 write_rtl8225(dev, 0x0, 0x2bf);
951
952 if(priv->card_type != USB)
953 rtl8185_rf_pins_enable(dev);
954 //set up ZEBRA AGC table, 2005.11.17,
955 for(i=0;i<128;i++){
956 data = rtl8225_agc[i];
957
958 addr = i + 0x80; //enable writing AGC table
959 write_phy_ofdm(dev, 0xb, data);
960
961 mdelay(1);
962 write_phy_ofdm(dev, 0xa, addr);
963
964 mdelay(1);
965 }
966 #if 0
967 for(i=0;i<128;i++){
968 write_phy_ofdm(dev, 0xb, rtl8225_agc[i]);
969
970 mdelay(1);
971 write_phy_ofdm(dev, 0xa, (u8)i+ 0x80);
972
973 mdelay(1);
974 }
975 #endif
976
977 force_pci_posting(dev);
978 mdelay(1);
979
980 write_phy_ofdm(dev, 0x0, 0x1); mdelay(1);
981 write_phy_ofdm(dev, 0x1, 0x2); mdelay(1);
982 write_phy_ofdm(dev, 0x2, ((priv->card_type == USB)? 0x42 : 0x62)); mdelay(1);
983 write_phy_ofdm(dev, 0x3, 0x0); mdelay(1);
984 write_phy_ofdm(dev, 0x4, 0x0); mdelay(1);
985 write_phy_ofdm(dev, 0x5, 0x0); mdelay(1);
986 write_phy_ofdm(dev, 0x6, 0x40); mdelay(1);
987 write_phy_ofdm(dev, 0x7, 0x0); mdelay(1);
988 write_phy_ofdm(dev, 0x8, 0x40); mdelay(1);
989 write_phy_ofdm(dev, 0x9, 0xfe); mdelay(1);
990
991 write_phy_ofdm(dev, 0xa, 0x8); mdelay(1);
992
993 //write_phy_ofdm(dev, 0x18, 0xef);
994 // }
995 //}
996 write_phy_ofdm(dev, 0xb, 0x80); mdelay(1);
997
998 write_phy_ofdm(dev, 0xc, 0x1);mdelay(1);
999
1000
1001 //if(priv->card_type != USB)
1002 write_phy_ofdm(dev, 0xd, 0x43);
1003
1004 write_phy_ofdm(dev, 0xe, 0xd3);mdelay(1);
1005
1006
1007 #if 0
1008 if(priv->card_8185 == 1){
1009 if(priv->card_8185_Bversion)
1010 write_phy_ofdm(dev, 0xf, 0x20);/*ver B*/
1011 else
1012 write_phy_ofdm(dev, 0xf, 0x28);/*ver C*/
1013 }else{
1014 #endif
1015 write_phy_ofdm(dev, 0xf, 0x38);mdelay(1);
1016 /*ver D & 8187*/
1017 // }
1018
1019 // if(priv->card_8185 == 1 && priv->card_8185_Bversion)
1020 // write_phy_ofdm(dev, 0x10, 0x04);/*ver B*/
1021 // else
1022 write_phy_ofdm(dev, 0x10, 0x84);mdelay(1);
1023 /*ver C & D & 8187*/
1024
1025 write_phy_ofdm(dev, 0x11, 0x07);mdelay(1);
1026 /*agc resp time 700*/
1027
1028
1029 // if(priv->card_8185 == 2){
1030 /* Ver D & 8187*/
1031 write_phy_ofdm(dev, 0x12, 0x20);mdelay(1);
1032
1033 write_phy_ofdm(dev, 0x13, 0x20);mdelay(1);
1034
1035 #if 0
1036 }else{
1037 /* Ver B & C*/
1038 write_phy_ofdm(dev, 0x12, 0x0);
1039 write_phy_ofdm(dev, 0x13, 0x0);
1040 }
1041 #endif
1042 write_phy_ofdm(dev, 0x14, 0x0); mdelay(1);
1043 write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
1044 write_phy_ofdm(dev, 0x16, 0x0); mdelay(1);
1045 write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
1046
1047 // if (priv->card_type == USB)
1048 // write_phy_ofdm(dev, 0x18, 0xef);
1049
1050 write_phy_ofdm(dev, 0x18, 0xef);mdelay(1);
1051
1052
1053 write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
1054 write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
1055 write_phy_ofdm(dev, 0x1b, 0x15);mdelay(1);
1056
1057 write_phy_ofdm(dev, 0x1c, 0x4);mdelay(1);
1058
1059 write_phy_ofdm(dev, 0x1d, 0xc5);mdelay(1); //2005.11.17,
1060
1061 write_phy_ofdm(dev, 0x1e, 0x95);mdelay(1);
1062
1063 write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1);
1064
1065 // }
1066
1067 write_phy_ofdm(dev, 0x20, 0x1f);mdelay(1);
1068
1069 write_phy_ofdm(dev, 0x21, 0x17);mdelay(1);
1070
1071 write_phy_ofdm(dev, 0x22, 0x16);mdelay(1);
1072
1073 // if(priv->card_type != USB)
1074 write_phy_ofdm(dev, 0x23, 0x80);mdelay(1); //FIXME maybe not needed // <>
1075
1076 write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
1077 write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
1078 write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
1079
1080 write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
1081
1082
1083 // <> Set init. gain to m74dBm.
1084
1085 rtl8225z2_set_gain(dev,4);
1086
1087 write_phy_cck(dev, 0x0, 0x98); mdelay(1);
1088 write_phy_cck(dev, 0x3, 0x20); mdelay(1);
1089 write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
1090 write_phy_cck(dev, 0x5, 0x12); mdelay(1);
1091 write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
1092
1093 write_phy_cck(dev, 0x7, 0x78);mdelay(1);
1094 /* Ver C & D & 8187*/
1095
1096 write_phy_cck(dev, 0x8, 0x2e);mdelay(1);
1097
1098 write_phy_cck(dev, 0x10, ((priv->card_type == USB) ? 0x9b: 0x93)); mdelay(1);
1099 write_phy_cck(dev, 0x11, 0x88); mdelay(1);
1100 write_phy_cck(dev, 0x12, 0x47); mdelay(1);
1101 #if 0
1102 if(priv->card_8185 == 1 && priv->card_8185_Bversion)
1103 write_phy_cck(dev, 0x13, 0x98); /* Ver B */
1104 else
1105 #endif
1106 write_phy_cck(dev, 0x13, 0xd0); /* Ver C & D & 8187*/
1107
1108 write_phy_cck(dev, 0x19, 0x0);
1109 write_phy_cck(dev, 0x1a, 0xa0);
1110 write_phy_cck(dev, 0x1b, 0x8);
1111 write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
1112
1113 write_phy_cck(dev, 0x41, 0x8d);mdelay(1);
1114
1115
1116 write_phy_cck(dev, 0x42, 0x15); mdelay(1);
1117 write_phy_cck(dev, 0x43, 0x18); mdelay(1);
1118
1119
1120 write_phy_cck(dev, 0x44, 0x36); mdelay(1);
1121 write_phy_cck(dev, 0x45, 0x35); mdelay(1);
1122 write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
1123 write_phy_cck(dev, 0x47, 0x25); mdelay(1);
1124 write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
1125 write_phy_cck(dev, 0x49, 0x12); mdelay(1);
1126 write_phy_cck(dev, 0x4a, 0x9); mdelay(1);
1127 write_phy_cck(dev, 0x4b, 0x4); mdelay(1);
1128 write_phy_cck(dev, 0x4c, 0x5);mdelay(1);
1129
1130
1131 write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
1132
1133
1134
1135 // <>
1136 // // TESTR 0xb 8187
1137 // write_phy_cck(dev, 0x10, 0x93);// & 0xfb);
1138 //
1139 // //if(priv->card_type != USB){
1140 // write_phy_ofdm(dev, 0x2, 0x62);
1141 // write_phy_ofdm(dev, 0x6, 0x0);
1142 // write_phy_ofdm(dev, 0x8, 0x0);
1143 // //}
1144
1145 rtl8225z2_SetTXPowerLevel(dev, channel);
1146 #ifdef CONFIG_RTL818X_S
1147 write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* Rx ant A, 0xdb for B */
1148 #else
1149 write_phy_cck(dev, 0x10, 0x9b); mdelay(1); /* Rx ant A, 0xdb for B */
1150 #endif
1151 write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* Rx ant A, 0x10 for B */
1152
1153 rtl8185_tx_antenna(dev, 0x3); /* TX ant A, 0x0 for B */
1154
1155 /* switch to high-speed 3-wire
1156 * last digit. 2 for both cck and ofdm
1157 */
1158 if(priv->card_type == USB)
1159 write_nic_dword(dev, 0x94, 0x3dc00002);
1160 else{
1161 write_nic_dword(dev, 0x94, 0x15c00002);
1162 rtl8185_rf_pins_enable(dev);
1163 }
1164
1165 // if(priv->card_type != USB)
1166 // rtl8225_set_gain(dev, 4); /* FIXME this '1' is random */ // <>
1167 // rtl8225_set_mode(dev, 1); /* FIXME start in B mode */ // <>
1168 //
1169 // /* make sure is waken up! */
1170 // write_rtl8225(dev,0x4, 0x9ff);
1171 // rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
1172 // rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
1173
1174 rtl8225_rf_set_chan(dev, priv->chan);
1175
1176 //write_nic_word(dev,BRSR,brsr);
1177
1178 //rtl8225z2_rf_set_mode(dev);
1179 }
1180
rtl8225z2_rf_set_mode(struct net_device * dev)1181 void rtl8225z2_rf_set_mode(struct net_device *dev)
1182 {
1183 struct r8180_priv *priv = ieee80211_priv(dev);
1184
1185 if(priv->ieee80211->mode == IEEE_A)
1186 {
1187 write_rtl8225(dev, 0x5, 0x1865);
1188 write_nic_dword(dev, RF_PARA, 0x10084);
1189 write_nic_dword(dev, RF_TIMING, 0xa8008);
1190 write_phy_ofdm(dev, 0x0, 0x0);
1191 write_phy_ofdm(dev, 0xa, 0x6);
1192 write_phy_ofdm(dev, 0xb, 0x99);
1193 write_phy_ofdm(dev, 0xf, 0x20);
1194 write_phy_ofdm(dev, 0x11, 0x7);
1195
1196 rtl8225z2_set_gain(dev,4);
1197
1198 write_phy_ofdm(dev,0x15, 0x40);
1199 write_phy_ofdm(dev,0x17, 0x40);
1200
1201 write_nic_dword(dev, 0x94,0x10000000);
1202 }else{
1203
1204 write_rtl8225(dev, 0x5, 0x1864);
1205 write_nic_dword(dev, RF_PARA, 0x10044);
1206 write_nic_dword(dev, RF_TIMING, 0xa8008);
1207 write_phy_ofdm(dev, 0x0, 0x1);
1208 write_phy_ofdm(dev, 0xa, 0x6);
1209 write_phy_ofdm(dev, 0xb, 0x99);
1210 write_phy_ofdm(dev, 0xf, 0x20);
1211 write_phy_ofdm(dev, 0x11, 0x7);
1212
1213 rtl8225z2_set_gain(dev,4);
1214
1215 write_phy_ofdm(dev,0x15, 0x40);
1216 write_phy_ofdm(dev,0x17, 0x40);
1217
1218 write_nic_dword(dev, 0x94,0x04000002);
1219 }
1220 }
1221
1222 //lzm mod 080826
1223 //#define MAX_DOZE_WAITING_TIMES_85B 64
1224 //#define MAX_POLLING_24F_TIMES_87SE 5
1225 #define MAX_DOZE_WAITING_TIMES_85B 20
1226 #define MAX_POLLING_24F_TIMES_87SE 10
1227 #define LPS_MAX_SLEEP_WAITING_TIMES_87SE 5
1228
1229 bool
SetZebraRFPowerState8185(struct net_device * dev,RT_RF_POWER_STATE eRFPowerState)1230 SetZebraRFPowerState8185(
1231 struct net_device *dev,
1232 RT_RF_POWER_STATE eRFPowerState
1233 )
1234 {
1235 struct r8180_priv *priv = ieee80211_priv(dev);
1236 u8 btCR9346, btConfig3;
1237 bool bActionAllowed= true, bTurnOffBB = true;//lzm mod 080826
1238 //u32 DWordContent;
1239 u8 u1bTmp;
1240 int i;
1241 //u16 u2bTFPC = 0;
1242 bool bResult = true;
1243 u8 QueueID;
1244
1245 if(priv->SetRFPowerStateInProgress == true)
1246 return false;
1247
1248 priv->SetRFPowerStateInProgress = true;
1249
1250 // enable EEM0 and EEM1 in 9346CR
1251 btCR9346 = read_nic_byte(dev, CR9346);
1252 write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
1253 // enable PARM_En in Config3
1254 btConfig3 = read_nic_byte(dev, CONFIG3);
1255 write_nic_byte(dev, CONFIG3, (btConfig3|CONFIG3_PARM_En) );
1256
1257 switch( priv->rf_chip )
1258 {
1259 case RF_ZEBRA2:
1260 switch( eRFPowerState )
1261 {
1262 case eRfOn:
1263 RF_WriteReg(dev,0x4,0x9FF);
1264
1265 write_nic_dword(dev, ANAPARAM, ANAPARM_ON);
1266 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ON);
1267
1268 write_nic_byte(dev, CONFIG4, priv->RFProgType);
1269
1270 //Follow 87B, Isaiah 2007-04-27
1271 u1bTmp = read_nic_byte(dev, 0x24E);
1272 write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5|BIT6))) );// 070124 SD1 Alex: turn on CCK and OFDM.
1273 break;
1274
1275 case eRfSleep:
1276 break;
1277
1278 case eRfOff:
1279 break;
1280
1281 default:
1282 bResult = false;
1283 break;
1284 }
1285 break;
1286
1287 case RF_ZEBRA4:
1288 switch( eRFPowerState )
1289 {
1290 case eRfOn:
1291 //printk("===================================power on@jiffies:%d\n",jiffies);
1292 write_nic_word(dev, 0x37C, 0x00EC);
1293
1294 //turn on AFE
1295 write_nic_byte(dev, 0x54, 0x00);
1296 write_nic_byte(dev, 0x62, 0x00);
1297
1298 //lzm mod 080826
1299 //turn on RF
1300 //RF_WriteReg(dev, 0x0, 0x009f); //mdelay(1);
1301 //RF_WriteReg(dev, 0x4, 0x0972); //mdelay(1);
1302 RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
1303 RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
1304 //turn on RF again, suggested by SD3 stevenl.
1305 RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
1306 RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
1307
1308 //turn on BB
1309 // write_nic_dword(dev, PhyAddr, 0x4090); //ofdm 10=00
1310 // write_nic_dword(dev, PhyAddr, 0x4092); //ofdm 12=00
1311 write_phy_ofdm(dev,0x10,0x40);
1312 write_phy_ofdm(dev,0x12,0x40);
1313 //Avoid power down at init time.
1314 write_nic_byte(dev, CONFIG4, priv->RFProgType);
1315
1316 u1bTmp = read_nic_byte(dev, 0x24E);
1317 write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5|BIT6))) );
1318
1319 break;
1320
1321 case eRfSleep:
1322 // Make sure BusyQueue is empty befor turn off RFE pwoer.
1323 //printk("===================================power sleep@jiffies:%d\n",jiffies);
1324
1325 for(QueueID = 0, i = 0; QueueID < 6; )
1326 {
1327 if(get_curr_tx_free_desc(dev,QueueID) == priv->txringcount)
1328 {
1329 QueueID++;
1330 continue;
1331 }
1332 #if 0 //reserved amy
1333 else if(priv->NdisAdapter.CurrentPowerState != NdisDeviceStateD0)
1334 {
1335 RT_TRACE(COMP_POWER, DBG_LOUD, ("eRfSleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (pMgntInfo->TxPollingTimes+1), QueueID));
1336 break;
1337 }
1338 #endif
1339 else//lzm mod 080826
1340 {
1341 priv->TxPollingTimes ++;
1342 if(priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE)
1343 {
1344 //RT_TRACE(COMP_POWER, DBG_WARNING, ("\n\n\n SetZebraRFPowerState8185B():eRfSleep: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", LPS_MAX_SLEEP_WAITING_TIMES_87SE, QueueID));
1345 bActionAllowed=false;
1346 break;
1347 }
1348 else
1349 {
1350 udelay(10); // Windows may delay 3~16ms actually.
1351 //RT_TRACE(COMP_POWER, DBG_LOUD, ("eRfSleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (pMgntInfo->TxPollingTimes), QueueID));
1352 }
1353 }
1354
1355 //lzm del 080826
1356 //if(i >= MAX_DOZE_WAITING_TIMES_85B)
1357 //{
1358 //printk("\n\n\n SetZebraRFPowerState8185B(): %d times BusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_85B, QueueID);
1359 //break;
1360 //}
1361 }
1362
1363 if(bActionAllowed)//lzm add 080826
1364 {
1365 //turn off BB RXIQ matrix to cut off rx signal
1366 // write_nic_dword(dev, PhyAddr, 0x0090); //ofdm 10=00
1367 // write_nic_dword(dev, PhyAddr, 0x0092); //ofdm 12=00
1368 write_phy_ofdm(dev,0x10,0x00);
1369 write_phy_ofdm(dev,0x12,0x00);
1370 //turn off RF
1371 RF_WriteReg(dev, 0x4, 0x0000); //mdelay(1);
1372 RF_WriteReg(dev, 0x0, 0x0000); //mdelay(1);
1373 //turn off AFE except PLL
1374 write_nic_byte(dev, 0x62, 0xff);
1375 write_nic_byte(dev, 0x54, 0xec);
1376 // mdelay(10);
1377
1378 #if 1
1379 mdelay(1);
1380 {
1381 int i = 0;
1382 while (true)
1383 {
1384 u8 tmp24F = read_nic_byte(dev, 0x24f);
1385 if ((tmp24F == 0x01) || (tmp24F == 0x09))
1386 {
1387 bTurnOffBB = true;
1388 break;
1389 }
1390 else//lzm mod 080826
1391 {
1392 udelay(10);
1393 i++;
1394 priv->TxPollingTimes++;
1395
1396 if(priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE)
1397 {
1398 //RT_TRACE(COMP_POWER, DBG_WARNING, ("\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times Rx Mac0x24F=0x%x !!!\n\n\n", i, u1bTmp24F));
1399 bTurnOffBB=false;
1400 break;
1401 }
1402 else
1403 {
1404 udelay(10);// Windows may delay 3~16ms actually.
1405 //RT_TRACE(COMP_POWER, DBG_LOUD,("(%d)eRfSleep- u1bTmp24F= 0x%X\n", i, u1bTmp24F));
1406
1407 }
1408 }
1409
1410 //lzm del 080826
1411 //if (i > MAX_POLLING_24F_TIMES_87SE)
1412 // break;
1413 }
1414 }
1415 #endif
1416 if (bTurnOffBB)//lzm mod 080826
1417 {
1418 //turn off BB
1419 u1bTmp = read_nic_byte(dev, 0x24E);
1420 write_nic_byte(dev, 0x24E, (u1bTmp|BIT5|BIT6));
1421
1422 //turn off AFE PLL
1423 //write_nic_byte(dev, 0x54, 0xec);
1424 //write_nic_word(dev, 0x37C, 0x00ec);
1425 write_nic_byte(dev, 0x54, 0xFC); //[ECS] FC-> EC->FC, asked by SD3 Stevenl
1426 write_nic_word(dev, 0x37C, 0x00FC);//[ECS] FC-> EC->FC, asked by SD3 Stevenl
1427 }
1428 }
1429 break;
1430
1431 case eRfOff:
1432 // Make sure BusyQueue is empty befor turn off RFE pwoer.
1433 //printk("===================================power off@jiffies:%d\n",jiffies);
1434 for(QueueID = 0, i = 0; QueueID < 6; )
1435 {
1436 if(get_curr_tx_free_desc(dev,QueueID) == priv->txringcount)
1437 {
1438 QueueID++;
1439 continue;
1440 }
1441 #if 0
1442 else if(Adapter->NdisAdapter.CurrentPowerState != NdisDeviceStateD0)
1443 {
1444 RT_TRACE(COMP_POWER, DBG_LOUD, ("%d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID));
1445 break;
1446 }
1447 #endif
1448 else
1449 {
1450 udelay(10);
1451 i++;
1452 }
1453
1454 if(i >= MAX_DOZE_WAITING_TIMES_85B)
1455 {
1456 //printk("\n\n\n SetZebraRFPowerState8185B(): %d times BusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_85B, QueueID);
1457 break;
1458 }
1459 }
1460
1461 //turn off BB RXIQ matrix to cut off rx signal
1462 // write_nic_dword(dev, PhyAddr, 0x0090); //ofdm 10=00
1463 // write_nic_dword(dev, PhyAddr, 0x0092); //ofdm 12=00
1464 write_phy_ofdm(dev,0x10,0x00);
1465 write_phy_ofdm(dev,0x12,0x00);
1466 //turn off RF
1467 RF_WriteReg(dev, 0x4, 0x0000); //mdelay(1);
1468 RF_WriteReg(dev, 0x0, 0x0000); //mdelay(1);
1469 //turn off AFE except PLL
1470 write_nic_byte(dev, 0x62, 0xff);
1471 write_nic_byte(dev, 0x54, 0xec);
1472 // mdelay(10);
1473 #if 1
1474 mdelay(1);
1475 {
1476 int i = 0;
1477 while (true)
1478 {
1479 u8 tmp24F = read_nic_byte(dev, 0x24f);
1480 if ((tmp24F == 0x01) || (tmp24F == 0x09))
1481 {
1482 bTurnOffBB = true;
1483 break;
1484 }
1485 else
1486 {
1487 bTurnOffBB = false;
1488 udelay(10);
1489 i++;
1490 }
1491 if (i > MAX_POLLING_24F_TIMES_87SE)
1492 break;
1493 }
1494 }
1495 #endif
1496 if (bTurnOffBB)//lzm mod 080826
1497 {
1498
1499 //turn off BB
1500 u1bTmp = read_nic_byte(dev, 0x24E);
1501 write_nic_byte(dev, 0x24E, (u1bTmp|BIT5|BIT6));
1502 //turn off AFE PLL (80M)
1503 //write_nic_byte(dev, 0x54, 0xec);
1504 //write_nic_word(dev, 0x37C, 0x00ec);
1505 write_nic_byte(dev, 0x54, 0xFC); //[ECS] FC-> EC->FC, asked by SD3 Stevenl
1506 write_nic_word(dev, 0x37C, 0x00FC); //[ECS] FC-> EC->FC, asked by SD3 Stevenl
1507 }
1508
1509 break;
1510
1511 default:
1512 bResult = false;
1513 printk("SetZebraRFPowerState8185(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1514 break;
1515 }
1516 break;
1517 }
1518
1519 // disable PARM_En in Config3
1520 btConfig3 &= ~(CONFIG3_PARM_En);
1521 write_nic_byte(dev, CONFIG3, btConfig3);
1522 // disable EEM0 and EEM1 in 9346CR
1523 btCR9346 &= ~(0xC0);
1524 write_nic_byte(dev, CR9346, btCR9346);
1525
1526 if(bResult && bActionAllowed)//lzm mod 080826
1527 {
1528 // Update current RF state variable.
1529 priv->eRFPowerState = eRFPowerState;
1530 #if 0
1531 switch(priv->eRFPowerState)
1532 {
1533 case eRfOff:
1534 //
1535 //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
1536 //
1537 if(priv->RfOffReason==RF_CHANGE_BY_IPS )
1538 {
1539 Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK);
1540 }
1541 else
1542 {
1543 // Turn off LED if RF is not ON.
1544 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1545 }
1546 break;
1547
1548 case eRfOn:
1549 // Turn on RF we are still linked, which might happen when
1550 // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
1551 if( pMgntInfo->bMediaConnect == TRUE )
1552 {
1553 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1554 }
1555 break;
1556
1557 default:
1558 // do nothing.
1559 break;
1560 }
1561 #endif
1562
1563 }
1564
1565 priv->SetRFPowerStateInProgress = false;
1566
1567 return (bResult && bActionAllowed) ;
1568 }
rtl8225z4_rf_sleep(struct net_device * dev)1569 void rtl8225z4_rf_sleep(struct net_device *dev)
1570 {
1571 //
1572 // Turn off RF power.
1573 //
1574 //printk("=========>%s()\n", __func__);
1575 MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
1576 //mdelay(2); //FIXME
1577 }
rtl8225z4_rf_wakeup(struct net_device * dev)1578 void rtl8225z4_rf_wakeup(struct net_device *dev)
1579 {
1580 //
1581 // Turn on RF power.
1582 //
1583 //printk("=========>%s()\n", __func__);
1584 MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS);
1585 }
1586 #endif
1587
1588