1 /************************************************************************** 2 * 3 * Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY 18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR 21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 27 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * The views and conclusions contained in the software and documentation 31 * are those of the authors and should not be interpreted as representing 32 * official policies, either expressed or implied, of Alacritech, Inc. 33 * 34 **************************************************************************/ 35 36 /* 37 * FILENAME: slichw.h 38 * 39 * This header file contains definitions that are common to our hardware. 40 */ 41 #ifndef __SLICHW_H__ 42 #define __SLICHW_H__ 43 44 #define PCI_VENDOR_ID_ALACRITECH 0x139A 45 #define SLIC_1GB_DEVICE_ID 0x0005 46 #define SLIC_2GB_DEVICE_ID 0x0007 /*Oasis Device ID */ 47 48 #define SLIC_1GB_CICADA_SUBSYS_ID 0x0008 49 50 #define SLIC_NBR_MACS 4 51 52 #define SLIC_RCVBUF_SIZE 2048 53 #define SLIC_RCVBUF_HEADSIZE 34 54 #define SLIC_RCVBUF_TAILSIZE 0 55 #define SLIC_RCVBUF_DATASIZE (SLIC_RCVBUF_SIZE - (SLIC_RCVBUF_HEADSIZE +\ 56 SLIC_RCVBUF_TAILSIZE)) 57 58 #define VGBSTAT_XPERR 0x40000000 59 #define VGBSTAT_XERRSHFT 25 60 #define VGBSTAT_XCSERR 0x23 61 #define VGBSTAT_XUFLOW 0x22 62 #define VGBSTAT_XHLEN 0x20 63 #define VGBSTAT_NETERR 0x01000000 64 #define VGBSTAT_NERRSHFT 16 65 #define VGBSTAT_NERRMSK 0x1ff 66 #define VGBSTAT_NCSERR 0x103 67 #define VGBSTAT_NUFLOW 0x102 68 #define VGBSTAT_NHLEN 0x100 69 #define VGBSTAT_LNKERR 0x00000080 70 #define VGBSTAT_LERRMSK 0xff 71 #define VGBSTAT_LDEARLY 0x86 72 #define VGBSTAT_LBOFLO 0x85 73 #define VGBSTAT_LCODERR 0x84 74 #define VGBSTAT_LDBLNBL 0x83 75 #define VGBSTAT_LCRCERR 0x82 76 #define VGBSTAT_LOFLO 0x81 77 #define VGBSTAT_LUFLO 0x80 78 #define IRHDDR_FLEN_MSK 0x0000ffff 79 #define IRHDDR_SVALID 0x80000000 80 #define IRHDDR_ERR 0x10000000 81 #define VRHSTAT_802OE 0x80000000 82 #define VRHSTAT_TPOFLO 0x10000000 83 #define VRHSTATB_802UE 0x80000000 84 #define VRHSTATB_RCVE 0x40000000 85 #define VRHSTATB_BUFF 0x20000000 86 #define VRHSTATB_CARRE 0x08000000 87 #define VRHSTATB_LONGE 0x02000000 88 #define VRHSTATB_PREA 0x01000000 89 #define VRHSTATB_CRC 0x00800000 90 #define VRHSTATB_DRBL 0x00400000 91 #define VRHSTATB_CODE 0x00200000 92 #define VRHSTATB_TPCSUM 0x00100000 93 #define VRHSTATB_TPHLEN 0x00080000 94 #define VRHSTATB_IPCSUM 0x00040000 95 #define VRHSTATB_IPLERR 0x00020000 96 #define VRHSTATB_IPHERR 0x00010000 97 #define SLIC_MAX64_BCNT 23 98 #define SLIC_MAX32_BCNT 26 99 #define IHCMD_XMT_REQ 0x01 100 #define IHFLG_IFSHFT 2 101 #define SLIC_RSPBUF_SIZE 32 102 103 #define SLIC_RESET_MAGIC 0xDEAD 104 #define ICR_INT_OFF 0 105 #define ICR_INT_ON 1 106 #define ICR_INT_MASK 2 107 108 #define ISR_ERR 0x80000000 109 #define ISR_RCV 0x40000000 110 #define ISR_CMD 0x20000000 111 #define ISR_IO 0x60000000 112 #define ISR_UPC 0x10000000 113 #define ISR_LEVENT 0x08000000 114 #define ISR_RMISS 0x02000000 115 #define ISR_UPCERR 0x01000000 116 #define ISR_XDROP 0x00800000 117 #define ISR_UPCBSY 0x00020000 118 #define ISR_EVMSK 0xffff0000 119 #define ISR_PINGMASK 0x00700000 120 #define ISR_PINGDSMASK 0x00710000 121 #define ISR_UPCMASK 0x11000000 122 #define SLIC_WCS_START 0x80000000 123 #define SLIC_WCS_COMPARE 0x40000000 124 #define SLIC_RCVWCS_BEGIN 0x40000000 125 #define SLIC_RCVWCS_FINISH 0x80000000 126 #define SLIC_PM_MAXPATTERNS 6 127 #define SLIC_PM_PATTERNSIZE 128 128 #define SLIC_PMCAPS_WAKEONLAN 0x00000001 129 #define MIICR_REG_PCR 0x00000000 130 #define MIICR_REG_4 0x00040000 131 #define MIICR_REG_9 0x00090000 132 #define MIICR_REG_16 0x00100000 133 #define PCR_RESET 0x8000 134 #define PCR_POWERDOWN 0x0800 135 #define PCR_SPEED_100 0x2000 136 #define PCR_SPEED_1000 0x0040 137 #define PCR_AUTONEG 0x1000 138 #define PCR_AUTONEG_RST 0x0200 139 #define PCR_DUPLEX_FULL 0x0100 140 #define PSR_LINKUP 0x0004 141 142 #define PAR_ADV100FD 0x0100 143 #define PAR_ADV100HD 0x0080 144 #define PAR_ADV10FD 0x0040 145 #define PAR_ADV10HD 0x0020 146 #define PAR_ASYMPAUSE 0x0C00 147 #define PAR_802_3 0x0001 148 149 #define PAR_ADV1000XFD 0x0020 150 #define PAR_ADV1000XHD 0x0040 151 #define PAR_ASYMPAUSE_FIBER 0x0180 152 153 #define PGC_ADV1000FD 0x0200 154 #define PGC_ADV1000HD 0x0100 155 #define SEEQ_LINKFAIL 0x4000 156 #define SEEQ_SPEED 0x0080 157 #define SEEQ_DUPLEX 0x0040 158 #define TDK_DUPLEX 0x0800 159 #define TDK_SPEED 0x0400 160 #define MRV_REG16_XOVERON 0x0068 161 #define MRV_REG16_XOVEROFF 0x0008 162 #define MRV_SPEED_1000 0x8000 163 #define MRV_SPEED_100 0x4000 164 #define MRV_SPEED_10 0x0000 165 #define MRV_FULLDUPLEX 0x2000 166 #define MRV_LINKUP 0x0400 167 168 #define GIG_LINKUP 0x0001 169 #define GIG_FULLDUPLEX 0x0002 170 #define GIG_SPEED_MASK 0x000C 171 #define GIG_SPEED_1000 0x0008 172 #define GIG_SPEED_100 0x0004 173 #define GIG_SPEED_10 0x0000 174 175 #define MCR_RESET 0x80000000 176 #define MCR_CRCEN 0x40000000 177 #define MCR_FULLD 0x10000000 178 #define MCR_PAD 0x02000000 179 #define MCR_RETRYLATE 0x01000000 180 #define MCR_BOL_SHIFT 21 181 #define MCR_IPG1_SHIFT 14 182 #define MCR_IPG2_SHIFT 7 183 #define MCR_IPG3_SHIFT 0 184 #define GMCR_RESET 0x80000000 185 #define GMCR_GBIT 0x20000000 186 #define GMCR_FULLD 0x10000000 187 #define GMCR_GAPBB_SHIFT 14 188 #define GMCR_GAPR1_SHIFT 7 189 #define GMCR_GAPR2_SHIFT 0 190 #define GMCR_GAPBB_1000 0x60 191 #define GMCR_GAPR1_1000 0x2C 192 #define GMCR_GAPR2_1000 0x40 193 #define GMCR_GAPBB_100 0x70 194 #define GMCR_GAPR1_100 0x2C 195 #define GMCR_GAPR2_100 0x40 196 #define XCR_RESET 0x80000000 197 #define XCR_XMTEN 0x40000000 198 #define XCR_PAUSEEN 0x20000000 199 #define XCR_LOADRNG 0x10000000 200 #define RCR_RESET 0x80000000 201 #define RCR_RCVEN 0x40000000 202 #define RCR_RCVALL 0x20000000 203 #define RCR_RCVBAD 0x10000000 204 #define RCR_CTLEN 0x08000000 205 #define RCR_ADDRAEN 0x02000000 206 #define GXCR_RESET 0x80000000 207 #define GXCR_XMTEN 0x40000000 208 #define GXCR_PAUSEEN 0x20000000 209 #define GRCR_RESET 0x80000000 210 #define GRCR_RCVEN 0x40000000 211 #define GRCR_RCVALL 0x20000000 212 #define GRCR_RCVBAD 0x10000000 213 #define GRCR_CTLEN 0x08000000 214 #define GRCR_ADDRAEN 0x02000000 215 #define GRCR_HASHSIZE_SHIFT 17 216 #define GRCR_HASHSIZE 14 217 218 #define SLIC_EEPROM_ID 0xA5A5 219 #define SLIC_SRAM_SIZE2GB (64 * 1024) 220 #define SLIC_SRAM_SIZE1GB (32 * 1024) 221 #define SLIC_HOSTID_DEFAULT 0xFFFF /* uninitialized hostid */ 222 #define SLIC_NBR_MACS 4 223 224 #ifndef FALSE 225 #define FALSE 0 226 #else 227 #undef FALSE 228 #define FALSE 0 229 #endif 230 231 #ifndef TRUE 232 #define TRUE 1 233 #else 234 #undef TRUE 235 #define TRUE 1 236 #endif 237 238 struct slic_rcvbuf { 239 unsigned char pad1[6]; 240 ushort pad2; 241 u32 pad3; 242 u32 pad4; 243 u32 buffer; 244 u32 length; 245 u32 status; 246 u32 pad5; 247 ushort pad6; 248 unsigned char data[SLIC_RCVBUF_DATASIZE]; 249 }; 250 251 struct slic_hddr_wds { 252 union { 253 struct { 254 u32 frame_status; 255 u32 frame_status_b; 256 u32 time_stamp; 257 u32 checksum; 258 } hdrs_14port; 259 struct { 260 u32 frame_status; 261 ushort ByteCnt; 262 ushort TpChksum; 263 ushort CtxHash; 264 ushort MacHash; 265 u32 BufLnk; 266 } hdrs_gbit; 267 } u0; 268 }; 269 270 #define frame_status14 u0.hdrs_14port.frame_status 271 #define frame_status_b14 u0.hdrs_14port.frame_status_b 272 #define frame_statusGB u0.hdrs_gbit.frame_status 273 274 struct slic_host64sg { 275 u32 paddrl; 276 u32 paddrh; 277 u32 length; 278 }; 279 280 struct slic_host64_cmd { 281 u32 hosthandle; 282 u32 RSVD; 283 unsigned char command; 284 unsigned char flags; 285 union { 286 ushort rsv1; 287 ushort rsv2; 288 } u0; 289 union { 290 struct { 291 u32 totlen; 292 struct slic_host64sg bufs[SLIC_MAX64_BCNT]; 293 } slic_buffers; 294 } u; 295 }; 296 297 struct slic_rspbuf { 298 u32 hosthandle; 299 u32 pad0; 300 u32 pad1; 301 u32 status; 302 u32 pad2[4]; 303 304 }; 305 306 struct slic_regs { 307 u32 slic_reset; /* Reset Register */ 308 u32 pad0; 309 310 u32 slic_icr; /* Interrupt Control Register */ 311 u32 pad2; 312 #define SLIC_ICR 0x0008 313 314 u32 slic_isp; /* Interrupt status pointer */ 315 u32 pad1; 316 #define SLIC_ISP 0x0010 317 318 u32 slic_isr; /* Interrupt status */ 319 u32 pad3; 320 #define SLIC_ISR 0x0018 321 322 u32 slic_hbar; /* Header buffer address reg */ 323 u32 pad4; 324 /* 31-8 - phy addr of set of contiguous hdr buffers 325 7-0 - number of buffers passed 326 Buffers are 256 bytes long on 256-byte boundaries. */ 327 #define SLIC_HBAR 0x0020 328 #define SLIC_HBAR_CNT_MSK 0x000000FF 329 330 u32 slic_dbar; /* Data buffer handle & address reg */ 331 u32 pad5; 332 333 /* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. */ 334 #define SLIC_DBAR 0x0028 335 #define SLIC_DBAR_SIZE 2048 336 337 u32 slic_cbar; /* Xmt Cmd buf addr regs.*/ 338 /* 1 per XMT interface 339 31-5 - phy addr of host command buffer 340 4-0 - length of cmd in multiples of 32 bytes 341 Buffers are 32 bytes up to 512 bytes long */ 342 #define SLIC_CBAR 0x0030 343 #define SLIC_CBAR_LEN_MSK 0x0000001F 344 #define SLIC_CBAR_ALIGN 0x00000020 345 346 u32 slic_wcs; /* write control store*/ 347 #define SLIC_WCS 0x0034 348 #define SLIC_WCS_START 0x80000000 /*Start the SLIC (Jump to WCS)*/ 349 #define SLIC_WCS_COMPARE 0x40000000 /* Compare with value in WCS*/ 350 351 u32 slic_rbar; /* Response buffer address reg.*/ 352 u32 pad7; 353 /*31-8 - phy addr of set of contiguous response buffers 354 7-0 - number of buffers passed 355 Buffers are 32 bytes long on 32-byte boundaries.*/ 356 #define SLIC_RBAR 0x0038 357 #define SLIC_RBAR_CNT_MSK 0x000000FF 358 #define SLIC_RBAR_SIZE 32 359 360 u32 slic_stats; /* read statistics (UPR) */ 361 u32 pad8; 362 #define SLIC_RSTAT 0x0040 363 364 u32 slic_rlsr; /* read link status */ 365 u32 pad9; 366 #define SLIC_LSTAT 0x0048 367 368 u32 slic_wmcfg; /* Write Mac Config */ 369 u32 pad10; 370 #define SLIC_WMCFG 0x0050 371 372 u32 slic_wphy; /* Write phy register */ 373 u32 pad11; 374 #define SLIC_WPHY 0x0058 375 376 u32 slic_rcbar; /*Rcv Cmd buf addr reg*/ 377 u32 pad12; 378 #define SLIC_RCBAR 0x0060 379 380 u32 slic_rconfig; /* Read SLIC Config*/ 381 u32 pad13; 382 #define SLIC_RCONFIG 0x0068 383 384 u32 slic_intagg; /* Interrupt aggregation time*/ 385 u32 pad14; 386 #define SLIC_INTAGG 0x0070 387 388 u32 slic_wxcfg; /* Write XMIT config reg*/ 389 u32 pad16; 390 #define SLIC_WXCFG 0x0078 391 392 u32 slic_wrcfg; /* Write RCV config reg*/ 393 u32 pad17; 394 #define SLIC_WRCFG 0x0080 395 396 u32 slic_wraddral; /* Write rcv addr a low*/ 397 u32 pad18; 398 #define SLIC_WRADDRAL 0x0088 399 400 u32 slic_wraddrah; /* Write rcv addr a high*/ 401 u32 pad19; 402 #define SLIC_WRADDRAH 0x0090 403 404 u32 slic_wraddrbl; /* Write rcv addr b low*/ 405 u32 pad20; 406 #define SLIC_WRADDRBL 0x0098 407 408 u32 slic_wraddrbh; /* Write rcv addr b high*/ 409 u32 pad21; 410 #define SLIC_WRADDRBH 0x00a0 411 412 u32 slic_mcastlow; /* Low bits of mcast mask*/ 413 u32 pad22; 414 #define SLIC_MCASTLOW 0x00a8 415 416 u32 slic_mcasthigh; /* High bits of mcast mask*/ 417 u32 pad23; 418 #define SLIC_MCASTHIGH 0x00b0 419 420 u32 slic_ping; /* Ping the card*/ 421 u32 pad24; 422 #define SLIC_PING 0x00b8 423 424 u32 slic_dump_cmd; /* Dump command */ 425 u32 pad25; 426 #define SLIC_DUMP_CMD 0x00c0 427 428 u32 slic_dump_data; /* Dump data pointer */ 429 u32 pad26; 430 #define SLIC_DUMP_DATA 0x00c8 431 432 u32 slic_pcistatus; /* Read card's pci_status register */ 433 u32 pad27; 434 #define SLIC_PCISTATUS 0x00d0 435 436 u32 slic_wrhostid; /* Write hostid field */ 437 u32 pad28; 438 #define SLIC_WRHOSTID 0x00d8 439 #define SLIC_RDHOSTID_1GB 0x1554 440 #define SLIC_RDHOSTID_2GB 0x1554 441 442 u32 slic_low_power; /* Put card in a low power state */ 443 u32 pad29; 444 #define SLIC_LOW_POWER 0x00e0 445 446 u32 slic_quiesce; /* force slic into quiescent state 447 before soft reset */ 448 u32 pad30; 449 #define SLIC_QUIESCE 0x00e8 450 451 u32 slic_reset_iface; /* reset interface queues */ 452 u32 pad31; 453 #define SLIC_RESET_IFACE 0x00f0 454 455 u32 slic_addr_upper; /* Bits 63-32 for host i/f addrs */ 456 u32 pad32; 457 #define SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/ 458 459 u32 slic_hbar64; /* 64 bit Header buffer address reg */ 460 u32 pad33; 461 #define SLIC_HBAR64 0x0100 462 463 u32 slic_dbar64; /* 64 bit Data buffer handle & address reg */ 464 u32 pad34; 465 #define SLIC_DBAR64 0x0108 466 467 u32 slic_cbar64; /* 64 bit Xmt Cmd buf addr regs. */ 468 u32 pad35; 469 #define SLIC_CBAR64 0x0110 470 471 u32 slic_rbar64; /* 64 bit Response buffer address reg.*/ 472 u32 pad36; 473 #define SLIC_RBAR64 0x0118 474 475 u32 slic_rcbar64; /* 64 bit Rcv Cmd buf addr reg*/ 476 u32 pad37; 477 #define SLIC_RCBAR64 0x0120 478 479 u32 slic_stats64; /*read statistics (64 bit UPR)*/ 480 u32 pad38; 481 #define SLIC_RSTAT64 0x0128 482 483 u32 slic_rcv_wcs; /*Download Gigabit RCV sequencer ucode*/ 484 u32 pad39; 485 #define SLIC_RCV_WCS 0x0130 486 #define SLIC_RCVWCS_BEGIN 0x40000000 487 #define SLIC_RCVWCS_FINISH 0x80000000 488 489 u32 slic_wrvlanid; /* Write VlanId field */ 490 u32 pad40; 491 #define SLIC_WRVLANID 0x0138 492 493 u32 slic_read_xf_info; /* Read Transformer info */ 494 u32 pad41; 495 #define SLIC_READ_XF_INFO 0x0140 496 497 u32 slic_write_xf_info; /* Write Transformer info */ 498 u32 pad42; 499 #define SLIC_WRITE_XF_INFO 0x0148 500 501 u32 RSVD1; /* TOE Only */ 502 u32 pad43; 503 504 u32 RSVD2; /* TOE Only */ 505 u32 pad44; 506 507 u32 RSVD3; /* TOE Only */ 508 u32 pad45; 509 510 u32 RSVD4; /* TOE Only */ 511 u32 pad46; 512 513 u32 slic_ticks_per_sec; /* Write card ticks per second */ 514 u32 pad47; 515 #define SLIC_TICKS_PER_SEC 0x0170 516 517 }; 518 519 enum UPR_REQUEST { 520 SLIC_UPR_STATS, 521 SLIC_UPR_RLSR, 522 SLIC_UPR_WCFG, 523 SLIC_UPR_RCONFIG, 524 SLIC_UPR_RPHY, 525 SLIC_UPR_ENLB, 526 SLIC_UPR_ENCT, 527 SLIC_UPR_PDWN, 528 SLIC_UPR_PING, 529 SLIC_UPR_DUMP, 530 }; 531 532 struct inicpm_wakepattern { 533 u32 patternlength; 534 unsigned char pattern[SLIC_PM_PATTERNSIZE]; 535 unsigned char mask[SLIC_PM_PATTERNSIZE]; 536 }; 537 538 struct inicpm_state { 539 u32 powercaps; 540 u32 powerstate; 541 u32 wake_linkstatus; 542 u32 wake_magicpacket; 543 u32 wake_framepattern; 544 struct inicpm_wakepattern wakepattern[SLIC_PM_MAXPATTERNS]; 545 }; 546 547 struct slicpm_packet_pattern { 548 u32 priority; 549 u32 reserved; 550 u32 masksize; 551 u32 patternoffset; 552 u32 patternsize; 553 u32 patternflags; 554 }; 555 556 enum slicpm_power_state { 557 slicpm_state_unspecified = 0, 558 slicpm_state_d0, 559 slicpm_state_d1, 560 slicpm_state_d2, 561 slicpm_state_d3, 562 slicpm_state_maximum 563 }; 564 565 struct slicpm_wakeup_capabilities { 566 enum slicpm_power_state min_magic_packet_wakeup; 567 enum slicpm_power_state min_pattern_wakeup; 568 enum slicpm_power_state min_link_change_wakeup; 569 }; 570 571 struct slic_pnp_capabilities { 572 u32 flags; 573 struct slicpm_wakeup_capabilities wakeup_capabilities; 574 }; 575 576 struct xmt_stats { 577 u32 xmit_tcp_bytes; 578 u32 xmit_tcp_segs; 579 u32 xmit_bytes; 580 u32 xmit_collisions; 581 u32 xmit_unicasts; 582 u32 xmit_other_error; 583 u32 xmit_excess_collisions; 584 }; 585 586 struct rcv_stats { 587 u32 rcv_tcp_bytes; 588 u32 rcv_tcp_segs; 589 u32 rcv_bytes; 590 u32 rcv_unicasts; 591 u32 rcv_other_error; 592 u32 rcv_drops; 593 }; 594 595 struct xmt_statsgb { 596 u64 xmit_tcp_bytes; 597 u64 xmit_tcp_segs; 598 u64 xmit_bytes; 599 u64 xmit_collisions; 600 u64 xmit_unicasts; 601 u64 xmit_other_error; 602 u64 xmit_excess_collisions; 603 }; 604 605 struct rcv_statsgb { 606 u64 rcv_tcp_bytes; 607 u64 rcv_tcp_segs; 608 u64 rcv_bytes; 609 u64 rcv_unicasts; 610 u64 rcv_other_error; 611 u64 rcv_drops; 612 }; 613 614 struct slic_stats { 615 union { 616 struct { 617 struct xmt_stats xmt100; 618 struct rcv_stats rcv100; 619 } stats_100; 620 struct { 621 struct xmt_statsgb xmtGB; 622 struct rcv_statsgb rcvGB; 623 } stats_GB; 624 } u; 625 }; 626 627 #define xmit_tcp_segs100 u.stats_100.xmt100.xmit_tcp_segs 628 #define xmit_tcp_bytes100 u.stats_100.xmt100.xmit_tcp_bytes 629 #define xmit_bytes100 u.stats_100.xmt100.xmit_bytes 630 #define xmit_collisions100 u.stats_100.xmt100.xmit_collisions 631 #define xmit_unicasts100 u.stats_100.xmt100.xmit_unicasts 632 #define xmit_other_error100 u.stats_100.xmt100.xmit_other_error 633 #define xmit_excess_collisions100 u.stats_100.xmt100.xmit_excess_collisions 634 #define rcv_tcp_segs100 u.stats_100.rcv100.rcv_tcp_segs 635 #define rcv_tcp_bytes100 u.stats_100.rcv100.rcv_tcp_bytes 636 #define rcv_bytes100 u.stats_100.rcv100.rcv_bytes 637 #define rcv_unicasts100 u.stats_100.rcv100.rcv_unicasts 638 #define rcv_other_error100 u.stats_100.rcv100.rcv_other_error 639 #define rcv_drops100 u.stats_100.rcv100.rcv_drops 640 #define xmit_tcp_segs_gb u.stats_GB.xmtGB.xmit_tcp_segs 641 #define xmit_tcp_bytes_gb u.stats_GB.xmtGB.xmit_tcp_bytes 642 #define xmit_bytes_gb u.stats_GB.xmtGB.xmit_bytes 643 #define xmit_collisions_gb u.stats_GB.xmtGB.xmit_collisions 644 #define xmit_unicasts_gb u.stats_GB.xmtGB.xmit_unicasts 645 #define xmit_other_error_gb u.stats_GB.xmtGB.xmit_other_error 646 #define xmit_excess_collisions_gb u.stats_GB.xmtGB.xmit_excess_collisions 647 648 #define rcv_tcp_segs_gb u.stats_GB.rcvGB.rcv_tcp_segs 649 #define rcv_tcp_bytes_gb u.stats_GB.rcvGB.rcv_tcp_bytes 650 #define rcv_bytes_gb u.stats_GB.rcvGB.rcv_bytes 651 #define rcv_unicasts_gb u.stats_GB.rcvGB.rcv_unicasts 652 #define rcv_other_error_gb u.stats_GB.rcvGB.rcv_other_error 653 #define rcv_drops_gb u.stats_GB.rcvGB.rcv_drops 654 655 struct slic_config_mac { 656 unsigned char macaddrA[6]; 657 }; 658 659 #define ATK_FRU_FORMAT 0x00 660 #define VENDOR1_FRU_FORMAT 0x01 661 #define VENDOR2_FRU_FORMAT 0x02 662 #define VENDOR3_FRU_FORMAT 0x03 663 #define VENDOR4_FRU_FORMAT 0x04 664 #define NO_FRU_FORMAT 0xFF 665 666 struct atk_fru { 667 unsigned char assembly[6]; 668 unsigned char revision[2]; 669 unsigned char serial[14]; 670 unsigned char pad[3]; 671 }; 672 673 struct vendor1_fru { 674 unsigned char commodity; 675 unsigned char assembly[4]; 676 unsigned char revision[2]; 677 unsigned char supplier[2]; 678 unsigned char date[2]; 679 unsigned char sequence[3]; 680 unsigned char pad[13]; 681 }; 682 683 struct vendor2_fru { 684 unsigned char part[8]; 685 unsigned char supplier[5]; 686 unsigned char date[3]; 687 unsigned char sequence[4]; 688 unsigned char pad[7]; 689 }; 690 691 struct vendor3_fru { 692 unsigned char assembly[6]; 693 unsigned char revision[2]; 694 unsigned char serial[14]; 695 unsigned char pad[3]; 696 }; 697 698 struct vendor4_fru { 699 unsigned char number[8]; 700 unsigned char part[8]; 701 unsigned char version[8]; 702 unsigned char pad[3]; 703 }; 704 705 union oemfru { 706 struct vendor1_fru vendor1_fru; 707 struct vendor2_fru vendor2_fru; 708 struct vendor3_fru vendor3_fru; 709 struct vendor4_fru vendor4_fru; 710 }; 711 712 /* 713 SLIC EEPROM structure for Mojave 714 */ 715 struct slic_eeprom { 716 ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/ 717 ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/ 718 ushort FlashSize; /* 02 Flash size */ 719 ushort EepromSize; /* 03 EEPROM Size */ 720 ushort VendorId; /* 04 Vendor ID */ 721 ushort DeviceId; /* 05 Device ID */ 722 unsigned char RevisionId; /* 06 Revision ID */ 723 unsigned char ClassCode[3]; /* 07 Class Code */ 724 unsigned char DbgIntPin; /* 08 Debug Interrupt pin */ 725 unsigned char NetIntPin0; /* Network Interrupt Pin */ 726 unsigned char MinGrant; /* 09 Minimum grant */ 727 unsigned char MaxLat; /* Maximum Latency */ 728 ushort PciStatus; /* 10 PCI Status */ 729 ushort SubSysVId; /* 11 Subsystem Vendor Id */ 730 ushort SubSysId; /* 12 Subsystem ID */ 731 ushort DbgDevId; /* 13 Debug Device Id */ 732 ushort DramRomFn; /* 14 Dram/Rom function */ 733 ushort DSize2Pci; /* 15 DRAM size to PCI (bytes * 64K) */ 734 ushort RSize2Pci; /* 16 ROM extension size to PCI (bytes * 4k) */ 735 unsigned char NetIntPin1;/* 17 Network Interface Pin 1 736 (simba/leone only) */ 737 unsigned char NetIntPin2; /*Network Interface Pin 2 (simba/leone only)*/ 738 union { 739 unsigned char NetIntPin3;/*18 Network Interface Pin 3 740 (simba only)*/ 741 unsigned char FreeTime;/*FreeTime setting (leone/mojave only) */ 742 } u1; 743 unsigned char TBIctl; /* 10-bit interface control (Mojave only) */ 744 ushort DramSize; /* 19 DRAM size (bytes * 64k) */ 745 union { 746 struct { 747 /* Mac Interface Specific portions */ 748 struct slic_config_mac MacInfo[SLIC_NBR_MACS]; 749 } mac; /* MAC access for all boards */ 750 struct { 751 /* use above struct for MAC access */ 752 struct slic_config_mac pad[SLIC_NBR_MACS - 1]; 753 ushort DeviceId2; /* Device ID for 2nd 754 PCI function */ 755 unsigned char IntPin2; /* Interrupt pin for 756 2nd PCI function */ 757 unsigned char ClassCode2[3]; /* Class Code for 2nd 758 PCI function */ 759 } mojave; /* 2nd function access for gigabit board */ 760 } u2; 761 ushort CfgByte6; /* Config Byte 6 */ 762 ushort PMECapab; /* Power Mgment capabilities */ 763 ushort NwClkCtrls; /* NetworkClockControls */ 764 unsigned char FruFormat; /* Alacritech FRU format type */ 765 struct atk_fru AtkFru; /* Alacritech FRU information */ 766 unsigned char OemFruFormat; /* optional OEM FRU format type */ 767 union oemfru OemFru; /* optional OEM FRU information */ 768 unsigned char Pad[4]; /* Pad to 128 bytes - includes 2 cksum bytes 769 *(if OEM FRU info exists) and two unusable 770 * bytes at the end */ 771 }; 772 773 /* SLIC EEPROM structure for Oasis */ 774 struct oslic_eeprom { 775 ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5' */ 776 ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/ 777 ushort FlashConfig0; /* 02 Flash Config for SPI device 0 */ 778 ushort FlashConfig1; /* 03 Flash Config for SPI device 1 */ 779 ushort VendorId; /* 04 Vendor ID */ 780 ushort DeviceId; /* 05 Device ID (function 0) */ 781 unsigned char RevisionId; /* 06 Revision ID */ 782 unsigned char ClassCode[3]; /* 07 Class Code for PCI function 0 */ 783 unsigned char IntPin1; /* 08 Interrupt pin for PCI function 1*/ 784 unsigned char ClassCode2[3]; /* 09 Class Code for PCI function 1 */ 785 unsigned char IntPin2; /* 10 Interrupt pin for PCI function 2*/ 786 unsigned char IntPin0; /* Interrupt pin for PCI function 0*/ 787 unsigned char MinGrant; /* 11 Minimum grant */ 788 unsigned char MaxLat; /* Maximum Latency */ 789 ushort SubSysVId; /* 12 Subsystem Vendor Id */ 790 ushort SubSysId; /* 13 Subsystem ID */ 791 ushort FlashSize; /* 14 Flash size (bytes / 4K) */ 792 ushort DSize2Pci; /* 15 DRAM size to PCI (bytes / 64K) */ 793 ushort RSize2Pci; /* 16 Flash (ROM extension) size to 794 PCI (bytes / 4K) */ 795 ushort DeviceId1; /* 17 Device Id (function 1) */ 796 ushort DeviceId2; /* 18 Device Id (function 2) */ 797 ushort CfgByte6; /* 19 Device Status Config Bytes 6-7 */ 798 ushort PMECapab; /* 20 Power Mgment capabilities */ 799 unsigned char MSICapab; /* 21 MSI capabilities */ 800 unsigned char ClockDivider; /* Clock divider */ 801 ushort PciStatusLow; /* 22 PCI Status bits 15:0 */ 802 ushort PciStatusHigh; /* 23 PCI Status bits 31:16 */ 803 ushort DramConfigLow; /* 24 DRAM Configuration bits 15:0 */ 804 ushort DramConfigHigh; /* 25 DRAM Configuration bits 31:16 */ 805 ushort DramSize; /* 26 DRAM size (bytes / 64K) */ 806 ushort GpioTbiCtl;/* 27 GPIO/TBI controls for functions 1/0 */ 807 ushort EepromSize; /* 28 EEPROM Size */ 808 struct slic_config_mac MacInfo[2]; /* 29 MAC addresses (2 ports) */ 809 unsigned char FruFormat; /* 35 Alacritech FRU format type */ 810 struct atk_fru AtkFru; /* Alacritech FRU information */ 811 unsigned char OemFruFormat; /* optional OEM FRU format type */ 812 union oemfru OemFru; /* optional OEM FRU information */ 813 unsigned char Pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes 814 * (if OEM FRU info exists) and two unusable 815 * bytes at the end 816 */ 817 }; 818 819 #define MAX_EECODE_SIZE sizeof(struct slic_eeprom) 820 #define MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */ 821 822 /* SLIC CONFIG structure 823 824 This structure lives in the CARD structure and is valid for all 825 board types. It is filled in from the appropriate EEPROM structure 826 by SlicGetConfigData(). 827 */ 828 struct slic_config { 829 bool EepromValid; /* Valid EEPROM flag (checksum good?) */ 830 ushort DramSize; /* DRAM size (bytes / 64K) */ 831 struct slic_config_mac MacInfo[SLIC_NBR_MACS]; /* MAC addresses */ 832 unsigned char FruFormat; /* Alacritech FRU format type */ 833 struct atk_fru AtkFru; /* Alacritech FRU information */ 834 unsigned char OemFruFormat; /* optional OEM FRU format type */ 835 union { 836 struct vendor1_fru vendor1_fru; 837 struct vendor2_fru vendor2_fru; 838 struct vendor3_fru vendor3_fru; 839 struct vendor4_fru vendor4_fru; 840 } OemFru; 841 }; 842 843 #pragma pack() 844 845 #endif 846