1 #ifndef _ISP1760_HCD_H_ 2 #define _ISP1760_HCD_H_ 3 4 /* exports for if */ 5 struct usb_hcd *isp1760_register(u64 res_start, u64 res_len, int irq, 6 u64 irqflags, struct device *dev, const char *busname, 7 unsigned int devflags); 8 int init_kmem_once(void); 9 void deinit_kmem_cache(void); 10 11 /* EHCI capability registers */ 12 #define HC_CAPLENGTH 0x00 13 #define HC_HCSPARAMS 0x04 14 #define HC_HCCPARAMS 0x08 15 16 /* EHCI operational registers */ 17 #define HC_USBCMD 0x20 18 #define HC_USBSTS 0x24 19 #define HC_FRINDEX 0x2c 20 #define HC_CONFIGFLAG 0x60 21 #define HC_PORTSC1 0x64 22 #define HC_ISO_PTD_DONEMAP_REG 0x130 23 #define HC_ISO_PTD_SKIPMAP_REG 0x134 24 #define HC_ISO_PTD_LASTPTD_REG 0x138 25 #define HC_INT_PTD_DONEMAP_REG 0x140 26 #define HC_INT_PTD_SKIPMAP_REG 0x144 27 #define HC_INT_PTD_LASTPTD_REG 0x148 28 #define HC_ATL_PTD_DONEMAP_REG 0x150 29 #define HC_ATL_PTD_SKIPMAP_REG 0x154 30 #define HC_ATL_PTD_LASTPTD_REG 0x158 31 32 /* Configuration Register */ 33 #define HC_HW_MODE_CTRL 0x300 34 #define ALL_ATX_RESET (1 << 31) 35 #define HW_ANA_DIGI_OC (1 << 15) 36 #define HW_DATA_BUS_32BIT (1 << 8) 37 #define HW_DACK_POL_HIGH (1 << 6) 38 #define HW_DREQ_POL_HIGH (1 << 5) 39 #define HW_INTR_HIGH_ACT (1 << 2) 40 #define HW_INTR_EDGE_TRIG (1 << 1) 41 #define HW_GLOBAL_INTR_EN (1 << 0) 42 43 #define HC_CHIP_ID_REG 0x304 44 #define HC_SCRATCH_REG 0x308 45 46 #define HC_RESET_REG 0x30c 47 #define SW_RESET_RESET_HC (1 << 1) 48 #define SW_RESET_RESET_ALL (1 << 0) 49 50 #define HC_BUFFER_STATUS_REG 0x334 51 #define ATL_BUFFER 0x1 52 #define INT_BUFFER 0x2 53 #define ISO_BUFFER 0x4 54 #define BUFFER_MAP 0x7 55 56 #define HC_MEMORY_REG 0x33c 57 #define ISP_BANK(x) ((x) << 16) 58 59 #define HC_PORT1_CTRL 0x374 60 #define PORT1_POWER (3 << 3) 61 #define PORT1_INIT1 (1 << 7) 62 #define PORT1_INIT2 (1 << 23) 63 #define HW_OTG_CTRL_SET 0x374 64 #define HW_OTG_CTRL_CLR 0x376 65 66 /* Interrupt Register */ 67 #define HC_INTERRUPT_REG 0x310 68 69 #define HC_INTERRUPT_ENABLE 0x314 70 #define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT | HC_EOT_INT) 71 72 #define HC_ISO_INT (1 << 9) 73 #define HC_ATL_INT (1 << 8) 74 #define HC_INTL_INT (1 << 7) 75 #define HC_EOT_INT (1 << 3) 76 #define HC_SOT_INT (1 << 1) 77 78 #define HC_ISO_IRQ_MASK_OR_REG 0x318 79 #define HC_INT_IRQ_MASK_OR_REG 0x31C 80 #define HC_ATL_IRQ_MASK_OR_REG 0x320 81 #define HC_ISO_IRQ_MASK_AND_REG 0x324 82 #define HC_INT_IRQ_MASK_AND_REG 0x328 83 #define HC_ATL_IRQ_MASK_AND_REG 0x32C 84 85 /* Register sets */ 86 #define HC_BEGIN_OF_ATL 0x0c00 87 #define HC_BEGIN_OF_INT 0x0800 88 #define HC_BEGIN_OF_ISO 0x0400 89 #define HC_BEGIN_OF_PAYLOAD 0x1000 90 91 /* urb state*/ 92 #define DELETE_URB (0x0008) 93 #define NO_TRANSFER_ACTIVE (0xffffffff) 94 95 #define ATL_REGS_OFFSET (0xc00) 96 #define INT_REGS_OFFSET (0x800) 97 98 /* Philips Transfer Descriptor (PTD) */ 99 struct ptd { 100 __le32 dw0; 101 __le32 dw1; 102 __le32 dw2; 103 __le32 dw3; 104 __le32 dw4; 105 __le32 dw5; 106 __le32 dw6; 107 __le32 dw7; 108 }; 109 110 struct inter_packet_info { 111 void *data_buffer; 112 u32 payload; 113 #define PTD_FIRE_NEXT (1 << 0) 114 #define PTD_URB_FINISHED (1 << 1) 115 struct urb *urb; 116 struct isp1760_qh *qh; 117 struct isp1760_qtd *qtd; 118 }; 119 120 121 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, 122 struct isp1760_qtd *qtd); 123 124 #define isp1760_dbg(priv, fmt, args...) \ 125 dev_dbg(priv_to_hcd(priv)->self.controller, fmt, ##args) 126 127 #define isp1760_info(priv, fmt, args...) \ 128 dev_info(priv_to_hcd(priv)->self.controller, fmt, ##args) 129 130 #define isp1760_err(priv, fmt, args...) \ 131 dev_err(priv_to_hcd(priv)->self.controller, fmt, ##args) 132 133 /* 134 * Device flags that can vary from board to board. All of these 135 * indicate the most "atypical" case, so that a devflags of 0 is 136 * a sane default configuration. 137 */ 138 #define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */ 139 #define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */ 140 #define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */ 141 #define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */ 142 #define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */ 143 #define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */ 144 145 /* chip memory management */ 146 struct memory_chunk { 147 unsigned int start; 148 unsigned int size; 149 unsigned int free; 150 }; 151 152 /* 153 * 60kb divided in: 154 * - 32 blocks @ 256 bytes 155 * - 20 blocks @ 1024 bytes 156 * - 4 blocks @ 8192 bytes 157 */ 158 159 #define BLOCK_1_NUM 32 160 #define BLOCK_2_NUM 20 161 #define BLOCK_3_NUM 4 162 163 #define BLOCK_1_SIZE 256 164 #define BLOCK_2_SIZE 1024 165 #define BLOCK_3_SIZE 8192 166 #define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM) 167 #define PAYLOAD_SIZE 0xf000 168 169 /* I saw if some reloads if the pointer was negative */ 170 #define ISP1760_NULL_POINTER (0x400) 171 172 /* ATL */ 173 /* DW0 */ 174 #define PTD_VALID 1 175 #define PTD_LENGTH(x) (((u32) x) << 3) 176 #define PTD_MAXPACKET(x) (((u32) x) << 18) 177 #define PTD_MULTI(x) (((u32) x) << 29) 178 #define PTD_ENDPOINT(x) (((u32) x) << 31) 179 /* DW1 */ 180 #define PTD_DEVICE_ADDR(x) (((u32) x) << 3) 181 #define PTD_PID_TOKEN(x) (((u32) x) << 10) 182 #define PTD_TRANS_BULK ((u32) 2 << 12) 183 #define PTD_TRANS_INT ((u32) 3 << 12) 184 #define PTD_TRANS_SPLIT ((u32) 1 << 14) 185 #define PTD_SE_USB_LOSPEED ((u32) 2 << 16) 186 #define PTD_PORT_NUM(x) (((u32) x) << 18) 187 #define PTD_HUB_NUM(x) (((u32) x) << 25) 188 #define PTD_PING(x) (((u32) x) << 26) 189 /* DW2 */ 190 #define PTD_RL_CNT(x) (((u32) x) << 25) 191 #define PTD_DATA_START_ADDR(x) (((u32) x) << 8) 192 #define BASE_ADDR 0x1000 193 /* DW3 */ 194 #define PTD_CERR(x) (((u32) x) << 23) 195 #define PTD_NAC_CNT(x) (((u32) x) << 19) 196 #define PTD_ACTIVE ((u32) 1 << 31) 197 #define PTD_DATA_TOGGLE(x) (((u32) x) << 25) 198 199 #define DW3_HALT_BIT (1 << 30) 200 #define DW3_ERROR_BIT (1 << 28) 201 #define DW3_QTD_ACTIVE (1 << 31) 202 203 #define INT_UNDERRUN (1 << 2) 204 #define INT_BABBLE (1 << 1) 205 #define INT_EXACT (1 << 0) 206 207 #define DW1_GET_PID(x) (((x) >> 10) & 0x3) 208 #define PTD_XFERRED_LENGTH(x) ((x) & 0x7fff) 209 #define PTD_XFERRED_LENGTH_LO(x) ((x) & 0x7ff) 210 211 #define SETUP_PID (2) 212 #define IN_PID (1) 213 #define OUT_PID (0) 214 #define GET_QTD_TOKEN_TYPE(x) ((x) & 0x3) 215 216 #define DATA_TOGGLE (1 << 31) 217 #define GET_DATA_TOGGLE(x) ((x) >> 31) 218 219 /* Errata 1 */ 220 #define RL_COUNTER (0) 221 #define NAK_COUNTER (0) 222 #define ERR_COUNTER (2) 223 224 #define HC_ATL_PL_SIZE (8192) 225 226 #endif 227