1 /*
2 * MUSB OTG controller driver for Blackfin Processors
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
15 #include <linux/init.h>
16 #include <linux/list.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/io.h>
20
21 #include <asm/cacheflush.h>
22
23 #include "musb_core.h"
24 #include "blackfin.h"
25
26 /*
27 * Load an endpoint's FIFO
28 */
musb_write_fifo(struct musb_hw_ep * hw_ep,u16 len,const u8 * src)29 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
30 {
31 void __iomem *fifo = hw_ep->fifo;
32 void __iomem *epio = hw_ep->regs;
33
34 prefetch((u8 *)src);
35
36 musb_writew(epio, MUSB_TXCOUNT, len);
37
38 DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
39 hw_ep->epnum, fifo, len, src, epio);
40
41 dump_fifo_data(src, len);
42
43 if (unlikely((unsigned long)src & 0x01))
44 outsw_8((unsigned long)fifo, src,
45 len & 0x01 ? (len >> 1) + 1 : len >> 1);
46 else
47 outsw((unsigned long)fifo, src,
48 len & 0x01 ? (len >> 1) + 1 : len >> 1);
49 }
50
51 /*
52 * Unload an endpoint's FIFO
53 */
musb_read_fifo(struct musb_hw_ep * hw_ep,u16 len,u8 * dst)54 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
55 {
56 void __iomem *fifo = hw_ep->fifo;
57 u8 epnum = hw_ep->epnum;
58 u16 dma_reg = 0;
59
60 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
61 'R', hw_ep->epnum, fifo, len, dst);
62
63 #ifdef CONFIG_BF52x
64 invalidate_dcache_range((unsigned int)dst,
65 (unsigned int)(dst + len));
66
67 /* Setup DMA address register */
68 dma_reg = (u16) ((u32) dst & 0xFFFF);
69 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
70 SSYNC();
71
72 dma_reg = (u16) (((u32) dst >> 16) & 0xFFFF);
73 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
74 SSYNC();
75
76 /* Setup DMA count register */
77 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
78 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
79 SSYNC();
80
81 /* Enable the DMA */
82 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
83 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
84 SSYNC();
85
86 /* Wait for compelete */
87 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
88 cpu_relax();
89
90 /* acknowledge dma interrupt */
91 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
92 SSYNC();
93
94 /* Reset DMA */
95 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
96 SSYNC();
97 #else
98 if (unlikely((unsigned long)dst & 0x01))
99 insw_8((unsigned long)fifo, dst,
100 len & 0x01 ? (len >> 1) + 1 : len >> 1);
101 else
102 insw((unsigned long)fifo, dst,
103 len & 0x01 ? (len >> 1) + 1 : len >> 1);
104 #endif
105
106 dump_fifo_data(dst, len);
107 }
108
blackfin_interrupt(int irq,void * __hci)109 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
110 {
111 unsigned long flags;
112 irqreturn_t retval = IRQ_NONE;
113 struct musb *musb = __hci;
114
115 spin_lock_irqsave(&musb->lock, flags);
116
117 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
118 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
119 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
120
121 if (musb->int_usb || musb->int_tx || musb->int_rx) {
122 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
123 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
124 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
125 retval = musb_interrupt(musb);
126 }
127
128 spin_unlock_irqrestore(&musb->lock, flags);
129
130 /* REVISIT we sometimes get spurious IRQs on g_ep0
131 * not clear why... fall in BF54x too.
132 */
133 if (retval != IRQ_HANDLED)
134 DBG(5, "spurious?\n");
135
136 return IRQ_HANDLED;
137 }
138
musb_conn_timer_handler(unsigned long _musb)139 static void musb_conn_timer_handler(unsigned long _musb)
140 {
141 struct musb *musb = (void *)_musb;
142 unsigned long flags;
143 u16 val;
144
145 spin_lock_irqsave(&musb->lock, flags);
146 switch (musb->xceiv.state) {
147 case OTG_STATE_A_IDLE:
148 case OTG_STATE_A_WAIT_BCON:
149 /* Start a new session */
150 val = musb_readw(musb->mregs, MUSB_DEVCTL);
151 val |= MUSB_DEVCTL_SESSION;
152 musb_writew(musb->mregs, MUSB_DEVCTL, val);
153
154 val = musb_readw(musb->mregs, MUSB_DEVCTL);
155 if (!(val & MUSB_DEVCTL_BDEVICE)) {
156 gpio_set_value(musb->config->gpio_vrsel, 1);
157 musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
158 } else {
159 gpio_set_value(musb->config->gpio_vrsel, 0);
160
161 /* Ignore VBUSERROR and SUSPEND IRQ */
162 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
163 val &= ~MUSB_INTR_VBUSERROR;
164 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
165
166 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
167 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
168
169 val = MUSB_POWER_HSENAB;
170 musb_writeb(musb->mregs, MUSB_POWER, val);
171 }
172 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
173 break;
174
175 default:
176 DBG(1, "%s state not handled\n", otg_state_string(musb));
177 break;
178 }
179 spin_unlock_irqrestore(&musb->lock, flags);
180
181 DBG(4, "state is %s\n", otg_state_string(musb));
182 }
183
musb_platform_enable(struct musb * musb)184 void musb_platform_enable(struct musb *musb)
185 {
186 if (is_host_enabled(musb)) {
187 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
188 musb->a_wait_bcon = TIMER_DELAY;
189 }
190 }
191
musb_platform_disable(struct musb * musb)192 void musb_platform_disable(struct musb *musb)
193 {
194 }
195
bfin_vbus_power(struct musb * musb,int is_on,int sleeping)196 static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
197 {
198 }
199
bfin_set_vbus(struct musb * musb,int is_on)200 static void bfin_set_vbus(struct musb *musb, int is_on)
201 {
202 if (is_on)
203 gpio_set_value(musb->config->gpio_vrsel, 1);
204 else
205 gpio_set_value(musb->config->gpio_vrsel, 0);
206
207 DBG(1, "VBUS %s, devctl %02x "
208 /* otg %3x conf %08x prcm %08x */ "\n",
209 otg_state_string(musb),
210 musb_readb(musb->mregs, MUSB_DEVCTL));
211 }
212
bfin_set_power(struct otg_transceiver * x,unsigned mA)213 static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
214 {
215 return 0;
216 }
217
musb_platform_try_idle(struct musb * musb,unsigned long timeout)218 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
219 {
220 if (is_host_enabled(musb))
221 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
222 }
223
musb_platform_get_vbus_status(struct musb * musb)224 int musb_platform_get_vbus_status(struct musb *musb)
225 {
226 return 0;
227 }
228
musb_platform_set_mode(struct musb * musb,u8 musb_mode)229 void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
230 {
231 }
232
musb_platform_init(struct musb * musb)233 int __init musb_platform_init(struct musb *musb)
234 {
235
236 /*
237 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
238 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
239 * be low for DEVICE mode and high for HOST mode. We set it high
240 * here because we are in host mode
241 */
242
243 if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
244 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
245 musb->config->gpio_vrsel);
246 return -ENODEV;
247 }
248 gpio_direction_output(musb->config->gpio_vrsel, 0);
249
250 if (ANOMALY_05000346) {
251 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
252 SSYNC();
253 }
254
255 if (ANOMALY_05000347) {
256 bfin_write_USB_APHY_CNTRL(0x0);
257 SSYNC();
258 }
259
260 /* TODO
261 * Set SIC-IVG register
262 */
263
264 /* Configure PLL oscillator register */
265 bfin_write_USB_PLLOSC_CTRL(0x30a8);
266 SSYNC();
267
268 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
269 SSYNC();
270
271 bfin_write_USB_EP_NI0_RXMAXP(64);
272 SSYNC();
273
274 bfin_write_USB_EP_NI0_TXMAXP(64);
275 SSYNC();
276
277 /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
278 bfin_write_USB_GLOBINTR(0x7);
279 SSYNC();
280
281 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
282 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
283 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
284 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
285 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
286 SSYNC();
287
288 if (is_host_enabled(musb)) {
289 musb->board_set_vbus = bfin_set_vbus;
290 setup_timer(&musb_conn_timer,
291 musb_conn_timer_handler, (unsigned long) musb);
292 }
293 if (is_peripheral_enabled(musb))
294 musb->xceiv.set_power = bfin_set_power;
295
296 musb->isr = blackfin_interrupt;
297
298 return 0;
299 }
300
musb_platform_suspend(struct musb * musb)301 int musb_platform_suspend(struct musb *musb)
302 {
303 return 0;
304 }
305
musb_platform_resume(struct musb * musb)306 int musb_platform_resume(struct musb *musb)
307 {
308 return 0;
309 }
310
311
musb_platform_exit(struct musb * musb)312 int musb_platform_exit(struct musb *musb)
313 {
314
315 bfin_vbus_power(musb, 0 /*off*/, 1);
316 gpio_free(musb->config->gpio_vrsel);
317 musb_platform_suspend(musb);
318
319 return 0;
320 }
321