1 /*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * This file is part of the Inventra Controller Driver for Linux.
5 *
6 * The Inventra Controller Driver for Linux is free software; you
7 * can redistribute it and/or modify it under the terms of the GNU
8 * General Public License version 2 as published by the Free Software
9 * Foundation.
10 *
11 * The Inventra Controller Driver for Linux is distributed in
12 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
13 * without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 * License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with The Inventra Controller Driver for Linux ; if not,
19 * write to the Free Software Foundation, Inc., 59 Temple Place,
20 * Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/list.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
32 #include <linux/io.h>
33 #include <linux/gpio.h>
34
35 #include <mach/hardware.h>
36 #include <mach/memory.h>
37 #include <mach/gpio.h>
38
39 #include <asm/mach-types.h>
40
41 #include "musb_core.h"
42
43 #ifdef CONFIG_MACH_DAVINCI_EVM
44 #define GPIO_nVBUS_DRV 87
45 #endif
46
47 #include "davinci.h"
48 #include "cppi_dma.h"
49
50
51 /* REVISIT (PM) we should be able to keep the PHY in low power mode most
52 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
53 * and, when in host mode, autosuspending idle root ports... PHYPLLON
54 * (overriding SUSPENDM?) then likely needs to stay off.
55 */
56
phy_on(void)57 static inline void phy_on(void)
58 {
59 /* start the on-chip PHY and its PLL */
60 __raw_writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON,
61 (void __force __iomem *) IO_ADDRESS(USBPHY_CTL_PADDR));
62 while ((__raw_readl((void __force __iomem *)
63 IO_ADDRESS(USBPHY_CTL_PADDR))
64 & USBPHY_PHYCLKGD) == 0)
65 cpu_relax();
66 }
67
phy_off(void)68 static inline void phy_off(void)
69 {
70 /* powerdown the on-chip PHY and its oscillator */
71 __raw_writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, (void __force __iomem *)
72 IO_ADDRESS(USBPHY_CTL_PADDR));
73 }
74
75 static int dma_off = 1;
76
musb_platform_enable(struct musb * musb)77 void musb_platform_enable(struct musb *musb)
78 {
79 u32 tmp, old, val;
80
81 /* workaround: setup irqs through both register sets */
82 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
83 << DAVINCI_USB_TXINT_SHIFT;
84 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
85 old = tmp;
86 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
87 << DAVINCI_USB_RXINT_SHIFT;
88 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
89 tmp |= old;
90
91 val = ~MUSB_INTR_SOF;
92 tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
93 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
94
95 if (is_dma_capable() && !dma_off)
96 printk(KERN_WARNING "%s %s: dma not reactivated\n",
97 __FILE__, __func__);
98 else
99 dma_off = 0;
100
101 /* force a DRVVBUS irq so we can start polling for ID change */
102 if (is_otg_enabled(musb))
103 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
104 DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
105 }
106
107 /*
108 * Disable the HDRC and flush interrupts
109 */
musb_platform_disable(struct musb * musb)110 void musb_platform_disable(struct musb *musb)
111 {
112 /* because we don't set CTRLR.UINT, "important" to:
113 * - not read/write INTRUSB/INTRUSBE
114 * - (except during initial setup, as workaround)
115 * - use INTSETR/INTCLRR instead
116 */
117 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
118 DAVINCI_USB_USBINT_MASK
119 | DAVINCI_USB_TXINT_MASK
120 | DAVINCI_USB_RXINT_MASK);
121 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
122 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
123
124 if (is_dma_capable() && !dma_off)
125 WARNING("dma still active\n");
126 }
127
128
129 /* REVISIT it's not clear whether DaVinci can support full OTG. */
130
131 static int vbus_state = -1;
132
133 #ifdef CONFIG_USB_MUSB_HDRC_HCD
134 #define portstate(stmt) stmt
135 #else
136 #define portstate(stmt)
137 #endif
138
139
140 /* VBUS SWITCHING IS BOARD-SPECIFIC */
141
142 #ifdef CONFIG_MACH_DAVINCI_EVM
143
144 /* I2C operations are always synchronous, and require a task context.
145 * With unloaded systems, using the shared workqueue seems to suffice
146 * to satisfy the 100msec A_WAIT_VRISE timeout...
147 */
evm_deferred_drvvbus(struct work_struct * ignored)148 static void evm_deferred_drvvbus(struct work_struct *ignored)
149 {
150 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
151 vbus_state = !vbus_state;
152 }
153 static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
154
155 #endif /* EVM */
156
davinci_source_power(struct musb * musb,int is_on,int immediate)157 static void davinci_source_power(struct musb *musb, int is_on, int immediate)
158 {
159 if (is_on)
160 is_on = 1;
161
162 if (vbus_state == is_on)
163 return;
164 vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
165
166 #ifdef CONFIG_MACH_DAVINCI_EVM
167 if (machine_is_davinci_evm()) {
168 if (immediate)
169 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
170 else
171 schedule_work(&evm_vbus_work);
172 }
173 #endif
174 if (immediate)
175 vbus_state = is_on;
176 }
177
davinci_set_vbus(struct musb * musb,int is_on)178 static void davinci_set_vbus(struct musb *musb, int is_on)
179 {
180 WARN_ON(is_on && is_peripheral_active(musb));
181 davinci_source_power(musb, is_on, 0);
182 }
183
184
185 #define POLL_SECONDS 2
186
187 static struct timer_list otg_workaround;
188
otg_timer(unsigned long _musb)189 static void otg_timer(unsigned long _musb)
190 {
191 struct musb *musb = (void *)_musb;
192 void __iomem *mregs = musb->mregs;
193 u8 devctl;
194 unsigned long flags;
195
196 /* We poll because DaVinci's won't expose several OTG-critical
197 * status change events (from the transceiver) otherwise.
198 */
199 devctl = musb_readb(mregs, MUSB_DEVCTL);
200 DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
201
202 spin_lock_irqsave(&musb->lock, flags);
203 switch (musb->xceiv.state) {
204 case OTG_STATE_A_WAIT_VFALL:
205 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
206 * seems to mis-handle session "start" otherwise (or in our
207 * case "recover"), in routine "VBUS was valid by the time
208 * VBUSERR got reported during enumeration" cases.
209 */
210 if (devctl & MUSB_DEVCTL_VBUS) {
211 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
212 break;
213 }
214 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
215 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
216 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
217 break;
218 case OTG_STATE_B_IDLE:
219 if (!is_peripheral_enabled(musb))
220 break;
221
222 /* There's no ID-changed IRQ, so we have no good way to tell
223 * when to switch to the A-Default state machine (by setting
224 * the DEVCTL.SESSION flag).
225 *
226 * Workaround: whenever we're in B_IDLE, try setting the
227 * session flag every few seconds. If it works, ID was
228 * grounded and we're now in the A-Default state machine.
229 *
230 * NOTE setting the session flag is _supposed_ to trigger
231 * SRP, but clearly it doesn't.
232 */
233 musb_writeb(mregs, MUSB_DEVCTL,
234 devctl | MUSB_DEVCTL_SESSION);
235 devctl = musb_readb(mregs, MUSB_DEVCTL);
236 if (devctl & MUSB_DEVCTL_BDEVICE)
237 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
238 else
239 musb->xceiv.state = OTG_STATE_A_IDLE;
240 break;
241 default:
242 break;
243 }
244 spin_unlock_irqrestore(&musb->lock, flags);
245 }
246
davinci_interrupt(int irq,void * __hci)247 static irqreturn_t davinci_interrupt(int irq, void *__hci)
248 {
249 unsigned long flags;
250 irqreturn_t retval = IRQ_NONE;
251 struct musb *musb = __hci;
252 void __iomem *tibase = musb->ctrl_base;
253 u32 tmp;
254
255 spin_lock_irqsave(&musb->lock, flags);
256
257 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
258 * the Mentor registers (except for setup), use the TI ones and EOI.
259 *
260 * Docs describe irq "vector" registers asociated with the CPPI and
261 * USB EOI registers. These hold a bitmask corresponding to the
262 * current IRQ, not an irq handler address. Would using those bits
263 * resolve some of the races observed in this dispatch code??
264 */
265
266 /* CPPI interrupts share the same IRQ line, but have their own
267 * mask, state, "vector", and EOI registers.
268 */
269 if (is_cppi_enabled()) {
270 u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
271 u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
272
273 if (cppi_tx || cppi_rx) {
274 DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
275 cppi_completion(musb, cppi_rx, cppi_tx);
276 retval = IRQ_HANDLED;
277 }
278 }
279
280 /* ack and handle non-CPPI interrupts */
281 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
282 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
283 DBG(4, "IRQ %08x\n", tmp);
284
285 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
286 >> DAVINCI_USB_RXINT_SHIFT;
287 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
288 >> DAVINCI_USB_TXINT_SHIFT;
289 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
290 >> DAVINCI_USB_USBINT_SHIFT;
291
292 /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
293 * DaVinci's missing ID change IRQ. We need an ID change IRQ to
294 * switch appropriately between halves of the OTG state machine.
295 * Managing DEVCTL.SESSION per Mentor docs requires we know its
296 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
297 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
298 */
299 if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
300 int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
301 void __iomem *mregs = musb->mregs;
302 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
303 int err = musb->int_usb & MUSB_INTR_VBUSERROR;
304
305 err = is_host_enabled(musb)
306 && (musb->int_usb & MUSB_INTR_VBUSERROR);
307 if (err) {
308 /* The Mentor core doesn't debounce VBUS as needed
309 * to cope with device connect current spikes. This
310 * means it's not uncommon for bus-powered devices
311 * to get VBUS errors during enumeration.
312 *
313 * This is a workaround, but newer RTL from Mentor
314 * seems to allow a better one: "re"starting sessions
315 * without waiting (on EVM, a **long** time) for VBUS
316 * to stop registering in devctl.
317 */
318 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
319 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
320 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
321 WARNING("VBUS error workaround (delay coming)\n");
322 } else if (is_host_enabled(musb) && drvvbus) {
323 musb->is_active = 1;
324 MUSB_HST_MODE(musb);
325 musb->xceiv.default_a = 1;
326 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
327 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
328 del_timer(&otg_workaround);
329 } else {
330 musb->is_active = 0;
331 MUSB_DEV_MODE(musb);
332 musb->xceiv.default_a = 0;
333 musb->xceiv.state = OTG_STATE_B_IDLE;
334 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
335 }
336
337 /* NOTE: this must complete poweron within 100 msec */
338 davinci_source_power(musb, drvvbus, 0);
339 DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
340 drvvbus ? "on" : "off",
341 otg_state_string(musb),
342 err ? " ERROR" : "",
343 devctl);
344 retval = IRQ_HANDLED;
345 }
346
347 if (musb->int_tx || musb->int_rx || musb->int_usb)
348 retval |= musb_interrupt(musb);
349
350 /* irq stays asserted until EOI is written */
351 musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
352
353 /* poll for ID change */
354 if (is_otg_enabled(musb)
355 && musb->xceiv.state == OTG_STATE_B_IDLE)
356 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
357
358 spin_unlock_irqrestore(&musb->lock, flags);
359
360 /* REVISIT we sometimes get unhandled IRQs
361 * (e.g. ep0). not clear why...
362 */
363 if (retval != IRQ_HANDLED)
364 DBG(5, "unhandled? %08x\n", tmp);
365 return IRQ_HANDLED;
366 }
367
musb_platform_set_mode(struct musb * musb,u8 mode)368 int musb_platform_set_mode(struct musb *musb, u8 mode)
369 {
370 /* EVM can't do this (right?) */
371 return -EIO;
372 }
373
musb_platform_init(struct musb * musb)374 int __init musb_platform_init(struct musb *musb)
375 {
376 void __iomem *tibase = musb->ctrl_base;
377 u32 revision;
378
379 musb->mregs += DAVINCI_BASE_OFFSET;
380
381 clk_enable(musb->clock);
382
383 /* returns zero if e.g. not clocked */
384 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
385 if (revision == 0)
386 return -ENODEV;
387
388 if (is_host_enabled(musb))
389 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
390
391 musb->board_set_vbus = davinci_set_vbus;
392 davinci_source_power(musb, 0, 1);
393
394 /* reset the controller */
395 musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
396
397 /* start the on-chip PHY and its PLL */
398 phy_on();
399
400 msleep(5);
401
402 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
403 pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
404 revision, __raw_readl((void __force __iomem *)
405 IO_ADDRESS(USBPHY_CTL_PADDR)),
406 musb_readb(tibase, DAVINCI_USB_CTRL_REG));
407
408 musb->isr = davinci_interrupt;
409 return 0;
410 }
411
musb_platform_exit(struct musb * musb)412 int musb_platform_exit(struct musb *musb)
413 {
414 if (is_host_enabled(musb))
415 del_timer_sync(&otg_workaround);
416
417 davinci_source_power(musb, 0 /*off*/, 1);
418
419 /* delay, to avoid problems with module reload */
420 if (is_host_enabled(musb) && musb->xceiv.default_a) {
421 int maxdelay = 30;
422 u8 devctl, warn = 0;
423
424 /* if there's no peripheral connected, this can take a
425 * long time to fall, especially on EVM with huge C133.
426 */
427 do {
428 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
429 if (!(devctl & MUSB_DEVCTL_VBUS))
430 break;
431 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
432 warn = devctl & MUSB_DEVCTL_VBUS;
433 DBG(1, "VBUS %d\n",
434 warn >> MUSB_DEVCTL_VBUS_SHIFT);
435 }
436 msleep(1000);
437 maxdelay--;
438 } while (maxdelay > 0);
439
440 /* in OTG mode, another host might be connected */
441 if (devctl & MUSB_DEVCTL_VBUS)
442 DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
443 }
444
445 phy_off();
446
447 clk_disable(musb->clock);
448
449 return 0;
450 }
451