1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39
40 #include <asm/atomic.h>
41
42 enum {
43 MLX4_FLAG_MSI_X = 1 << 0,
44 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
45 };
46
47 enum {
48 MLX4_MAX_PORTS = 2
49 };
50
51 enum {
52 MLX4_BOARD_ID_LEN = 64
53 };
54
55 enum {
56 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
57 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
58 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
59 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
60 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
61 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
62 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
63 MLX4_DEV_CAP_FLAG_DPDP = 1 << 12,
64 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
65 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
66 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
67 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
68 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
69 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
70 };
71
72 enum {
73 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
74 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
75 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
76 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
77 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
78 };
79
80 enum mlx4_event {
81 MLX4_EVENT_TYPE_COMP = 0x00,
82 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
83 MLX4_EVENT_TYPE_COMM_EST = 0x02,
84 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
85 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
86 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
87 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
88 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
89 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
90 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
91 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
92 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
93 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
94 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
95 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
96 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
97 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
98 MLX4_EVENT_TYPE_CMD = 0x0a
99 };
100
101 enum {
102 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
103 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
104 };
105
106 enum {
107 MLX4_PERM_LOCAL_READ = 1 << 10,
108 MLX4_PERM_LOCAL_WRITE = 1 << 11,
109 MLX4_PERM_REMOTE_READ = 1 << 12,
110 MLX4_PERM_REMOTE_WRITE = 1 << 13,
111 MLX4_PERM_ATOMIC = 1 << 14
112 };
113
114 enum {
115 MLX4_OPCODE_NOP = 0x00,
116 MLX4_OPCODE_SEND_INVAL = 0x01,
117 MLX4_OPCODE_RDMA_WRITE = 0x08,
118 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
119 MLX4_OPCODE_SEND = 0x0a,
120 MLX4_OPCODE_SEND_IMM = 0x0b,
121 MLX4_OPCODE_LSO = 0x0e,
122 MLX4_OPCODE_RDMA_READ = 0x10,
123 MLX4_OPCODE_ATOMIC_CS = 0x11,
124 MLX4_OPCODE_ATOMIC_FA = 0x12,
125 MLX4_OPCODE_ATOMIC_MASK_CS = 0x14,
126 MLX4_OPCODE_ATOMIC_MASK_FA = 0x15,
127 MLX4_OPCODE_BIND_MW = 0x18,
128 MLX4_OPCODE_FMR = 0x19,
129 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
130 MLX4_OPCODE_CONFIG_CMD = 0x1f,
131
132 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
133 MLX4_RECV_OPCODE_SEND = 0x01,
134 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
135 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
136
137 MLX4_CQE_OPCODE_ERROR = 0x1e,
138 MLX4_CQE_OPCODE_RESIZE = 0x16,
139 };
140
141 enum {
142 MLX4_STAT_RATE_OFFSET = 5
143 };
144
145 enum {
146 MLX4_MTT_FLAG_PRESENT = 1
147 };
148
149 enum mlx4_qp_region {
150 MLX4_QP_REGION_FW = 0,
151 MLX4_QP_REGION_ETH_ADDR,
152 MLX4_QP_REGION_FC_ADDR,
153 MLX4_QP_REGION_FC_EXCH,
154 MLX4_NUM_QP_REGION
155 };
156
157 enum mlx4_port_type {
158 MLX4_PORT_TYPE_IB = 1 << 0,
159 MLX4_PORT_TYPE_ETH = 1 << 1,
160 };
161
162 enum mlx4_special_vlan_idx {
163 MLX4_NO_VLAN_IDX = 0,
164 MLX4_VLAN_MISS_IDX,
165 MLX4_VLAN_REGULAR
166 };
167
168 enum {
169 MLX4_NUM_FEXCH = 64 * 1024,
170 };
171
mlx4_fw_ver(u64 major,u64 minor,u64 subminor)172 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
173 {
174 return (major << 32) | (minor << 16) | subminor;
175 }
176
177 struct mlx4_caps {
178 u64 fw_ver;
179 int num_ports;
180 int vl_cap[MLX4_MAX_PORTS + 1];
181 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
182 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
183 u64 def_mac[MLX4_MAX_PORTS + 1];
184 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
185 int gid_table_len[MLX4_MAX_PORTS + 1];
186 int pkey_table_len[MLX4_MAX_PORTS + 1];
187 int local_ca_ack_delay;
188 int num_uars;
189 int bf_reg_size;
190 int bf_regs_per_page;
191 int max_sq_sg;
192 int max_rq_sg;
193 int num_qps;
194 int max_wqes;
195 int max_sq_desc_sz;
196 int max_rq_desc_sz;
197 int max_qp_init_rdma;
198 int max_qp_dest_rdma;
199 int sqp_start;
200 int num_srqs;
201 int max_srq_wqes;
202 int max_srq_sge;
203 int reserved_srqs;
204 int num_cqs;
205 int max_cqes;
206 int reserved_cqs;
207 int num_eqs;
208 int reserved_eqs;
209 int num_comp_vectors;
210 int num_mpts;
211 int num_mtt_segs;
212 int fmr_reserved_mtts;
213 int reserved_mtts;
214 int reserved_mrws;
215 int reserved_uars;
216 int num_mgms;
217 int num_amgms;
218 int reserved_mcgs;
219 int num_qp_per_mgm;
220 int num_pds;
221 int reserved_pds;
222 int mtt_entry_sz;
223 u32 max_msg_sz;
224 u32 page_size_cap;
225 u32 flags;
226 u32 bmme_flags;
227 u32 reserved_lkey;
228 u16 stat_rate_support;
229 u8 port_width_cap[MLX4_MAX_PORTS + 1];
230 int max_gso_sz;
231 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
232 int reserved_qps;
233 int reserved_qps_base[MLX4_NUM_QP_REGION];
234 int log_num_macs;
235 int log_num_vlans;
236 int log_num_prios;
237 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
238 u8 supported_type[MLX4_MAX_PORTS + 1];
239 u32 port_mask;
240 };
241
242 struct mlx4_buf_list {
243 void *buf;
244 dma_addr_t map;
245 };
246
247 struct mlx4_buf {
248 struct mlx4_buf_list direct;
249 struct mlx4_buf_list *page_list;
250 int nbufs;
251 int npages;
252 int page_shift;
253 };
254
255 struct mlx4_mtt {
256 u32 first_seg;
257 int order;
258 int page_shift;
259 };
260
261 enum {
262 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
263 };
264
265 struct mlx4_db_pgdir {
266 struct list_head list;
267 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
268 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
269 unsigned long *bits[2];
270 __be32 *db_page;
271 dma_addr_t db_dma;
272 };
273
274 struct mlx4_ib_user_db_page;
275
276 struct mlx4_db {
277 __be32 *db;
278 union {
279 struct mlx4_db_pgdir *pgdir;
280 struct mlx4_ib_user_db_page *user_page;
281 } u;
282 dma_addr_t dma;
283 int index;
284 int order;
285 };
286
287 struct mlx4_hwq_resources {
288 struct mlx4_db db;
289 struct mlx4_mtt mtt;
290 struct mlx4_buf buf;
291 };
292
293 struct mlx4_mr {
294 struct mlx4_mtt mtt;
295 u64 iova;
296 u64 size;
297 u32 key;
298 u32 pd;
299 u32 access;
300 int enabled;
301 };
302
303 struct mlx4_fmr {
304 struct mlx4_mr mr;
305 struct mlx4_mpt_entry *mpt;
306 __be64 *mtts;
307 dma_addr_t dma_handle;
308 int max_pages;
309 int max_maps;
310 int maps;
311 u8 page_shift;
312 };
313
314 struct mlx4_uar {
315 unsigned long pfn;
316 int index;
317 };
318
319 struct mlx4_cq {
320 void (*comp) (struct mlx4_cq *);
321 void (*event) (struct mlx4_cq *, enum mlx4_event);
322
323 struct mlx4_uar *uar;
324
325 u32 cons_index;
326
327 __be32 *set_ci_db;
328 __be32 *arm_db;
329 int arm_sn;
330
331 int cqn;
332 unsigned vector;
333
334 atomic_t refcount;
335 struct completion free;
336 };
337
338 struct mlx4_qp {
339 void (*event) (struct mlx4_qp *, enum mlx4_event);
340
341 int qpn;
342
343 atomic_t refcount;
344 struct completion free;
345 };
346
347 struct mlx4_srq {
348 void (*event) (struct mlx4_srq *, enum mlx4_event);
349
350 int srqn;
351 int max;
352 int max_gs;
353 int wqe_shift;
354
355 atomic_t refcount;
356 struct completion free;
357 };
358
359 struct mlx4_av {
360 __be32 port_pd;
361 u8 reserved1;
362 u8 g_slid;
363 __be16 dlid;
364 u8 reserved2;
365 u8 gid_index;
366 u8 stat_rate;
367 u8 hop_limit;
368 __be32 sl_tclass_flowlabel;
369 u8 dgid[16];
370 };
371
372 struct mlx4_dev {
373 struct pci_dev *pdev;
374 unsigned long flags;
375 struct mlx4_caps caps;
376 struct radix_tree_root qp_table_tree;
377 u32 rev_id;
378 char board_id[MLX4_BOARD_ID_LEN];
379 };
380
381 struct mlx4_init_port_param {
382 int set_guid0;
383 int set_node_guid;
384 int set_si_guid;
385 u16 mtu;
386 int port_width_cap;
387 u16 vl_cap;
388 u16 max_gid;
389 u16 max_pkey;
390 u64 guid0;
391 u64 node_guid;
392 u64 si_guid;
393 };
394
395 #define mlx4_foreach_port(port, dev, type) \
396 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
397 if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
398 ~(dev)->caps.port_mask) & 1 << ((port) - 1))
399
400 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
401 struct mlx4_buf *buf);
402 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
mlx4_buf_offset(struct mlx4_buf * buf,int offset)403 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
404 {
405 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
406 return buf->direct.buf + offset;
407 else
408 return buf->page_list[offset >> PAGE_SHIFT].buf +
409 (offset & (PAGE_SIZE - 1));
410 }
411
412 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
413 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
414
415 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
416 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
417
418 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
419 struct mlx4_mtt *mtt);
420 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
421 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
422
423 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
424 int npages, int page_shift, struct mlx4_mr *mr);
425 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
426 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
427 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
428 int start_index, int npages, u64 *page_list);
429 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
430 struct mlx4_buf *buf);
431
432 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
433 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
434
435 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
436 int size, int max_direct);
437 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
438 int size);
439
440 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
441 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
442 unsigned vector, int collapsed);
443 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
444
445 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
446 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
447
448 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
449 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
450
451 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
452 u64 db_rec, struct mlx4_srq *srq);
453 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
454 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
455 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
456
457 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
458 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
459
460 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
461 int block_mcast_loopback);
462 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
463
464 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index);
465 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);
466
467 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
468 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
469
470 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
471 int npages, u64 iova, u32 *lkey, u32 *rkey);
472 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
473 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
474 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
475 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
476 u32 *lkey, u32 *rkey);
477 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
478 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
479
480 #endif /* MLX4_DEVICE_H */
481