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Searched refs:__raw_writel (Results 1 – 25 of 460) sorted by relevance

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/arch/arm/mach-iop13xx/
Dpci.c250 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR, in iop13xx_atux_pci_status()
286 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atux_read_config()
315 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR); in iop13xx_atux_write_config()
317 __raw_writel(addr, IOP13XX_ATUX_OCCAR); in iop13xx_atux_write_config()
318 __raw_writel(value, IOP13XX_ATUX_OCCDR); in iop13xx_atux_write_config()
382 __raw_writel(status, IOP13XX_ATUE_PIE_STS); in iop13xx_atue_pci_status()
407 __raw_writel(addr, IOP13XX_ATUE_OCCAR); in iop13xx_atue_read()
429 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atue_read_config()
462 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR); in iop13xx_atue_write_config()
464 __raw_writel(addr, IOP13XX_ATUE_OCCAR); in iop13xx_atue_write_config()
[all …]
/arch/mips/alchemy/common/
Dvss.c26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
29 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
33 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
35 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
37 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
39 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
42 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
45 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
48 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
57 __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ in __disable_block()
[all …]
Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
323 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic1_mask()
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic0_ack()
338 __raw_writel(1 << bit, base + IC_RISINGCLR); in au1x_ic0_ack()
[all …]
Dusb.c109 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
115 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
125 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
131 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
138 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
142 __raw_writel(0, base + USB_DWC_CTRL7); in __au1300_ohci_control()
147 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
153 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
167 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ehci_control()
172 __raw_writel(r, base + USB_DWC_CTRL1); in __au1300_ehci_control()
[all …]
/arch/mips/kernel/
Dcevt-txx9.c57 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
58 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
59 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9_clocksource_init()
60 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9_clocksource_init()
61 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); in txx9_clocksource_init()
62 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
74 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
76 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
89 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, in txx9tmr_set_mode()
92 __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> in txx9tmr_set_mode()
[all …]
/arch/mips/sgi-ip22/
Dip22-nvram.c35 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
36 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
39 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
44 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
46 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
63 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/arch/arm/mach-lpc32xx/
Dtimer.c37 __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET, in lpc32xx_clkevt_next_event()
39 __raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE)); in lpc32xx_clkevt_next_event()
40 __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN, in lpc32xx_clkevt_next_event()
61 __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); in lpc32xx_clkevt_mode()
83 __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0), in lpc32xx_timer_interrupt()
107 __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN | in lpc32xx_timer_init()
130 __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); in lpc32xx_timer_init()
131 __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0), in lpc32xx_timer_init()
133 __raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE)); in lpc32xx_timer_init()
134 __raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) | in lpc32xx_timer_init()
[all …]
Dserial.c80 __raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL); in lpc32xx_serial_init()
92 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); in lpc32xx_serial_init()
99 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
100 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
105 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
109 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); in lpc32xx_serial_init()
113 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
114 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
118 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
124 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
[all …]
Dirq.c217 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); in lpc32xx_mask_irq()
227 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); in lpc32xx_unmask_irq()
236 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); in lpc32xx_ack_irq()
240 __raw_writel(lpc32xx_events[d->hwirq].mask, in lpc32xx_ack_irq()
257 __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl)); in __lpc32xx_set_irq_type()
265 __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl)); in __lpc32xx_set_irq_type()
276 __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg); in __lpc32xx_set_irq_type()
332 __raw_writel(lpc32xx_events[d->hwirq].mask, in lpc32xx_irq_wake()
337 __raw_writel(eventreg, in lpc32xx_irq_wake()
344 __raw_writel(lpc32xx_events[d->hwirq].mask, in lpc32xx_irq_wake()
[all …]
/arch/arm/mach-mmp/
Dtime.c56 __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); in timer_read()
76 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_interrupt()
81 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_interrupt()
98 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_set_next_event()
103 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_set_next_event()
104 __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); in timer_set_next_event()
109 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); in timer_set_next_event()
114 __raw_writel(0x03, mmp_timer_base + TMR_CER); in timer_set_next_event()
132 __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); in timer_set_mode()
166 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ in timer_config()
[all …]
Dpm-mmp2.c64 __raw_writel(data, MPMU_WUCRM_PJ); in mmp2_set_wake()
69 __raw_writel(data, MPMU_WUCRM_PJ); in mmp2_set_wake()
80 __raw_writel(0x0, CIU_REG(0x64)); in pm_scu_clk_disable()
81 __raw_writel(0x0, CIU_REG(0x68)); in pm_scu_clk_disable()
86 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_disable()
96 __raw_writel(0x03003003, CIU_REG(0x64)); in pm_scu_clk_enable()
97 __raw_writel(0x00303030, CIU_REG(0x68)); in pm_scu_clk_enable()
102 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_enable()
113 __raw_writel(0x0000a010, MPMU_CGR_PJ); in pm_mpmu_clk_disable()
120 __raw_writel(0xdffefffe, MPMU_CGR_PJ); in pm_mpmu_clk_enable()
[all …]
/arch/arm/mach-pxa/
Dsmemc.c35 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
36 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
37 __raw_writel(sxcnfg, SXCNFG); in pxa3xx_smemc_resume()
38 __raw_writel(memclkcfg, MEMCLKCFG); in pxa3xx_smemc_resume()
39 __raw_writel(csadrcfg[0], CSADRCFG0); in pxa3xx_smemc_resume()
40 __raw_writel(csadrcfg[1], CSADRCFG1); in pxa3xx_smemc_resume()
41 __raw_writel(csadrcfg[2], CSADRCFG2); in pxa3xx_smemc_resume()
42 __raw_writel(csadrcfg[3], CSADRCFG3); in pxa3xx_smemc_resume()
44 __raw_writel(0x2, CSMSADRCFG); in pxa3xx_smemc_resume()
63 __raw_writel(0x2, CSMSADRCFG); in smemc_init()
/arch/sh/mm/
Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
35 __raw_writel(get_asid(), MMU_PTEAEX); in __update_tlb()
47 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
56 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
101 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
/arch/arm/mach-imx/
Dcpu.c32 __raw_writel(0x77777777, base + 0x0); in imx_set_aips()
33 __raw_writel(0x77777777, base + 0x4); in imx_set_aips()
40 __raw_writel(0x0, base + 0x40); in imx_set_aips()
41 __raw_writel(0x0, base + 0x44); in imx_set_aips()
42 __raw_writel(0x0, base + 0x48); in imx_set_aips()
43 __raw_writel(0x0, base + 0x4C); in imx_set_aips()
45 __raw_writel(reg, base + 0x50); in imx_set_aips()
/arch/arm/mach-at91/
Dgpio.c151 __raw_writel(mask, pio + PIO_IDR); in at91_set_GPIO_periph()
152 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); in at91_set_GPIO_periph()
153 __raw_writel(mask, pio + PIO_PER); in at91_set_GPIO_periph()
170 __raw_writel(mask, pio + PIO_IDR); in at91_set_A_periph()
171 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); in at91_set_A_periph()
173 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, in at91_set_A_periph()
175 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, in at91_set_A_periph()
178 __raw_writel(mask, pio + PIO_ASR); in at91_set_A_periph()
180 __raw_writel(mask, pio + PIO_PDR); in at91_set_A_periph()
197 __raw_writel(mask, pio + PIO_IDR); in at91_set_B_periph()
[all …]
/arch/arm/mach-s3c24xx/
Dpm-s3c2416.c31 __raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG); in s3c2416_cpu_suspend()
34 __raw_writel(0x2BED, S3C2443_PWRMODE); in s3c2416_cpu_suspend()
49 __raw_writel(0x2BED, S3C2412_INFORM0); in s3c2416_pm_prepare()
50 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); in s3c2416_pm_prepare()
78 __raw_writel(0x0, S3C2443_PWRMODE); in s3c2416_pm_resume()
79 __raw_writel(0x0, S3C2412_INFORM0); in s3c2416_pm_resume()
80 __raw_writel(0x0, S3C2412_INFORM1); in s3c2416_pm_resume()
Dmach-n30.c408 __raw_writel(0x007fffff, S3C2410_GPACON); in n30_hwinit()
410 __raw_writel(0x007fefff, S3C2410_GPACON); in n30_hwinit()
411 __raw_writel(0x00000000, S3C2410_GPADAT); in n30_hwinit()
426 __raw_writel(0x00154556, S3C2410_GPBCON); in n30_hwinit()
427 __raw_writel(0x00000750, S3C2410_GPBDAT); in n30_hwinit()
428 __raw_writel(0x00000073, S3C2410_GPBUP); in n30_hwinit()
445 __raw_writel(0xaaa80618, S3C2410_GPCCON); in n30_hwinit()
446 __raw_writel(0x0000014c, S3C2410_GPCDAT); in n30_hwinit()
447 __raw_writel(0x0000fef2, S3C2410_GPCUP); in n30_hwinit()
457 __raw_writel(0xaa95aaa4, S3C2410_GPDCON); in n30_hwinit()
[all …]
/arch/arm/mach-s3c24xx/include/mach/
Dpm-core.h23 __raw_writel(tmp, S3C2410_CLKCON); in s3c_pm_debug_init_uart()
29 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); in s3c_pm_arch_prepare_irqs()
30 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); in s3c_pm_arch_prepare_irqs()
34 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); in s3c_pm_arch_prepare_irqs()
35 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); in s3c_pm_arch_prepare_irqs()
36 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); in s3c_pm_arch_prepare_irqs()
42 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ in s3c_pm_arch_stop_clocks()
/arch/sh/kernel/cpu/sh4a/
Dubc.c37 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx)); in sh4a_ubc_enable()
38 __raw_writel(info->address, UBC_CAR(idx)); in sh4a_ubc_enable()
43 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
44 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
53 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
62 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
85 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
115 __raw_writel(0, UBC_CBCR); in sh4a_ubc_init()
118 __raw_writel(0, UBC_CAMR(i)); in sh4a_ubc_init()
119 __raw_writel(0, UBC_CBR(i)); in sh4a_ubc_init()
[all …]
/arch/arm/mach-exynos/
Dpm.c113 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); in exynos_pm_prepare()
119 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); in exynos_pm_prepare()
123 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); in exynos_pm_prepare()
168 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK); in exynos4_restore_pll()
186 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK); in exynos4_restore_pll()
227 __raw_writel(tmp, S5P_WAKEUP_MASK); in exynos_pm_drvinit()
250 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); in exynos_pm_suspend()
255 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); in exynos_pm_suspend()
285 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); in exynos_pm_resume()
287 __raw_writel(0x0, S5P_WAKEUP_STAT); in exynos_pm_resume()
[all …]
/arch/sh/drivers/pci/
Dpci-sh7780.c130 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
143 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
157 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
172 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
203 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \ in sh7780_pci_setup_irqs()
208 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \ in sh7780_pci_setup_irqs()
234 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
244 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
261 __raw_writel(PCIECR_ENBL, PCIECR); in sh7780_pci_init()
264 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST | PCICR_ENDIANNESS, in sh7780_pci_init()
[all …]
/arch/sh/boards/mach-sh7763rdp/
Dirq.c31 __raw_writel(1 << 25, INTC_INT2MSKCR); in init_sh7763rdp_IRQ()
34 __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000, in init_sh7763rdp_IRQ()
38 __raw_writel(1 << 17, INTC_INT2MSKCR1); in init_sh7763rdp_IRQ()
41 __raw_writel(1 << 16, INTC_INT2MSKCR1); in init_sh7763rdp_IRQ()
44 __raw_writel(1 << 8, INTC_INT2MSKCR); in init_sh7763rdp_IRQ()
/arch/mips/pci/
Dops-tx4927.c68 __raw_writel(((bus->number & 0xff) << 0x10) in mkaddr()
73 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
88 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
134 __raw_writel(val, &pcicptr->g2pcfgdata); in icd_writel()
242 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
250 __raw_writel((channel->io_resource->end - channel->io_resource->start) in tx4927_pcic_setup()
264 __raw_writel(0, &pcicptr->g2pmmask[i]); in tx4927_pcic_setup()
269 __raw_writel((channel->mem_resource->end in tx4927_pcic_setup()
284 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ in tx4927_pcic_setup()
287 __raw_writel(0, &pcicptr->p2gm0plbase); in tx4927_pcic_setup()
[all …]
/arch/arm/mach-w90x900/
Dtime.c61 __raw_writel(timer0_load, REG_TICR0); in nuc900_clockevent_setmode()
75 __raw_writel(val, REG_TCSR0); in nuc900_clockevent_setmode()
83 __raw_writel(evt, REG_TICR0); in nuc900_clockevent_setnextevent()
87 __raw_writel(val, REG_TCSR0); in nuc900_clockevent_setnextevent()
106 __raw_writel(0x01, REG_TISR); /* clear TIF0 */ in nuc900_timer0_interrupt()
125 __raw_writel(0x00, REG_TCSR0); in nuc900_clockevents_init()
132 __raw_writel(RESETINT, REG_TISR); in nuc900_clockevents_init()
149 __raw_writel(0x00, REG_TCSR1); in nuc900_clocksource_init()
154 __raw_writel(0xffffffff, REG_TICR1); in nuc900_clocksource_init()
158 __raw_writel(val, REG_TCSR1); in nuc900_clocksource_init()
/arch/m68k/platform/coldfire/
Dpci.c89 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_readconfig()
105 __raw_writel(0, PCICAR); in mcf_pci_readconfig()
121 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_writeconfig()
132 __raw_writel(cpu_to_le32(value), addr); in mcf_pci_writeconfig()
137 __raw_writel(0, PCICAR); in mcf_pci_writeconfig()
204 __raw_writel(cpu_to_le32(v), iospace + (addr & PCI_IO_MASK)); in mcf_pci_outl()
264 __raw_writel(PCIGSCR_RESET, PCIGSCR); in mcf_pci_init()
265 __raw_writel(0, PCITCR); in mcf_pci_init()
271 __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) | in mcf_pci_init()
279 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | in mcf_pci_init()
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