| /arch/arm/mach-omap2/ |
| D | sram34xx.S | 138 ldr r4, [sp, #52]
140 ldr r4, [sp, #56]
142 ldr r4, [sp, #60]
144 ldr r4, [sp, #64]
146 ldr r4, [sp, #68]
150 ldr r4, [sp, #72]
152 ldr r4, [sp, #76]
154 ldr r4, [sp, #80]
184 ldr r11, omap3_sdrc_dlla_ctrl
185 ldr r12, [r11]
[all …]
|
| D | sleep34xx.S | 101 ldr r12, high_mask
103 ldr r12, sram_phy_addr_mask
168 ldr r4, omap3_do_wfi_sram_addr
169 ldr r5, [r4]
185 ldr r1, kernel_flush
204 ldr r1, kernel_flush
244 ldr r4, sdrc_power @ read the SDRC_POWER register
245 ldr r5, [r4] @ read the contents of SDRC_POWER
290 ldr r4, cm_idlest_ckgen
292 ldr r5, [r4]
[all …]
|
| D | sleep44xx.S | 74 ldr r9, [r0, #OMAP_TYPE_OFFSET]
80 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
113 ldr r9, [r8, #OMAP_TYPE_OFFSET]
122 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
167 ldr r0, =0xffff
170 ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
171 ldr r1, =0xffff
185 ldr r0, [r2, #L2X0_CACHE_SYNC]
216 ldr r9, [r8, #OMAP_TYPE_OFFSET]
222 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
[all …]
|
| D | omap-headsmp.S | 36 wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
37 ldr r0, [r2]
53 hold: ldr r12,=0x103
70 hold_2: ldr r12,=0x103
94 ldr r1, =OMAP44XX_GIC_DIST_BASE
95 ldr r0, [r1]
|
| /arch/arm/plat-samsung/ |
| D | s5p-sleep.S | 58 ldr r1, =CPU_MASK
60 ldr r1, =CPU_CORTEX_A9
64 ldr r0, [r0]
65 ldr r1, [r0, #L2X0_R_PHY_BASE]
66 ldr r2, [r1, #L2X0_CTRL]
69 ldr r2, [r0, #L2X0_R_AUX_CTRL]
71 ldr r2, [r0, #L2X0_R_TAG_LATENCY]
73 ldr r2, [r0, #L2X0_R_DATA_LATENCY]
75 ldr r2, [r0, #L2X0_R_PREFETCH_CTRL]
77 ldr r2, [r0, #L2X0_R_PWR_CTRL]
|
| /arch/arm/lib/ |
| D | io-readsw-armv3.S | 24 ldr r3, [r0]
45 .Linsw_8_lp: ldr r3, [r0]
47 ldr r4, [r0]
50 ldr r4, [r0]
52 ldr r5, [r0]
55 ldr r5, [r0]
57 ldr r6, [r0]
60 ldr r6, [r0]
62 ldr lr, [r0]
76 ldr r3, [r0]
[all …]
|
| /arch/arm/mach-davinci/ |
| D | sleep.S | 55 ldr ip, CACHE_FLUSH
65 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
70 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
85 ldr ip, [r3, #PLLDIV1]
90 ldr ip, [r3, #PLLCTL]
101 ldr ip, [r3, #PLLCTL]
106 ldr ip, [r4]
114 ldr ip, [r4]
121 ldr ip, [r3, #PLLCTL]
126 ldr ip, [r3, #PLLCTL]
[all …]
|
| /arch/arm/mach-imx/ |
| D | ssi-fiq.S | 45 ldr r12, .L_imx_ssi_fiq_base
48 ldr r13, .L_imx_ssi_fiq_tx_buffer
51 ldr r11, [r12, #SSI_SIER]
56 ldr r11, [r12, #SSI_SISR]
87 ldr r11, [r12, #SSI_SIER]
92 ldr r11, [r12, #SSI_SISR]
96 ldr r13, .L_imx_ssi_fiq_rx_buffer
104 ldr r11, [r12, #SSI_SACNT]
107 ldr r11, [r12, #SSI_SRX0]
110 ldr r11, [r12, #SSI_SRX0]
[all …]
|
| /arch/arm/mach-prima2/ |
| D | sleep.S | 22 ldr r0, =sirfsoc_memc_base
23 ldr r5, [r0]
25 ldr r0, =sirfsoc_pwrc_base
26 ldr r6, [r0]
28 ldr r0, =sirfsoc_rtciobrg_base
29 ldr r7, [r0]
43 ldr r2, [r5, #DENALI_CTL_22_OFF]
52 ldr r4, [r5, #DENALI_CTL_112_OFF]
61 ldr r3, [r7]
|
| /arch/arm/mach-pxa/ |
| D | standby.S | 22 ldr r0, =PSSR
26 ldr ip, [r3]
62 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
69 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
72 1: ldr r0, [r1, #PXA3_DDR_HCAL]
76 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
83 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
87 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
92 1: ldr r0, [r1, #PXA3_DMCISR]
96 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
[all …]
|
| /arch/arm/mach-davinci/include/mach/ |
| D | entry-macro.S | 14 ldr \base, =davinci_intc_base
15 ldr \base, [\base]
20 ldr \tmp, =davinci_intc_type
21 ldr \tmp, [\tmp]
26 ldr \tmp, [\base, #0x14]
32 1001: ldr \irqnr, [\base, #0x80] /* get irq number */
|
| /arch/arm/mach-mv78xx0/include/mach/ |
| D | entry-macro.S | 14 ldr \base, =IRQ_VIRT_BASE
19 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
20 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
26 ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
27 ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF]
33 ldr \irqstat, [\base, #IRQ_CAUSE_ERR_OFF]
34 ldr \tmp, [\base, #IRQ_MASK_ERR_OFF]
|
| /arch/arm/mach-omap1/include/mach/ |
| D | entry-macro.S | 20 ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
21 ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
22 ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
28 ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
29 ldr \tmp, =omap_irq_flags @ irq flags address
30 ldr \tmp, [\tmp, #0] @ irq flags value
|
| /arch/arm/kvm/ |
| D | interrupts_head.S | 178 ldr r2, [vcpu, #VCPU_PC]
179 ldr r3, [vcpu, #VCPU_CPSR]
184 ldr r2, [vcpu, #VCPU_USR_SP]
185 ldr r3, [vcpu, #VCPU_USR_LR]
324 ldr r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
332 ldr r2, [vcpu, #CP15_OFFSET(c13_CID)]
333 ldr r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
334 ldr r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
335 ldr r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
336 ldr r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
[all …]
|
| /arch/arm/mach-sa1100/ |
| D | sleep.S | 36 ldr r6, =MDREFR
37 ldr r4, [r6]
39 ldr r5, =PPCR
81 ldr r0, =MSC0
82 ldr r1, =MSC1
83 ldr r2, =MSC2
85 ldr r3, [r0]
89 ldr r4, [r1]
93 ldr r5, [r2]
97 ldr r7, [r6]
[all …]
|
| /arch/arm/mach-at91/ |
| D | pm_slowclock.S | 57 ldr tmp1, [pmc, #AT91_PMC_SR]
71 ldr tmp1, [pmc, #AT91_PMC_SR]
85 ldr tmp1, [pmc, #AT91_PMC_SR]
99 ldr tmp1, [pmc, #AT91_PMC_SR]
147 ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
170 ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
179 ldr tmp1, [pmc, #AT91_PMC_MCKR]
203 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
211 ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
218 ldr tmp1, [pmc, #AT91_CKGR_MOR]
[all …]
|
| D | at91sam9_alt_reset.S | 25 at91sam9_alt_restart: ldr r0, =at91_ramc_base @ preload constants
26 ldr r0, [r0]
27 ldr r4, =at91_rstc_base
28 ldr r1, [r4]
32 ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
|
| D | at91sam9g45_reset.S | 22 ldr r5, =at91_ramc_base @ preload constants
23 ldr r0, [r5]
24 ldr r4, =at91_rstc_base
25 ldr r1, [r4]
29 ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
|
| /arch/arm/include/debug/ |
| D | samsung.S | 17 ldr \rd, [\rx, # S3C2410_UFSTAT]
22 ldr \rd, [\rx, # S3C2410_UFSTAT]
30 ldr \rd, [\rx, # S3C2410_UFSTAT]
39 ldr \rd, [\rx, # S3C2410_UFSTAT]
52 ldr \rd, [\rx, # S3C2410_UFCON]
63 ldr \rd, [\rx, # S3C2410_UTRSTAT]
71 ldr \rd, [\rx, # S3C2410_UFCON]
82 ldr \rd, [\rx, # S3C2410_UTRSTAT]
|
| /arch/arm/boot/compressed/ |
| D | head-shmobile.S | 31 ldr r0, __image_start
32 ldr r1, __image_end
34 ldr r0, __load_base
38 ldr r0, __loaded
39 ldr r1, __image_start
41 ldr r1, __load_base
76 ldr r7, 1f @ Set machine type register
|
| D | head-sharpsl.S | 27 ldr r7, .TOSAID
37 ldr r3, .PXA270ID
42 ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
53 ldr r6, [r1, #0] @ Load Chip ID
54 ldr r3, .W100ID
55 ldr r7, .POODLEID
60 ldr r7, .CORGIID
61 ldr r3, .PXA255ID
67 ldr r7, .SHEPHERDID
72 ldr r7, .HUSKYID @ Must be Husky
[all …]
|
| /arch/arm/mach-msm/include/mach/ |
| D | debug-macro.S | 23 ldr \rp, =MSM_DEBUG_UART_PHYS
24 ldr \rv, =MSM_DEBUG_UART_BASE
40 ldr \rd, [\rx, #0x08]
44 1001: ldr \rd, [\rx, #0x14]
55 ldr \rd, [\rx, #0x08]
58 1001: ldr \rd, [\rx, #0x08]
|
| /arch/arm/kernel/ |
| D | relocate_kernel.S | 10 ldr r0,kexec_indirection_page
11 ldr r1,kexec_start_address
21 ldr r3, [r0],#4
48 ldr r5,[r3],#4
58 ldr r1,kexec_mach_type
59 ldr r2,kexec_boot_atags
|
| /arch/arm/mach-kirkwood/include/mach/ |
| D | entry-macro.S | 14 ldr \base, =IRQ_VIRT_BASE
19 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
20 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
26 ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
27 ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF]
|
| /arch/arm/crypto/ |
| D | sha1-armv4-large.S | 64 ldr r8,.LK_00_19
83 ldr r9,[r1],#4 @ handles unaligned
108 ldr r9,[r1],#4 @ handles unaligned
133 ldr r9,[r1],#4 @ handles unaligned
158 ldr r9,[r1],#4 @ handles unaligned
183 ldr r9,[r1],#4 @ handles unaligned
211 ldr r9,[r1],#4 @ handles unaligned
224 ldr r9,[r14,#15*4]
225 ldr r10,[r14,#13*4]
226 ldr r11,[r14,#7*4]
[all …]
|