1/* 2 * reset AT91SAM9G45 as per errata 3 * 4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com> 5 * 6 * unless the SDRAM is cleanly shutdown before we hit the 7 * reset register it can be left driving the data bus and 8 * killing the chance of a subsequent boot from NAND 9 * 10 * GPLv2 Only 11 */ 12 13#include <linux/linkage.h> 14#include <mach/hardware.h> 15#include <mach/at91_ramc.h> 16#include "at91_rstc.h" 17 .arm 18 19 .globl at91sam9g45_restart 20 21at91sam9g45_restart: 22 ldr r5, =at91_ramc_base @ preload constants 23 ldr r0, [r5] 24 ldr r4, =at91_rstc_base 25 ldr r1, [r4] 26 27 mov r2, #1 28 mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN 29 ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST 30 31 .balign 32 @ align to cache line 32 33 str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access 34 str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 35 str r4, [r1, #AT91_RSTC_CR] @ reset processor 36 37 b . 38