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Searched refs:CSR8 (Results 1 – 12 of 12) sorted by relevance

/drivers/net/wireless/rt2x00/
Drt2400pci.c990 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); in rt2400pci_toggle_irq()
996 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_toggle_irq()
1326 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); in rt2400pci_enable_interrupt()
1328 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_enable_interrupt()
1351 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); in rt2400pci_txstatus_tasklet()
1355 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_txstatus_tasklet()
1425 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); in rt2400pci_interrupt()
1427 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_interrupt()
Drt2500pci.c1144 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); in rt2500pci_toggle_irq()
1150 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_toggle_irq()
1454 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); in rt2500pci_enable_interrupt()
1456 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_enable_interrupt()
1479 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); in rt2500pci_txstatus_tasklet()
1483 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_txstatus_tasklet()
1553 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); in rt2500pci_interrupt()
1555 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_interrupt()
Drt2400pci.h149 #define CSR8 0x0020 macro
Drt2500pci.h200 #define CSR8 0x0020 macro
/drivers/net/ethernet/amd/
Dariadne.h68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */ macro
Dariadne.c432 lance->RAP = CSR8; /* Logical Address Filter, LADRF[15:0] */ in ariadne_open()
669 lance->RAP = CSR8 + (i << 8); in set_multicast_list()
Dsun3lance.c206 #define CSR8 8 /* address filter */ macro
921 REGA( CSR8+i ) = multicast_table[i]; in set_multicast_list()
Datarilance.c307 #define CSR8 8 /* address filter */ macro
1100 REGA( CSR8+i ) = multicast_table[i]; in set_multicast_list()
/drivers/net/ethernet/dec/tulip/
Dinterrupt.c689 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff; in tulip_interrupt()
805 if ((missed = ioread32(ioaddr + CSR8) & 0x1ffff)) {
Dtulip.h114 CSR8 = 0x40, enumerator
Dtulip_core.c782 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff; in tulip_down()
863 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff; in tulip_get_stats()
1517 ioread32(ioaddr + CSR8); in tulip_init_one()
Dxircom_cb.c57 #define CSR8 0x40 macro