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Searched refs:PACKET0 (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/radeon/
Dr300.c183 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); in r300_fence_ring_emit()
185 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); in r300_fence_ring_emit()
188 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r300_fence_ring_emit()
190 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); in r300_fence_ring_emit()
193 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r300_fence_ring_emit()
197 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r300_fence_ring_emit()
200 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r300_fence_ring_emit()
203 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r300_fence_ring_emit()
205 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); in r300_fence_ring_emit()
236 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); in r300_ring_start()
[all …]
Drv515.c70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
84 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start()
86 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start()
88 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); in rv515_ring_start()
90 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); in rv515_ring_start()
92 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
[all …]
Dr200.c104 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
112 radeon_ring_write(ring, PACKET0(0x720, 2)); in r200_copy_dma()
119 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
Dradeon_uvd.c576 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); in radeon_uvd_send_msg()
578 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); in radeon_uvd_send_msg()
580 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); in radeon_uvd_send_msg()
Dr600.c2654 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in r600_uvd_rbc_start()
2658 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in r600_uvd_rbc_start()
2662 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in r600_uvd_rbc_start()
2667 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); in r600_uvd_rbc_start()
2670 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); in r600_uvd_rbc_start()
2913 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in r600_uvd_ring_test()
2980 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); in r600_fence_ring_emit()
2991 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in r600_uvd_fence_emit()
2993 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in r600_uvd_fence_emit()
2995 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in r600_uvd_fence_emit()
[all …]
Dr100.c854 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); in r100_fence_ring_emit()
856 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); in r100_fence_ring_emit()
859 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r100_fence_ring_emit()
861 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r100_fence_ring_emit()
864 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r100_fence_ring_emit()
867 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r100_fence_ring_emit()
869 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); in r100_fence_ring_emit()
942 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); in r100_copy_blit()
944 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r100_copy_blit()
979 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); in r100_ring_start()
[all …]
Dr420.c212 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); in r420_cp_errata_init()
226 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r420_cp_errata_fini()
Dni.c1232 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in cayman_uvd_semaphore_emit()
1235 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in cayman_uvd_semaphore_emit()
1238 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in cayman_uvd_semaphore_emit()
2440 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0)); in cayman_vm_flush()
2444 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); in cayman_vm_flush()
2448 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); in cayman_vm_flush()
Dr300d.h60 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
Dnid.h507 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
Dsid.h844 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
Drv515d.h200 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
Dr100d.h59 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
Devergreend.h1046 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
Dr600d.h1218 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro