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Searched refs:REG_READ (Results 1 – 25 of 61) sorted by relevance

123

/drivers/gpu/drm/gma500/
Dcdv_intel_display.c178 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
190 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
196 *val = REG_READ(SB_DATA); in cdv_sb_read()
213 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
226 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
247 REG_READ(DPIO_CFG); in cdv_sb_reset()
499 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { in cdv_intel_find_best_PLL()
506 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == in cdv_intel_find_best_PLL()
624 dspcntr = REG_READ(map->cntr); in cdv_intel_pipe_set_base()
652 REG_READ(map->base); in cdv_intel_pipe_set_base()
[all …]
Dcdv_device.c46 REG_READ(vga_reg); in cdv_disable_vga()
61 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
63 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
67 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
69 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
85 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; in cdv_backlight_combination_mode()
90 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
108 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in cdv_get_brightness()
144 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_set_brightness()
273 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); in cdv_save_display_registers()
[all …]
Dmdfld_intel_display.c73 temp = REG_READ(map->conf); in mdfldWaitForPipeDisable()
101 temp = REG_READ(map->conf); in mdfldWaitForPipeEnable()
134 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
152 dspcntr = REG_READ(dspcntr_reg); in mdfld__intel_plane_set_alpha()
221 dspcntr = REG_READ(map->cntr); in mdfld__intel_pipe_set_base()
244 REG_READ(map->linoff); in mdfld__intel_pipe_set_base()
246 REG_READ(map->surf); in mdfld__intel_pipe_set_base()
271 temp = REG_READ(map->cntr); in mdfld_disable_crtc()
276 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_disable_crtc()
277 REG_READ(map->base); in mdfld_disable_crtc()
[all …]
Doaktrail_crtc.c187 temp = REG_READ(map->dpll); in oaktrail_crtc_dpms()
190 REG_READ(map->dpll); in oaktrail_crtc_dpms()
194 REG_READ(map->dpll); in oaktrail_crtc_dpms()
198 REG_READ(map->dpll); in oaktrail_crtc_dpms()
203 temp = REG_READ(map->conf); in oaktrail_crtc_dpms()
207 temp = REG_READ(map->cntr); in oaktrail_crtc_dpms()
212 REG_WRITE(map->base, REG_READ(map->base)); in oaktrail_crtc_dpms()
229 temp = REG_READ(map->cntr); in oaktrail_crtc_dpms()
234 REG_WRITE(map->base, REG_READ(map->base)); in oaktrail_crtc_dpms()
235 REG_READ(map->base); in oaktrail_crtc_dpms()
[all …]
Dpsb_intel_display.c182 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { in psb_intel_find_best_PLL()
189 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == in psb_intel_find_best_PLL()
273 dspcntr = REG_READ(map->cntr); in psb_intel_pipe_set_base()
299 REG_READ(map->base); in psb_intel_pipe_set_base()
334 temp = REG_READ(map->dpll); in psb_intel_crtc_dpms()
337 REG_READ(map->dpll); in psb_intel_crtc_dpms()
341 REG_READ(map->dpll); in psb_intel_crtc_dpms()
345 REG_READ(map->dpll); in psb_intel_crtc_dpms()
351 temp = REG_READ(map->conf); in psb_intel_crtc_dpms()
356 temp = REG_READ(map->cntr); in psb_intel_crtc_dpms()
[all …]
Dpsb_intel_lvds.c77 ret = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
89 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
201 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_set_backlight()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
235 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
246 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
275 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); in psb_intel_lvds_save()
276 lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); in psb_intel_lvds_save()
277 lvds_priv->saveLVDS = REG_READ(LVDS); in psb_intel_lvds_save()
[all …]
Doaktrail_hdmi.c297 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
313 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
361 dspcntr = REG_READ(dspcntr_reg); in oaktrail_crtc_hdmi_mode_set()
367 pipeconf = REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
371 REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
374 REG_READ(PCH_PIPEBCONF); in oaktrail_crtc_hdmi_mode_set()
397 temp = REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
400 REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
402 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); in oaktrail_crtc_hdmi_dpms()
403 REG_READ(DSPBSURF); in oaktrail_crtc_hdmi_dpms()
[all …]
Dintel_gmbus.c105 reserved = REG_READ(gpio->reg) & in get_reserved()
120 return (REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0; in get_clock()
131 return (REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0; in get_data()
149 REG_READ(gpio->reg); /* Posting */ in set_clock()
167 REG_READ(gpio->reg); in set_data()
275 REG_READ(GMBUS2+reg_offset); in gmbus_xfer()
279 if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) in gmbus_xfer()
281 if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) in gmbus_xfer()
284 val = REG_READ(GMBUS3 + reg_offset); in gmbus_xfer()
304 REG_READ(GMBUS2+reg_offset); in gmbus_xfer()
[all …]
Dpsb_lid.c40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
42 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
46 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func()
56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
58 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
Dcdv_intel_dp.c195 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
199 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
209 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
213 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
228 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
233 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
235 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { in cdv_intel_edp_panel_on()
236 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); in cdv_intel_edp_panel_on()
253 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
266 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
[all …]
Dmdfld_dsi_dpi.c46 (REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) { in mdfld_wait_for_HS_DATA_FIFO()
63 while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg) in mdfld_wait_for_HS_CTRL_FIFO()
80 while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) & in mdfld_wait_for_DPI_CTRL_FIFO()
98 while ((timeout < 20000) && (!(REG_READ(intr_stat_reg) in mdfld_wait_for_SPL_PKG_SENT()
147 REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
151 REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in dsi_set_pipe_plane_enable_state()
158 REG_READ(dspbase_reg); in dsi_set_pipe_plane_enable_state()
573 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
583 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
[all …]
Dintel_i2c.c39 val = REG_READ(chan->reg); in get_clock()
49 val = REG_READ(chan->reg); in get_data()
61 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
81 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_data()
Dcdv_intel_crt.c45 temp = REG_READ(reg); in cdv_intel_crt_dpms()
116 dpll_md = REG_READ(dpll_md_reg); in cdv_intel_crt_mode_set()
156 orig = hotplug_en = REG_READ(PORT_HOTPLUG_EN); in cdv_intel_crt_detect_hotplug()
170 if (!(REG_READ(PORT_HOTPLUG_EN) & in cdv_intel_crt_detect_hotplug()
177 if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) != in cdv_intel_crt_detect_hotplug()
Doaktrail_lvds.c56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
59 pp_status = REG_READ(PP_STATUS); in oaktrail_lvds_set_power()
67 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
70 pp_status = REG_READ(PP_STATUS); in oaktrail_lvds_set_power()
113 lvds_port = (REG_READ(LVDS) & in oaktrail_lvds_mode_set()
176 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in oaktrail_lvds_prepare()
189 ret = ((REG_READ(BLC_PWM_CTL) & in oaktrail_lvds_get_max_backlight()
Dcdv_intel_lvds.c75 retval = ((REG_READ(BLC_PWM_CTL) & in cdv_intel_lvds_get_max_backlight()
183 REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_intel_lvds_set_backlight()
209 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
212 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
223 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
331 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in cdv_intel_lvds_prepare()
745 lvds = REG_READ(LVDS); in cdv_intel_lvds_init()
770 pwm = REG_READ(BLC_PWM_CTL2); in cdv_intel_lvds_init()
/drivers/net/wireless/ath/ath9k/
Dar9002_calib.c90 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
125 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
127 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
129 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
144 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
146 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
148 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
168 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
170 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
[all …]
Dar9002_mac.c42 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { in ar9002_hw_get_isr()
43 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) in ar9002_hw_get_isr()
45 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
49 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & in ar9002_hw_get_isr()
58 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
64 isr2 = REG_READ(ah, AR_ISR_S2); in ar9002_hw_get_isr()
81 isr = REG_READ(ah, AR_ISR_RAC); in ar9002_hw_get_isr()
100 s0_s = REG_READ(ah, AR_ISR_S0_S); in ar9002_hw_get_isr()
104 s1_s = REG_READ(ah, AR_ISR_S1_S); in ar9002_hw_get_isr()
123 s5_s = REG_READ(ah, AR_ISR_S5_S); in ar9002_hw_get_isr()
[all …]
Dar9003_mci.c38 if (!(REG_READ(ah, address) & bit_position)) { in ar9003_mci_wait_for_interrupt()
70 REG_READ(ah, AR_MCI_INTERRUPT_RAW), in ar9003_mci_wait_for_interrupt()
71 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); in ar9003_mci_wait_for_interrupt()
231 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN); in ar9003_mci_prep_interface()
235 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); in ar9003_mci_prep_interface()
237 REG_READ(ah, AR_MCI_INTERRUPT_RAW)); in ar9003_mci_prep_interface()
350 intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); in ar9003_mci_check_int()
374 rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); in ar9003_mci_get_isr()
375 raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); in ar9003_mci_get_isr()
386 mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS); in ar9003_mci_get_isr()
[all …]
Dmac.c48 return REG_READ(ah, AR_QTXDP(q)); in ath9k_hw_gettxbuf()
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ath9k_hw_numtxpending()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
114 txcfg = REG_READ(ah, AR_TXCFG); in ath9k_hw_updatetxtriglevel()
656 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_setrxabort()
713 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) in ath9k_hw_stopdmarecv()
717 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; in ath9k_hw_stopdmarecv()
733 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
734 REG_READ(ah, AR_DIAG_SW), in ath9k_hw_stopdmarecv()
735 REG_READ(ah, AR_DMADBG_7)); in ath9k_hw_stopdmarecv()
[all …]
Dar9003_phy.c544 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); in ar9003_hw_set_channel_regs()
561 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); in ar9003_hw_set_channel_regs()
586 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_init_bb()
629 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); in ar9003_hw_override_ini()
797 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) in ar9003_hw_process_ini()
896 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_rfbus_done()
1128 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1135 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1186 val = REG_READ(ah, AR_PHY_SFCORR); in ar9003_hw_ani_cache_ini_regs()
1191 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar9003_hw_ani_cache_ini_regs()
[all …]
Dhw.c176 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
184 timeout, reg, REG_READ(ah, reg), mask, val); in ath9k_hw_wait()
332 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
338 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
346 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; in ath9k_hw_read_revisions()
349 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
413 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
417 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
428 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
580 ah->WARegVal = REG_READ(ah, AR_WA); in __ath9k_hw_init()
[all …]
Dar9002_phy.c76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
242 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
443 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), in ar9002_olc_init()
481 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ar9002_hw_do_getnf()
484 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
491 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); in ar9002_hw_do_getnf()
494 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
528 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
544 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
Dar9003_mac.c190 async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE); in ar9003_hw_get_isr()
193 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) in ar9003_hw_get_isr()
195 isr = REG_READ(ah, AR_ISR); in ar9003_hw_get_isr()
199 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; in ar9003_hw_get_isr()
209 isr2 = REG_READ(ah, AR_ISR_S2); in ar9003_hw_get_isr()
235 isr = REG_READ(ah, AR_ISR_RAC); in ar9003_hw_get_isr()
263 s0 = REG_READ(ah, AR_ISR_S0); in ar9003_hw_get_isr()
265 s1 = REG_READ(ah, AR_ISR_S1); in ar9003_hw_get_isr()
277 s5 = REG_READ(ah, AR_ISR_S5_S); in ar9003_hw_get_isr()
279 s5 = REG_READ(ah, AR_ISR_S5); in ar9003_hw_get_isr()
[all …]
Dar5008_phy.c204 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar5008_hw_set_channel()
301 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
550 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_init_bb()
597 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ar5008_hw_init_chain_masks()
613 val = REG_READ(ah, AR_PCU_MISC_MODE2); in ar5008_hw_override_ini()
640 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); in ar5008_hw_override_ini()
653 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & in ar5008_hw_set_channel_regs()
871 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_rfbus_done()
1179 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ar5008_hw_do_getnf()
1182 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); in ar5008_hw_do_getnf()
[all …]
/drivers/net/wireless/ath/
Dhw.c23 #define REG_READ (common->ops->read) macro
124 id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK; in ath_hw_setbssidmask()
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
152 busy = REG_READ(ah, AR_RCCNT); in ath_hw_cycle_counters_update()
153 rx = REG_READ(ah, AR_RFCNT); in ath_hw_cycle_counters_update()
154 tx = REG_READ(ah, AR_TFCNT); in ath_hw_cycle_counters_update()

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