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Searched refs:csio_rd_reg32 (Results 1 – 7 of 7) sorted by relevance

/drivers/scsi/csiostor/
Dcsio_hw_t5.c62 csio_rd_reg32(hw, in csio_t5_set_mem_win()
186 if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST) in csio_t5_mc_read()
201 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i))); in csio_t5_mc_read()
242 if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST) in csio_t5_edc_read()
257 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i))); in csio_t5_edc_read()
301 edc_size = EDRAM_SIZE_GET(csio_rd_reg32(hw, MA_EDRAM0_BAR)); in csio_t5_memory_rw()
305 mc_size = EXT_MEM_SIZE_GET(csio_rd_reg32(hw, in csio_t5_memory_rw()
322 mem_reg = csio_rd_reg32(hw, in csio_t5_memory_rw()
348 csio_rd_reg32(hw, in csio_t5_memory_rw()
353 *buf++ = csio_rd_reg32(hw, mem_base + offset); in csio_t5_memory_rw()
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Dcsio_hw_t4.c102 csio_rd_reg32(hw, in csio_t4_set_mem_win()
212 if (csio_rd_reg32(hw, MC_BIST_CMD) & START_BIST) in csio_t4_mc_read()
227 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i))); in csio_t4_mc_read()
253 if (csio_rd_reg32(hw, EDC_BIST_CMD + idx) & START_BIST) in csio_t4_edc_read()
268 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i))); in csio_t4_edc_read()
310 edc_size = EDRAM_SIZE_GET(csio_rd_reg32(hw, MA_EDRAM0_BAR)); in csio_t4_memory_rw()
314 mc_size = EXT_MEM_SIZE_GET(csio_rd_reg32(hw, in csio_t4_memory_rw()
331 mem_reg = csio_rd_reg32(hw, in csio_t4_memory_rw()
360 csio_rd_reg32(hw, in csio_t4_memory_rw()
365 *buf++ = csio_rd_reg32(hw, mem_base + offset); in csio_t4_memory_rw()
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Dcsio_hw.c164 val = csio_rd_reg32(hw, reg); in csio_hw_wait_op_done_val()
193 val |= csio_rd_reg32(hw, TP_PIO_DATA) & ~mask; in csio_hw_tp_wr_bits_indirect()
201 uint32_t val = csio_rd_reg32(hw, reg) & ~mask; in csio_set_reg_field()
205 csio_rd_reg32(hw, reg); in csio_set_reg_field()
425 if (csio_rd_reg32(hw, SF_OP) & SF_BUSY) in csio_hw_sf1_read()
435 *valp = csio_rd_reg32(hw, SF_DATA); in csio_hw_sf1_read()
457 if (csio_rd_reg32(hw, SF_OP) & SF_BUSY) in csio_hw_sf1_write()
881 while (((reg = csio_rd_reg32(hw, PL_WHOAMI)) == 0xFFFFFFFF) && in csio_hw_dev_ready()
982 pcie_fw = csio_rd_reg32(hw, PCIE_FW); in csio_do_hello()
1280 if (!(csio_rd_reg32(hw, PCIE_FW) & PCIE_FW_HALT)) in csio_hw_fw_restart()
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Dcsio_mb.c1184 csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE)); in csio_mb_intr_enable()
1197 csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE)); in csio_mb_intr_disable()
1246 csio_rd_reg32(hw, ctl_reg); in csio_mb_debug_cmd_handler()
1303 owner = MBOWNER_GET(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue()
1308 owner = MBOWNER_GET(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue()
1357 csio_rd_reg32(hw, ctl_reg); in csio_mb_issue()
1372 ctl = csio_rd_reg32(hw, ctl_reg); in csio_mb_issue()
1542 pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE)); in csio_mb_isr_handler()
1543 cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE)); in csio_mb_isr_handler()
1559 ctl = csio_rd_reg32(hw, ctl_reg); in csio_mb_isr_handler()
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Dcsio_wr.c59 sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0 + in csio_get_flbuf_size()
1342 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2) + in csio_wr_fixup_host_params()
1346 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3) + in csio_wr_fixup_host_params()
1393 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL); in csio_wr_get_sge()
1419 timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1); in csio_wr_get_sge()
1420 timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3); in csio_wr_get_sge()
1421 timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5); in csio_wr_get_sge()
1436 ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD); in csio_wr_get_sge()
1465 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL); in csio_wr_set_sge()
Dcsio_hw.h556 #define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r))) macro
Dcsio_init.c131 i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE); in csio_setup_debugfs()