Searched refs:ep0_state (Results 1 – 17 of 17) sorted by relevance
514 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN; in ep0_rxstate()570 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT; in ep0_txstate()635 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT; in musb_read_setup()637 musb->ep0_state = MUSB_EP0_STAGE_TX; in musb_read_setup()644 musb->ep0_state = MUSB_EP0_STAGE_RX; in musb_read_setup()679 csr, len, decode_ep0stage(musb->ep0_state)); in musb_g_ep0_irq()694 musb->ep0_state = MUSB_EP0_STAGE_IDLE; in musb_g_ep0_irq()703 switch (musb->ep0_state) { in musb_g_ep0_irq()705 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT; in musb_g_ep0_irq()708 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN; in musb_g_ep0_irq()[all …]
419 enum musb_g_ep0_state ep0_state; member
2098 musb->ep0_state = MUSB_EP0_STAGE_SETUP; in musb_g_reset()
188 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep0_stall()651 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep_init()806 && (udc->ep0_state == WAIT_FOR_SETUP)) { in ep0_setup_handle()844 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep0_rx()1111 if ((ep->epnum == 0) && (udc->ep0_state == DATA_STATE_NEED_ZLP)) in qe_ep_tx()1258 udc->ep0_state = DATA_STATE_NEED_ZLP; in ep0_prime_status()1263 udc->ep0_state = WAIT_FOR_OUT_STATUS; in ep0_prime_status()1275 switch (udc->ep0_state) { in ep0_req_complete()1285 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()1297 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()[all …]
1041 udc->ep0_state = WAIT_FOR_SETUP; in fsl_ep_set_halt()1259 udc->ep0_state = WAIT_FOR_SETUP; in ep0stall()1276 if (udc->ep0_state != DATA_STATE_XMIT) in ep0_prime_status()1277 udc->ep0_state = WAIT_FOR_OUT_STATUS; in ep0_prime_status()1380 udc->ep0_state = DATA_STATE_XMIT; in ch9getstatus()1490 udc->ep0_state = (setup->bRequestType & USB_DIR_IN) in setup_received_irq()1496 if (udc->ep0_state == DATA_STATE_XMIT) in setup_received_irq()1508 udc->ep0_state = WAIT_FOR_OUT_STATUS; in setup_received_irq()1526 switch (udc->ep0_state) { in ep0_req_complete()1529 udc->ep0_state = WAIT_FOR_OUT_STATUS; in ep0_req_complete()[all …]
69 enum ep0_state { enum103 enum ep0_state ep0state;
60 enum ep0_state { enum
124 udc->ep0_state = WAIT_FOR_SETUP; in ep0_stall()753 udc->ep0_state = DATA_STATE_XMIT; in mv_ep_queue()943 udc->ep0_state = WAIT_FOR_SETUP; in mv_ep_set_halt_wedge()1353 udc->ep0_state = WAIT_FOR_SETUP; in mv_udc_start()1442 udc->ep0_state = WAIT_FOR_OUT_STATUS; in udc_prime_status()1549 udc->ep0_state = DATA_STATE_XMIT; in ch9getstatus()1697 udc->ep0_state = (setup->bRequestType & USB_DIR_IN) in handle_setup_packet()1707 udc->ep0_state = WAIT_FOR_OUT_STATUS; in handle_setup_packet()1727 switch (udc->ep0_state) { in ep0_req_complete()1739 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()[all …]
30 enum ep0_state { enum55 enum ep0_state ep0state;
382 enum ep0_state { enum452 enum ep0_state ep0state;
201 unsigned int ep0_state; /* Endpoint zero state */ member
269 unsigned int ep0_state; /* Endpoint zero state */ member
115 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP; in mv_u3d_ep0_stall()807 && u3d->ep0_state == MV_U3D_STATUS_STAGE in mv_u3d_ep_queue()810 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP; in mv_u3d_ep_queue()1428 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP; in mv_u3d_irq_process_link_change()1578 u3d->ep0_state = MV_U3D_STATUS_STAGE; in mv_u3d_handle_setup_packet()
340 u32 ep0_state; /* Enpoint zero state */ member
504 u32 ep0_state; /* Endpoint zero state */ member
83 enum ep0_state { enum116 enum ep0_state state; /* P: lock */992 enum ep0_state state; in ep0_read()
47 enum ep0_state stat);962 struct imx_udc_struct *imx_usb, enum ep0_state stat) in ep0_chg_stat()