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Searched refs:ew32 (Results 1 – 20 of 20) sorted by relevance

/drivers/net/ethernet/smsc/
Depic100.c186 #define ew32(reg, val) iowrite32(val, ioaddr + (reg)) macro
409 ew32(GENCTL, 0x4200); in epic_init_one()
413 ew32(TEST1, 0x0008); in epic_init_one()
416 ew32(MIICfg, 0x12); in epic_init_one()
418 ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800); in epic_init_one()
419 ew32(GENCTL, 0x0200); in epic_init_one()
473 ew32(NVCTL, er32(NVCTL) & ~0x483c); in epic_init_one()
474 ew32(GENCTL, 0x0008); in epic_init_one()
543 ew32(INTMASK, 0x00000000); in epic_disable_int()
558 ew32(INTMASK, ep->irq_mask & ~EpicNapiEvent); in epic_napi_irq_off()
[all …]
/drivers/net/ethernet/intel/e1000e/
D82571.c180 ew32(EECD, eecd); in e1000_init_nvm_params_82571()
309 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK); in e1000_init_mac_params_82571()
330 ew32(SWSM, swsm & ~E1000_SWSM_SMBI); in e1000_init_mac_params_82571()
496 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); in e1000_get_hw_semaphore_82571()
527 ew32(SWSM, swsm); in e1000_put_hw_semaphore_82571()
545 ew32(EXTCNF_CTRL, extcnf_ctrl); in e1000_get_hw_semaphore_82573()
578 ew32(EXTCNF_CTRL, extcnf_ctrl); in e1000_put_hw_semaphore_82573()
635 ew32(POEMB, data); in e1000_set_d0_lplu_state_82574()
662 ew32(POEMB, data); in e1000_set_d3_lplu_state_82574()
783 ew32(HICR, E1000_HICR_FW_RESET_ENABLE); in e1000_update_nvm_checksum_82571()
[all …]
Dmac.c250 ew32(RAL(index), rar_low); in e1000e_rar_set_generic()
252 ew32(RAH(index), rar_high); in e1000e_rar_set_generic()
506 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); in e1000e_check_for_fiber_link()
511 ew32(CTRL, ctrl); in e1000e_check_for_fiber_link()
526 ew32(TXCW, mac->txcw); in e1000e_check_for_fiber_link()
527 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); in e1000e_check_for_fiber_link()
569 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); in e1000e_check_for_serdes_link()
574 ew32(CTRL, ctrl); in e1000e_check_for_serdes_link()
589 ew32(TXCW, mac->txcw); in e1000e_check_for_serdes_link()
590 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); in e1000e_check_for_serdes_link()
[all …]
Dnvm.c41 ew32(EECD, *eecd); in e1000_raise_eec_clk()
56 ew32(EECD, *eecd); in e1000_lower_eec_clk()
87 ew32(EECD, eecd); in e1000_shift_out_eec_bits()
99 ew32(EECD, eecd); in e1000_shift_out_eec_bits()
181 ew32(EECD, eecd | E1000_EECD_REQ); in e1000e_acquire_nvm()
194 ew32(EECD, eecd); in e1000e_acquire_nvm()
216 ew32(EECD, eecd); in e1000_standby_nvm()
220 ew32(EECD, eecd); in e1000_standby_nvm()
258 ew32(EECD, eecd); in e1000e_release_nvm()
278 ew32(EECD, eecd); in e1000_ready_nvm_eeprom()
[all …]
D80003es2lan.c328 ew32(SW_FW_SYNC, swfw_sync); in e1000_acquire_swfw_sync_80003es2lan()
352 ew32(SW_FW_SYNC, swfw_sync); in e1000_release_swfw_sync_80003es2lan()
702 ew32(IMC, 0xffffffff); in e1000_reset_hw_80003es2lan()
704 ew32(RCTL, 0); in e1000_reset_hw_80003es2lan()
705 ew32(TCTL, E1000_TCTL_PSP); in e1000_reset_hw_80003es2lan()
717 ew32(CTRL, ctrl | E1000_CTRL_RST); in e1000_reset_hw_80003es2lan()
733 ew32(IMC, 0xffffffff); in e1000_reset_hw_80003es2lan()
789 ew32(TXDCTL(0), reg_data); in e1000_init_hw_80003es2lan()
795 ew32(TXDCTL(1), reg_data); in e1000_init_hw_80003es2lan()
800 ew32(TCTL, reg_data); in e1000_init_hw_80003es2lan()
[all …]
Dich8lan.c263 ew32(CTRL_EXT, mac_reg); in e1000_init_phy_workarounds_pchlan()
277 ew32(CTRL_EXT, mac_reg); in e1000_init_phy_workarounds_pchlan()
299 ew32(FEXTNVM3, mac_reg); in e1000_init_phy_workarounds_pchlan()
307 ew32(CTRL_EXT, mac_reg); in e1000_init_phy_workarounds_pchlan()
314 ew32(CTRL, mac_reg); in e1000_init_phy_workarounds_pchlan()
318 ew32(CTRL, mac_reg); in e1000_init_phy_workarounds_pchlan()
825 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); in e1000_k1_workaround_lpt_lp()
835 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); in e1000_k1_workaround_lpt_lp()
924 ew32(LTRV, reg); in e1000_platform_pm_pch_lpt()
977 ew32(TIPG, reg); in e1000_check_for_copper_link_ich8lan()
[all …]
Dnetdev.c611 ew32(RCTL, rctl & ~E1000_RCTL_EN); in e1000e_update_rdt_wa()
627 ew32(TCTL, tctl & ~E1000_TCTL_EN); in e1000e_update_tdt_wa()
1090 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); in e1000_print_hw_hang()
1096 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); in e1000_print_hw_hang()
1754 ew32(RCTL, rctl & ~E1000_RCTL_EN); in e1000_intr_msi()
1834 ew32(RCTL, rctl & ~E1000_RCTL_EN); in e1000_intr()
1879 ew32(IMS, E1000_IMS_OTHER); in e1000_msix_other()
1884 ew32(ICS, (icr & adapter->eiac_mask)); in e1000_msix_other()
1897 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER); in e1000_msix_other()
1914 ew32(ICS, tx_ring->ims_val); in e1000_intr_msix_tx()
[all …]
Dethtool.c830 ew32(STATUS, toggle); in e1000_reg_test()
839 ew32(STATUS, before); in e1000_reg_test()
979 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test()
1010 ew32(IMC, mask); in e1000_intr_test()
1011 ew32(ICS, mask); in e1000_intr_test()
1028 ew32(IMS, mask); in e1000_intr_test()
1029 ew32(ICS, mask); in e1000_intr_test()
1046 ew32(IMC, ~mask & 0x00007FFF); in e1000_intr_test()
1047 ew32(ICS, ~mask & 0x00007FFF); in e1000_intr_test()
1059 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test()
[all …]
Dphy.c161 ew32(MDIC, mdic); in e1000e_read_phy_reg_mdic()
225 ew32(MDIC, mdic); in e1000e_write_phy_reg_mdic()
492 ew32(KMRNCTRLSTA, kmrnctrlsta); in __e1000_read_kmrn_reg()
565 ew32(KMRNCTRLSTA, kmrnctrlsta); in __e1000_write_kmrn_reg()
1487 ew32(CTRL, ctrl); in e1000e_phy_force_speed_duplex_setup()
2127 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); in e1000e_phy_hw_reset_generic()
2132 ew32(CTRL, ctrl); in e1000e_phy_hw_reset_generic()
Dptp.c78 ew32(TIMINCA, timinca); in e1000e_phc_adjfreq()
Dmanage.c304 ew32(HICR, hicr | E1000_HICR_C); in e1000e_mng_write_dhcp_info()
De1000.h616 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) macro
/drivers/net/ethernet/intel/e1000/
De1000_hw.c428 ew32(IMC, 0xffffffff); in e1000_reset_hw()
434 ew32(RCTL, 0); in e1000_reset_hw()
435 ew32(TCTL, E1000_TCTL_PSP); in e1000_reset_hw()
450 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); in e1000_reset_hw()
477 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); in e1000_reset_hw()
481 ew32(CTRL, (ctrl | E1000_CTRL_RST)); in e1000_reset_hw()
498 ew32(CTRL_EXT, ctrl_ext); in e1000_reset_hw()
522 ew32(MANC, manc); in e1000_reset_hw()
532 ew32(LEDCTL, led_ctrl); in e1000_reset_hw()
537 ew32(IMC, 0xffffffff); in e1000_reset_hw()
[all …]
De1000_ethtool.c755 ew32(STATUS, toggle); in e1000_reg_test()
764 ew32(STATUS, before); in e1000_reg_test()
874 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test()
892 ew32(IMC, mask); in e1000_intr_test()
893 ew32(ICS, mask); in e1000_intr_test()
910 ew32(IMS, mask); in e1000_intr_test()
911 ew32(ICS, mask); in e1000_intr_test()
928 ew32(IMC, ~mask & 0x00007FFF); in e1000_intr_test()
929 ew32(ICS, ~mask & 0x00007FFF); in e1000_intr_test()
941 ew32(IMC, 0xFFFFFFFF); in e1000_intr_test()
[all …]
De1000_main.c308 ew32(IMC, ~0); in e1000_irq_disable()
321 ew32(IMS, IMS_ENABLE_MASK); in e1000_irq_enable()
363 ew32(MANC, manc); in e1000_init_manageability()
377 ew32(MANC, manc); in e1000_release_manageability()
425 ew32(ICS, E1000_ICS_LSC); in e1000_up()
515 ew32(RCTL, rctl & ~E1000_RCTL_EN); in e1000_down()
523 ew32(TCTL, tctl); in e1000_down()
622 ew32(PBA, pba); in e1000_reset()
674 ew32(PBA, pba); in e1000_reset()
697 ew32(WUC, 0); in e1000_reset()
[all …]
De1000_osdep.h58 #define ew32(reg, value) \ macro
/drivers/net/ethernet/intel/igbvf/
Dnetdev.c884 ew32(EIMS, adapter->eims_other); in igbvf_msix_other()
909 ew32(EICS, tx_ring->eims_value); in igbvf_intr_msix_tx()
911 ew32(EIMS, tx_ring->eims_value); in igbvf_intr_msix_tx()
1012 ew32(IVAR_MISC, tmp); in igbvf_configure_msix()
1172 ew32(EIMC, ~0); in igbvf_irq_disable()
1175 ew32(EIAC, 0); in igbvf_irq_disable()
1185 ew32(EIAC, adapter->eims_enable_mask); in igbvf_irq_enable()
1186 ew32(EIAM, adapter->eims_enable_mask); in igbvf_irq_enable()
1187 ew32(EIMS, adapter->eims_enable_mask); in igbvf_irq_enable()
1212 ew32(EIMS, adapter->rx_ring->eims_value); in igbvf_poll()
[all …]
Dmbx.c240 ew32(V2PMAILBOX(0), E1000_V2PMAILBOX_VFU); in e1000_obtain_mbx_lock_vf()
279 ew32(V2PMAILBOX(0), E1000_V2PMAILBOX_REQ); in e1000_write_mbx_vf()
308 ew32(V2PMAILBOX(0), E1000_V2PMAILBOX_ACK); in e1000_read_mbx_vf()
Dregs.h101 #define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg) macro
Dvf.c135 ew32(CTRL, ctrl | E1000_CTRL_RST); in e1000_reset_hw_vf()