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Searched refs:lobj (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
Devergreen_cs.c1165 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1196 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); in evergreen_cs_check_reg()
1197 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); in evergreen_cs_check_reg()
1198 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_check_reg()
1201 evergreen_tiling_fields(reloc->lobj.tiling_flags, in evergreen_cs_check_reg()
1237 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1249 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1261 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1273 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1297 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
[all …]
Dr600_cs.c1029 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1070 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1072 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset; in r600_cs_check_reg()
1091 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1128 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1131 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1200 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1231 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1267 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1270 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset; in r600_cs_check_reg()
[all …]
Dr200.c188 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
201 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
218 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
220 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
225 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
227 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
271 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
290 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
292 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
365 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
Dradeon_object.c341 void radeon_bo_list_add_object(struct radeon_bo_list *lobj, in radeon_bo_list_add_object() argument
344 if (lobj->written) { in radeon_bo_list_add_object()
345 list_add(&lobj->tv.head, head); in radeon_bo_list_add_object()
347 list_add_tail(&lobj->tv.head, head); in radeon_bo_list_add_object()
353 struct radeon_bo_list *lobj; in radeon_bo_list_validate() local
362 list_for_each_entry(lobj, head, tv.head) { in radeon_bo_list_validate()
363 bo = lobj->bo; in radeon_bo_list_validate()
365 domain = lobj->domain; in radeon_bo_list_validate()
374 if (r != -ERESTARTSYS && domain != lobj->alt_domain) { in radeon_bo_list_validate()
375 domain = lobj->alt_domain; in radeon_bo_list_validate()
[all …]
Dradeon_cs.c80 p->relocs[i].lobj.bo = p->relocs[i].robj; in radeon_cs_parser_relocs()
81 p->relocs[i].lobj.written = !!r->write_domain; in radeon_cs_parser_relocs()
87 p->relocs[i].lobj.domain = in radeon_cs_parser_relocs()
90 p->relocs[i].lobj.alt_domain = in radeon_cs_parser_relocs()
97 p->relocs[i].lobj.domain = domain; in radeon_cs_parser_relocs()
100 p->relocs[i].lobj.alt_domain = domain; in radeon_cs_parser_relocs()
103 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; in radeon_cs_parser_relocs()
106 radeon_bo_list_add_object(&p->relocs[i].lobj, in radeon_cs_parser_relocs()
396 struct radeon_bo_list *lobj; in radeon_bo_vm_update_pte() local
404 list_for_each_entry(lobj, &parser->validated, tv.head) { in radeon_bo_vm_update_pte()
[all …]
Dr300.c643 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()
656 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()
685 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); in r300_packet0_check()
687 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
689 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
691 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
694 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()
756 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
758 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
760 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
[all …]
Dr100.c1257 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); in r100_reloc_pitch_offset()
1260 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1262 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1308 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); in r100_packet3_load_vbpntr()
1320 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); in r100_packet3_load_vbpntr()
1334 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); in r100_packet3_load_vbpntr()
1577 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r100_packet0_check()
1590 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r100_packet0_check()
1604 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1606 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
[all …]
Dradeon_object.h129 extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
Dradeon_uvd.c416 start = reloc->lobj.gpu_offset; in radeon_uvd_cs_reloc()
Dradeon.h841 struct radeon_bo_list lobj; member