Home
last modified time | relevance | path

Searched refs:reg_idx (Results 1 – 14 of 14) sorted by relevance

/drivers/net/ethernet/intel/ixgbe/
Dixgbe_lib.c48 u16 reg_idx; in ixgbe_cache_ring_dcb_sriov() local
60 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
61 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
63 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
64 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
65 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
68 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
69 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
71 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
72 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
[all …]
Dixgbe_main.c797 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); in ixgbe_get_tx_pending()
798 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); in ixgbe_get_tx_pending()
972 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), in ixgbe_clean_tx_irq()
973 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), in ixgbe_clean_tx_irq()
1023 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1027 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1053 u8 reg_idx = rx_ring->reg_idx; in ixgbe_update_rx_dca() local
1073 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); in ixgbe_update_rx_dca()
2026 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbe_configure_msix()
2029 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbe_configure_msix()
[all …]
Dixgbe_ethtool.c1527 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); in ixgbe_free_desc_rings()
1529 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); in ixgbe_free_desc_rings()
1561 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; in ixgbe_setup_desc_rings()
1585 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; in ixgbe_setup_desc_rings()
2554 adapter->rx_ring[input->action]->reg_idx); in ixgbe_add_ethtool_fdir_entry()
Dixgbe_fcoe.c639 fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx; in ixgbe_configure_fcoe()
653 fcoe_q = adapter->rx_ring[fcoe->offset]->reg_idx; in ixgbe_configure_fcoe()
Dixgbe_sriov.c1155 unsigned int reg_idx = (vf * queues_per_pool) + queue; in ixgbe_set_vf_rate_limit() local
1157 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, reg_idx); in ixgbe_set_vf_rate_limit()
Dixgbe.h243 u8 reg_idx; /* holds the special value that gets member
/drivers/sh/intc/
Dhandle.c41 unsigned int *reg_idx, in _intc_mask_data() argument
48 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) { in _intc_mask_data()
49 mr = desc->hw.mask_regs + *reg_idx; in _intc_mask_data()
82 (*reg_idx)++; in _intc_mask_data()
109 unsigned int *reg_idx, in _intc_prio_data() argument
116 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) { in _intc_prio_data()
117 pr = desc->hw.prio_regs + *reg_idx; in _intc_prio_data()
151 (*reg_idx)++; in _intc_prio_data()
/drivers/hwmon/
Dw83791d.c787 u8 reg_idx = 0; in store_pwmenable() local
800 reg_idx = 0; in store_pwmenable()
805 reg_idx = 0; in store_pwmenable()
810 reg_idx = 1; in store_pwmenable()
816 reg_cfg_tmp = w83791d_read(client, W83791D_REG_FAN_CFG[reg_idx]); in store_pwmenable()
820 w83791d_write(client, W83791D_REG_FAN_CFG[reg_idx], reg_cfg_tmp); in store_pwmenable()
894 u8 reg_idx = 0; in store_temp_tolerance() local
903 reg_idx = 0; in store_temp_tolerance()
908 reg_idx = 0; in store_temp_tolerance()
913 reg_idx = 1; in store_temp_tolerance()
[all …]
/drivers/net/ethernet/intel/ixgbevf/
Dixgbevf_main.c112 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rx_ring->reg_idx), val); in ixgbevf_release_rx_desc()
623 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
626 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1070 j = ring->reg_idx; in ixgbevf_configure_tx()
1168 j = adapter->rx_ring[i].reg_idx; in ixgbevf_configure_rx()
1335 int j = adapter->rx_ring[rxr].reg_idx; in ixgbevf_rx_desc_queue_enable()
1420 j = adapter->tx_ring[i].reg_idx; in ixgbevf_up_complete()
1428 j = adapter->tx_ring[i].reg_idx; in ixgbevf_up_complete()
1435 j = adapter->rx_ring[i].reg_idx; in ixgbevf_up_complete()
1492 adapter->tx_ring[0].reg_idx = def_q; in ixgbevf_reset_queues()
[all …]
Dixgbevf.h83 u16 reg_idx; /* holds the special value that gets the hardware register member
/drivers/net/ethernet/intel/igb/
Digb_main.c734 adapter->rx_ring[i]->reg_idx = rbase_offset + in igb_cache_ring_register()
745 adapter->rx_ring[i]->reg_idx = rbase_offset + i; in igb_cache_ring_register()
747 adapter->tx_ring[j]->reg_idx = rbase_offset + j; in igb_cache_ring_register()
788 rx_queue = q_vector->rx.ring->reg_idx; in igb_assign_vector()
790 tx_queue = q_vector->tx.ring->reg_idx; in igb_assign_vector()
2984 int reg_idx = ring->reg_idx; in igb_configure_tx_ring() local
2987 wr32(E1000_TXDCTL(reg_idx), 0); in igb_configure_tx_ring()
2991 wr32(E1000_TDLEN(reg_idx), in igb_configure_tx_ring()
2993 wr32(E1000_TDBAL(reg_idx), in igb_configure_tx_ring()
2995 wr32(E1000_TDBAH(reg_idx), tdba >> 32); in igb_configure_tx_ring()
[all …]
Digb.h251 u8 reg_idx; /* physical index of the ring */ member
Digb_ethtool.c1531 tx_ring->reg_idx = adapter->vfs_allocated_count; in igb_setup_desc_rings()
1545 rx_ring->reg_idx = adapter->vfs_allocated_count; in igb_setup_desc_rings()
/drivers/media/radio/wl128x/
Dfmdrv_common.c639 u8 reg_idx = fmdev->rx.region.fm_band; in fm_rx_update_af_cache() local
653 if (reg_idx == FM_BAND_EUROPE_US && af > FM_RDS_MAX_AF) in fm_rx_update_af_cache()
655 if (reg_idx == FM_BAND_JAPAN && af > FM_RDS_MAX_AF_JAPAN) in fm_rx_update_af_cache()