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Searched refs:regval (Results 1 – 25 of 110) sorted by relevance

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/drivers/media/pci/cx23885/
Dcx23885-417.c288 u32 regval; in cx23885_mc417_init() local
293 regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) | in cx23885_mc417_init()
296 cx_write(MC417_CTL, regval); in cx23885_mc417_init()
299 regval = MC417_MIRDY; in cx23885_mc417_init()
300 cx_write(MC417_OEN, regval); in cx23885_mc417_init()
303 regval = MC417_MIWR | MC417_MIRD | MC417_MICS; in cx23885_mc417_init()
304 cx_write(MC417_RWD, regval); in cx23885_mc417_init()
324 u32 regval; in mc417_register_write() local
332 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 | in mc417_register_write()
334 cx_write(MC417_RWD, regval); in mc417_register_write()
[all …]
/drivers/rapidio/switches/
Dtsi57x.c123 u32 regval; in tsi57x_set_domain() local
131 TSI578_SP_MODE_GLBL, &regval); in tsi57x_set_domain()
133 regval & ~TSI578_SP_MODE_LUT_512); in tsi57x_set_domain()
145 u32 regval; in tsi57x_get_domain() local
151 TSI578_GLBL_ROUTE_BASE, &regval); in tsi57x_get_domain()
153 *sw_domain = (u8)(regval >> 24); in tsi57x_get_domain()
161 u32 regval; in tsi57x_em_init() local
170 TSI578_SP_MODE(portnum), &regval); in tsi57x_em_init()
173 regval & ~TSI578_SP_MODE_PW_DIS); in tsi57x_em_init()
179 &regval); in tsi57x_em_init()
[all …]
Didt_gen2.c200 u32 regval; in idtg2_get_domain() local
206 IDT_RIO_DOMAIN, &regval); in idtg2_get_domain()
208 *sw_domain = (u8)(regval & 0xff); in idtg2_get_domain()
216 u32 regval; in idtg2_em_init() local
241 rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval); in idtg2_em_init()
243 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); in idtg2_em_init()
259 rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval); in idtg2_em_init()
261 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | in idtg2_em_init()
281 rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval); in idtg2_em_init()
283 regval | IDT_LANE_CTRL_GENPW); in idtg2_em_init()
[all …]
/drivers/regulator/
Dab3100.c163 u8 regval; in ab3100_enable_regulator() local
166 &regval); in ab3100_enable_regulator()
174 if (regval & AB3100_REG_ON_MASK) in ab3100_enable_regulator()
177 regval |= AB3100_REG_ON_MASK; in ab3100_enable_regulator()
180 regval); in ab3100_enable_regulator()
194 u8 regval; in ab3100_disable_regulator() local
212 &regval); in ab3100_disable_regulator()
218 regval &= ~AB3100_REG_ON_MASK; in ab3100_disable_regulator()
220 regval); in ab3100_disable_regulator()
226 u8 regval; in ab3100_is_enabled_regulator() local
[all …]
Dab8500-ext.c61 u8 regval; in ab8500_ext_regulator_enable() local
73 regval = info->update_val_hp; in ab8500_ext_regulator_enable()
75 regval = info->update_val; in ab8500_ext_regulator_enable()
79 info->update_mask, regval); in ab8500_ext_regulator_enable()
89 info->update_mask, regval); in ab8500_ext_regulator_enable()
98 u8 regval; in ab8500_ext_regulator_disable() local
109 regval = info->update_val_hw; in ab8500_ext_regulator_disable()
111 regval = 0; in ab8500_ext_regulator_disable()
115 info->update_mask, regval); in ab8500_ext_regulator_disable()
125 info->update_mask, regval); in ab8500_ext_regulator_disable()
[all …]
Dlp8755.c97 unsigned int regval; in lp8755_buck_enable_time() local
101 ret = lp8755_read(pchip, 0x12 + id, &regval); in lp8755_buck_enable_time()
106 return (regval & 0xff) * 100; in lp8755_buck_enable_time()
155 unsigned int regval; in lp8755_buck_get_mode() local
159 ret = lp8755_read(pchip, 0x06, &regval); in lp8755_buck_get_mode()
164 if (regval & (0x01 << id)) in lp8755_buck_get_mode()
167 ret = lp8755_read(pchip, 0x08 + id, &regval); in lp8755_buck_get_mode()
172 if (regval & 0x20) in lp8755_buck_get_mode()
186 unsigned int regval = 0x00; in lp8755_buck_set_ramp() local
193 regval = 0x07; in lp8755_buck_set_ramp()
[all …]
Dtps6105x-regulator.c63 u8 regval; in tps6105x_regulator_is_enabled() local
66 ret = tps6105x_get(tps6105x, TPS6105X_REG_0, &regval); in tps6105x_regulator_is_enabled()
69 regval &= TPS6105X_REG0_MODE_MASK; in tps6105x_regulator_is_enabled()
70 regval >>= TPS6105X_REG0_MODE_SHIFT; in tps6105x_regulator_is_enabled()
72 if (regval == TPS6105X_REG0_MODE_VOLTAGE) in tps6105x_regulator_is_enabled()
81 u8 regval; in tps6105x_regulator_get_voltage_sel() local
84 ret = tps6105x_get(tps6105x, TPS6105X_REG_0, &regval); in tps6105x_regulator_get_voltage_sel()
88 regval &= TPS6105X_REG0_VOLTAGE_MASK; in tps6105x_regulator_get_voltage_sel()
89 regval >>= TPS6105X_REG0_VOLTAGE_SHIFT; in tps6105x_regulator_get_voltage_sel()
90 return (int) regval; in tps6105x_regulator_get_voltage_sel()
/drivers/watchdog/
Dts72xx_wdt.c52 int regval; member
88 int regval; member
113 return ts72xx_wdt_map[i].regval; in timeout_to_regval()
126 static int regval_to_timeout(int regval) in regval_to_timeout() argument
131 if (ts72xx_wdt_map[i].regval == regval) in regval_to_timeout()
166 __raw_writeb((u8)wdt->regval, wdt->control_reg); in ts72xx_wdt_start()
184 int regval; in ts72xx_wdt_open() local
190 regval = timeout_to_regval(timeout); in ts72xx_wdt_open()
191 if (regval < 0) { in ts72xx_wdt_open()
207 wdt->regval = regval; in ts72xx_wdt_open()
[all …]
/drivers/i2c/busses/
Di2c-sirf.c104 u32 regval; in i2c_sirfsoc_queue_cmd() local
110 regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0); in i2c_sirfsoc_queue_cmd()
113 regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK; in i2c_sirfsoc_queue_cmd()
114 writel(regval, in i2c_sirfsoc_queue_cmd()
123 regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0); in i2c_sirfsoc_queue_cmd()
126 regval |= SIRFSOC_I2C_STOP; in i2c_sirfsoc_queue_cmd()
127 writel(regval, in i2c_sirfsoc_queue_cmd()
174 u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE; in i2c_sirfsoc_set_address() local
178 regval |= SIRFSOC_I2C_STOP; in i2c_sirfsoc_set_address()
180 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_set_address()
[all …]
/drivers/net/ethernet/intel/igb/
Digb_ptp.c473 u64 regval; in igb_ptp_tx_hwtstamp() local
475 regval = rd32(E1000_TXSTMPL); in igb_ptp_tx_hwtstamp()
476 regval |= (u64)rd32(E1000_TXSTMPH) << 32; in igb_ptp_tx_hwtstamp()
478 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); in igb_ptp_tx_hwtstamp()
498 __le64 *regval = (__le64 *)va; in igb_ptp_rx_pktstamp() local
505 le64_to_cpu(regval[1])); in igb_ptp_rx_pktstamp()
521 u64 regval; in igb_ptp_rx_rgtstamp() local
536 regval = rd32(E1000_RXSTMPL); in igb_ptp_rx_rgtstamp()
537 regval |= (u64)rd32(E1000_RXSTMPH) << 32; in igb_ptp_rx_rgtstamp()
539 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); in igb_ptp_rx_rgtstamp()
[all …]
/drivers/net/wireless/brcm80211/brcmfmac/
Dsdio_chip.h49 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) argument
50 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) argument
51 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) argument
52 #define SBSDIO_CLKAV(regval, alponly) \ argument
53 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
/drivers/video/
Dsvgalib.c25 u8 regval, bitval, bitnum; in svga_wcrt_multi() local
28 regval = vga_rcrt(regbase, regset->regnum); in svga_wcrt_multi()
32 regval = regval & ~bitval; in svga_wcrt_multi()
33 if (value & 1) regval = regval | bitval; in svga_wcrt_multi()
37 vga_wcrt(regbase, regset->regnum, regval); in svga_wcrt_multi()
45 u8 regval, bitval, bitnum; in svga_wseq_multi() local
48 regval = vga_rseq(regbase, regset->regnum); in svga_wseq_multi()
52 regval = regval & ~bitval; in svga_wseq_multi()
53 if (value & 1) regval = regval | bitval; in svga_wseq_multi()
57 vga_wseq(regbase, regset->regnum, regval); in svga_wseq_multi()
[all …]
/drivers/spi/
Dspi-sirf.c350 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL); in spi_sirfsoc_chipselect() local
351 regval |= SIRFSOC_SPI_CS_IO_OUT; in spi_sirfsoc_chipselect()
355 regval |= SIRFSOC_SPI_CS_IO_OUT; in spi_sirfsoc_chipselect()
357 regval &= ~SIRFSOC_SPI_CS_IO_OUT; in spi_sirfsoc_chipselect()
361 regval &= ~SIRFSOC_SPI_CS_IO_OUT; in spi_sirfsoc_chipselect()
363 regval |= SIRFSOC_SPI_CS_IO_OUT; in spi_sirfsoc_chipselect()
366 writel(regval, sspi->base + SIRFSOC_SPI_CTRL); in spi_sirfsoc_chipselect()
379 u32 regval; in spi_sirfsoc_setup_transfer() local
391 regval = (sspi->ctrl_freq / (2 * hz)) - 1; in spi_sirfsoc_setup_transfer()
393 if (regval > 0xFFFF || regval < 0) { in spi_sirfsoc_setup_transfer()
[all …]
/drivers/net/ethernet/intel/ixgbe/
Dixgbe_ptp.c479 u64 regval = 0, ns; in ixgbe_ptp_tx_hwtstamp() local
482 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); in ixgbe_ptp_tx_hwtstamp()
483 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32; in ixgbe_ptp_tx_hwtstamp()
486 ns = timecounter_cyc2time(&adapter->tc, regval); in ixgbe_ptp_tx_hwtstamp()
548 u64 regval = 0, ns; in __ixgbe_ptp_rx_hwtstamp() local
567 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); in __ixgbe_ptp_rx_hwtstamp()
568 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32; in __ixgbe_ptp_rx_hwtstamp()
572 ns = timecounter_cyc2time(&adapter->tc, regval); in __ixgbe_ptp_rx_hwtstamp()
611 u32 regval; in ixgbe_ptp_hwtstamp_ioctl() local
685 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); in ixgbe_ptp_hwtstamp_ioctl()
[all …]
/drivers/rapidio/
Drio.c565 u32 regval; in rio_set_port_lockout() local
569 &regval); in rio_set_port_lockout()
571 regval |= RIO_PORT_N_CTL_LOCKOUT; in rio_set_port_lockout()
573 regval &= ~RIO_PORT_N_CTL_LOCKOUT; in rio_set_port_lockout()
577 regval); in rio_set_port_lockout()
637 u32 regval; in rio_enable_rx_tx_port() local
651 &regval); in rio_enable_rx_tx_port()
654 ext_ftr_ptr + RIO_PORT_N_CTL_CSR(port_num), &regval) < 0) in rio_enable_rx_tx_port()
658 if (regval & RIO_PORT_N_CTL_P_TYP_SER) { in rio_enable_rx_tx_port()
660 regval = regval | RIO_PORT_N_CTL_EN_RX_SER in rio_enable_rx_tx_port()
[all …]
/drivers/mfd/
Dtwl4030-madc.c642 u8 regval; in twl4030_madc_set_current_generator() local
645 &regval, TWL4030_BCI_BCICTL1); in twl4030_madc_set_current_generator()
652 regval |= chan ? TWL4030_BCI_ITHEN : TWL4030_BCI_TYPEN; in twl4030_madc_set_current_generator()
654 regval &= chan ? ~TWL4030_BCI_ITHEN : ~TWL4030_BCI_TYPEN; in twl4030_madc_set_current_generator()
656 regval, TWL4030_BCI_BCICTL1); in twl4030_madc_set_current_generator()
674 u8 regval; in twl4030_madc_set_power() local
678 &regval, TWL4030_MADC_CTRL1); in twl4030_madc_set_power()
685 regval |= TWL4030_MADC_MADCON; in twl4030_madc_set_power()
687 regval &= ~TWL4030_MADC_MADCON; in twl4030_madc_set_power()
688 ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, regval, TWL4030_MADC_CTRL1); in twl4030_madc_set_power()
[all …]
Dtps6105x.c69 u8 regval; in tps6105x_mask_and_set() local
77 regval = ret; in tps6105x_mask_and_set()
78 regval = (~bitmask & regval) | (bitmask & bitvalues); in tps6105x_mask_and_set()
79 ret = i2c_smbus_write_byte_data(tps6105x->client, reg, regval); in tps6105x_mask_and_set()
92 u8 regval; in tps6105x_startup() local
94 ret = tps6105x_get(tps6105x, TPS6105X_REG_0, &regval); in tps6105x_startup()
97 switch (regval >> TPS6105X_REG0_MODE_SHIFT) { in tps6105x_startup()
/drivers/net/wireless/ath/ath9k/
Dar9003_phy.c1269 u32 regval; in ar9003_hw_antdiv_comb_conf_get() local
1271 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_get()
1272 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> in ar9003_hw_antdiv_comb_conf_get()
1274 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> in ar9003_hw_antdiv_comb_conf_get()
1276 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> in ar9003_hw_antdiv_comb_conf_get()
1297 u32 regval; in ar9003_hw_antdiv_comb_conf_set() local
1299 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_set()
1300 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | in ar9003_hw_antdiv_comb_conf_set()
1305 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) in ar9003_hw_antdiv_comb_conf_set()
1307 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) in ar9003_hw_antdiv_comb_conf_set()
[all …]
/drivers/hwmon/
Dasc7621.c250 u16 regval; in show_fan16() local
253 regval = (data->reg[param->msb[0]] << 8) | data->reg[param->lsb[0]]; in show_fan16()
257 (regval == 0 ? -1 : (regval) == in show_fan16()
258 0xffff ? 0 : 5400000 / regval)); in show_fan16()
311 u16 regval; in show_in10() local
315 regval = (data->reg[param->msb[0]] << 8) | (data->reg[param->lsb[0]]); in show_in10()
319 regval = (regval >> 6) * asc7621_in_scaling[nr] / (0xc0 << 2); in show_in10()
321 return sprintf(buf, "%u\n", regval); in show_in10()
418 u8 regval = data->reg[param->msb[0]]; in show_temp62() local
419 int temp = ((s8) (regval & 0xfc) * 1000) + ((regval & 0x03) * 250); in show_temp62()
[all …]
Dk10temp.c57 u32 regval; in show_temp() local
60 REG_REPORTED_TEMPERATURE, &regval); in show_temp()
61 return sprintf(buf, "%u\n", (regval >> 21) * 125); in show_temp()
75 u32 regval; in show_temp_crit() local
79 REG_HARDWARE_THERMAL_CONTROL, &regval); in show_temp_crit()
80 value = ((regval >> 16) & 0x7f) * 500 + 52000; in show_temp_crit()
82 value -= ((regval >> 24) & 0xf) * 500; in show_temp_crit()
Dltc4245.c178 const u8 regval = data->vregs[reg - 0x10]; in ltc4245_get_voltage() local
184 voltage = regval * 55; in ltc4245_get_voltage()
188 voltage = regval * 22; in ltc4245_get_voltage()
192 voltage = regval * 15; in ltc4245_get_voltage()
196 voltage = regval * -55; in ltc4245_get_voltage()
199 voltage = regval * 10; in ltc4245_get_voltage()
214 const u8 regval = data->vregs[reg - 0x10]; in ltc4245_get_current() local
235 voltage = regval * 250; /* voltage in uV */ in ltc4245_get_current()
239 voltage = regval * 125; /* voltage in uV */ in ltc4245_get_current()
243 voltage = regval * 125; /* voltage in uV */ in ltc4245_get_current()
[all …]
/drivers/net/phy/
Dmicrel.c58 int regval; in ksz_config_flags() local
61 regval = phy_read(phydev, MII_KSZPHY_CTRL); in ksz_config_flags()
62 regval |= KSZ8051_RMII_50MHZ_CLK; in ksz_config_flags()
63 return phy_write(phydev, MII_KSZPHY_CTRL, regval); in ksz_config_flags()
149 int regval; in ksz8873mll_read_status() local
152 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); in ksz8873mll_read_status()
154 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); in ksz8873mll_read_status()
156 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) in ksz8873mll_read_status()
161 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) in ksz8873mll_read_status()
/drivers/staging/iio/cdc/
Dad7152.c98 u8 regval) in ad7152_start_calib() argument
114 regval |= AD7152_CONF_CH1EN; in ad7152_start_calib()
116 regval |= AD7152_CONF_CH2EN; in ad7152_start_calib()
119 ret = i2c_smbus_write_byte_data(chip->client, AD7152_REG_CFG, regval); in ad7152_start_calib()
132 } while ((ret == regval) && timeout--); in ad7152_start_calib()
327 u8 regval = 0; in ad7152_read_raw() local
335 regval = chip->setup[chan->channel]; in ad7152_read_raw()
342 if (regval != chip->setup[chan->channel]) { in ad7152_read_raw()
351 regval = AD7152_CONF_CH1EN; in ad7152_read_raw()
353 regval = AD7152_CONF_CH2EN; in ad7152_read_raw()
[all …]
Dad7746.c283 u8 regval) in ad7746_start_calib() argument
298 regval |= chip->config; in ad7746_start_calib()
299 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval); in ad7746_start_calib()
312 } while ((ret == regval) && timeout--); in ad7746_start_calib()
567 u8 regval, reg; in ad7746_read_raw() local
584 regval = chip->config | AD7746_CONF_MODE_SINGLE_CONV; in ad7746_read_raw()
586 regval); in ad7746_read_raw()
700 unsigned char regval = 0; in ad7746_probe() local
729 regval |= AD7746_EXCSETUP_NEXCA; in ad7746_probe()
731 regval |= AD7746_EXCSETUP_EXCA; in ad7746_probe()
[all …]
/drivers/rtc/
Drtc-ab3100.c205 u8 regval; in ab3100_rtc_probe() local
210 AB3100_RTC, &regval); in ab3100_rtc_probe()
216 if ((regval & 0xFE) != RTC_SETTING) { in ab3100_rtc_probe()
218 regval); in ab3100_rtc_probe()
221 if ((regval & 1) == 0) { in ab3100_rtc_probe()
226 regval = 1 | RTC_SETTING; in ab3100_rtc_probe()
228 AB3100_RTC, regval); in ab3100_rtc_probe()

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