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Searched refs:sync_offset (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/host1x/
Ddev.c51 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_writel()
58 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_readl()
79 .sync_offset = 0x3000,
Ddev.h97 int sync_offset; member
/drivers/scsi/
Ddc395x.c290 u8 sync_offset; /* for reg. and nego.(low nibble) */ member
1282 dcb->sync_offset = 0; in reset_dev_param()
1415 dcb->sync_offset = 0; in build_sdtr()
1417 } else if (dcb->sync_offset == 0) in build_sdtr()
1418 dcb->sync_offset = SYNC_NEGO_OFFSET; in build_sdtr()
1424 *ptr++ = dcb->sync_offset; /* Transfer period (max. REQ/ACK dist) */ in build_sdtr()
1548 DC395x_write8(acb, TRM_S1040_SCSI_OFFSET, dcb->sync_offset); in start_scsi()
2690 DC395x_write8(acb, TRM_S1040_SCSI_OFFSET, dcb->sync_offset); in reprogram_regs()
2705 dcb->sync_offset = 0; in msgin_set_async()
2734 dcb->sync_offset = 0; in msgin_set_sync()
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Dmac53c94.h55 #define sync_offset flags macro
Dmac53c94.c137 writeb(0, &regs->sync_offset); in mac53c94_init()
169 writeb(0, &regs->sync_offset); in mac53c94_start()
Dqla1280.h472 uint8_t sync_offset:4; member
479 uint8_t sync_offset:5; member
Dqla1280.c1175 mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8); in qla1280_set_target_parameters()
1180 mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8); in qla1280_set_target_parameters()
2041 nv->bus[bus].target[target].flags.flags1x160.sync_offset = 0x0e; in qla1280_set_target_defaults()
2048 nv->bus[bus].target[target].flags.flags1x80.sync_offset = 12; in qla1280_set_target_defaults()
2128 mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8; in qla1280_config_target()
2130 mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8; in qla1280_config_target()
/drivers/scsi/sym53c8xx_2/
Dsym_nvram.h107 u_char sync_offset; member
/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_link.c4761 u32 sync_offset, media_types; in bnx2x_link_status_update() local
4782 sync_offset = params->shmem_base + in bnx2x_link_status_update()
4785 media_types = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
4799 sync_offset = params->shmem_base + in bnx2x_link_status_update()
4803 vars->aeu_int_mask = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
8047 u32 sync_offset = 0, phy_idx, media_types; in bnx2x_get_edc_mode() local
8137 sync_offset = params->shmem_base + in bnx2x_get_edc_mode()
8140 media_types = REG_RD(bp, sync_offset); in bnx2x_get_edc_mode()
8152 REG_WR(bp, sync_offset, media_types); in bnx2x_get_edc_mode()
12209 u32 phy_config_swapped, sync_offset, media_types; in bnx2x_phy_probe() local
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