1 /*
2 * Tegra host1x driver
3 *
4 * Copyright (c) 2010-2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include <linux/module.h>
20 #include <linux/list.h>
21 #include <linux/slab.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/clk.h>
25 #include <linux/io.h>
26
27 #define CREATE_TRACE_POINTS
28 #include <trace/events/host1x.h>
29
30 #include "dev.h"
31 #include "intr.h"
32 #include "channel.h"
33 #include "debug.h"
34 #include "hw/host1x01.h"
35 #include "host1x_client.h"
36
host1x_set_drm_data(struct device * dev,void * data)37 void host1x_set_drm_data(struct device *dev, void *data)
38 {
39 struct host1x *host1x = dev_get_drvdata(dev);
40 host1x->drm_data = data;
41 }
42
host1x_get_drm_data(struct device * dev)43 void *host1x_get_drm_data(struct device *dev)
44 {
45 struct host1x *host1x = dev_get_drvdata(dev);
46 return host1x->drm_data;
47 }
48
host1x_sync_writel(struct host1x * host1x,u32 v,u32 r)49 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
50 {
51 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
52
53 writel(v, sync_regs + r);
54 }
55
host1x_sync_readl(struct host1x * host1x,u32 r)56 u32 host1x_sync_readl(struct host1x *host1x, u32 r)
57 {
58 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
59
60 return readl(sync_regs + r);
61 }
62
host1x_ch_writel(struct host1x_channel * ch,u32 v,u32 r)63 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
64 {
65 writel(v, ch->regs + r);
66 }
67
host1x_ch_readl(struct host1x_channel * ch,u32 r)68 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
69 {
70 return readl(ch->regs + r);
71 }
72
73 static const struct host1x_info host1x01_info = {
74 .nb_channels = 8,
75 .nb_pts = 32,
76 .nb_mlocks = 16,
77 .nb_bases = 8,
78 .init = host1x01_init,
79 .sync_offset = 0x3000,
80 };
81
82 static struct of_device_id host1x_of_match[] = {
83 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
84 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
85 { },
86 };
87 MODULE_DEVICE_TABLE(of, host1x_of_match);
88
host1x_probe(struct platform_device * pdev)89 static int host1x_probe(struct platform_device *pdev)
90 {
91 const struct of_device_id *id;
92 struct host1x *host;
93 struct resource *regs;
94 int syncpt_irq;
95 int err;
96
97 id = of_match_device(host1x_of_match, &pdev->dev);
98 if (!id)
99 return -EINVAL;
100
101 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
102 if (!regs) {
103 dev_err(&pdev->dev, "failed to get registers\n");
104 return -ENXIO;
105 }
106
107 syncpt_irq = platform_get_irq(pdev, 0);
108 if (syncpt_irq < 0) {
109 dev_err(&pdev->dev, "failed to get IRQ\n");
110 return -ENXIO;
111 }
112
113 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
114 if (!host)
115 return -ENOMEM;
116
117 host->dev = &pdev->dev;
118 host->info = id->data;
119
120 /* set common host1x device data */
121 platform_set_drvdata(pdev, host);
122
123 host->regs = devm_ioremap_resource(&pdev->dev, regs);
124 if (IS_ERR(host->regs))
125 return PTR_ERR(host->regs);
126
127 if (host->info->init) {
128 err = host->info->init(host);
129 if (err)
130 return err;
131 }
132
133 host->clk = devm_clk_get(&pdev->dev, NULL);
134 if (IS_ERR(host->clk)) {
135 dev_err(&pdev->dev, "failed to get clock\n");
136 err = PTR_ERR(host->clk);
137 return err;
138 }
139
140 err = host1x_channel_list_init(host);
141 if (err) {
142 dev_err(&pdev->dev, "failed to initialize channel list\n");
143 return err;
144 }
145
146 err = clk_prepare_enable(host->clk);
147 if (err < 0) {
148 dev_err(&pdev->dev, "failed to enable clock\n");
149 return err;
150 }
151
152 err = host1x_syncpt_init(host);
153 if (err) {
154 dev_err(&pdev->dev, "failed to initialize syncpts\n");
155 return err;
156 }
157
158 err = host1x_intr_init(host, syncpt_irq);
159 if (err) {
160 dev_err(&pdev->dev, "failed to initialize interrupts\n");
161 goto fail_deinit_syncpt;
162 }
163
164 host1x_debug_init(host);
165
166 host1x_drm_alloc(pdev);
167
168 return 0;
169
170 fail_deinit_syncpt:
171 host1x_syncpt_deinit(host);
172 return err;
173 }
174
host1x_remove(struct platform_device * pdev)175 static int __exit host1x_remove(struct platform_device *pdev)
176 {
177 struct host1x *host = platform_get_drvdata(pdev);
178
179 host1x_intr_deinit(host);
180 host1x_syncpt_deinit(host);
181 clk_disable_unprepare(host->clk);
182
183 return 0;
184 }
185
186 static struct platform_driver tegra_host1x_driver = {
187 .probe = host1x_probe,
188 .remove = __exit_p(host1x_remove),
189 .driver = {
190 .owner = THIS_MODULE,
191 .name = "tegra-host1x",
192 .of_match_table = host1x_of_match,
193 },
194 };
195
tegra_host1x_init(void)196 static int __init tegra_host1x_init(void)
197 {
198 int err;
199
200 err = platform_driver_register(&tegra_host1x_driver);
201 if (err < 0)
202 return err;
203
204 #ifdef CONFIG_DRM_TEGRA
205 err = platform_driver_register(&tegra_dc_driver);
206 if (err < 0)
207 goto unregister_host1x;
208
209 err = platform_driver_register(&tegra_hdmi_driver);
210 if (err < 0)
211 goto unregister_dc;
212
213 err = platform_driver_register(&tegra_gr2d_driver);
214 if (err < 0)
215 goto unregister_hdmi;
216 #endif
217
218 return 0;
219
220 #ifdef CONFIG_DRM_TEGRA
221 unregister_hdmi:
222 platform_driver_unregister(&tegra_hdmi_driver);
223 unregister_dc:
224 platform_driver_unregister(&tegra_dc_driver);
225 unregister_host1x:
226 platform_driver_unregister(&tegra_host1x_driver);
227 return err;
228 #endif
229 }
230 module_init(tegra_host1x_init);
231
tegra_host1x_exit(void)232 static void __exit tegra_host1x_exit(void)
233 {
234 #ifdef CONFIG_DRM_TEGRA
235 platform_driver_unregister(&tegra_gr2d_driver);
236 platform_driver_unregister(&tegra_hdmi_driver);
237 platform_driver_unregister(&tegra_dc_driver);
238 #endif
239 platform_driver_unregister(&tegra_host1x_driver);
240 }
241 module_exit(tegra_host1x_exit);
242
243 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
244 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
245 MODULE_DESCRIPTION("Host1x driver for Tegra products");
246 MODULE_LICENSE("GPL");
247