| /drivers/gpu/drm/radeon/ |
| D | rs600d.h | 33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument
42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument
43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument
45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument
46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument
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| D | r100d.h | 69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
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| D | r420d.h | 32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
39 #define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
40 #define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
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| D | rs690d.h | 34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
43 #define S_00007C_MC_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
44 #define G_00007C_MC_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
47 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
48 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
51 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
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| D | r300d.h | 70 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
71 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
73 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
74 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
77 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) argument
78 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) argument
80 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) argument
81 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) argument
84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
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| D | rs400d.h | 33 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
34 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
36 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
37 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
40 #define S_00015C_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
41 #define G_00015C_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
43 #define S_00015C_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
44 #define G_00015C_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
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| D | r520d.h | 33 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
34 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
37 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
38 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) argument
41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
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| D | rv250d.h | 32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) argument
33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) argument
35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) argument
36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) argument
38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) argument
39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) argument
41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) argument
42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) argument
44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) argument
45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) argument
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| D | rv515d.h | 210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
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| D | r600d.h | 67 #define BACKEND_DISABLE(x) ((x) << 16) argument
70 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) argument
71 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) argument
90 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) argument
91 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) argument
93 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) argument
94 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) argument
104 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) argument
105 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) argument
107 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) argument
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| D | rv770d.h | 47 # define UPLL_REF_DIV(x) ((x) << 16) argument
52 # define UPLL_SW_HILEN(x) ((x) << 0) argument
53 # define UPLL_SW_LOLEN(x) ((x) << 4) argument
54 # define UPLL_SW_HILEN2(x) ((x) << 8) argument
55 # define UPLL_SW_LOLEN2(x) ((x) << 12) argument
57 # define VCLK_SRC_SEL(x) ((x) << 20) argument
59 # define DCLK_SRC_SEL(x) ((x) << 25) argument
62 # define UPLL_FB_DIV(x) ((x) << 0) argument
78 #define BACKEND_DISABLE(x) ((x) << 16) argument
95 #define STQ_SPLIT(x) ((x) << 0) argument
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| D | evergreend.h | 67 # define UPLL_PDIV_A(x) ((x) << 0) argument
69 # define UPLL_PDIV_B(x) ((x) << 8) argument
71 # define VCLK_SRC_SEL(x) ((x) << 20) argument
73 # define DCLK_SRC_SEL(x) ((x) << 25) argument
76 # define UPLL_FB_DIV(x) ((x) << 0) argument
94 #define INSTANCE_INDEX(x) ((x) << 0) argument
95 #define SE_INDEX(x) ((x) << 16) argument
102 #define BACKEND_DISABLE(x) ((x) << 16) argument
104 #define NUM_PIPES(x) ((x) << 0) argument
106 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) argument
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| D | rv350d.h | 33 #define S_00000D_FORCE_VAP(x) (((x) & 0x1) << 21) argument
34 #define G_00000D_FORCE_VAP(x) (((x) >> 21) & 0x1) argument
36 #define S_00000D_FORCE_SR(x) (((x) & 0x1) << 25) argument
37 #define G_00000D_FORCE_SR(x) (((x) >> 25) & 0x1) argument
39 #define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26) argument
40 #define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1) argument
42 #define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27) argument
43 #define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1) argument
45 #define S_00000D_FORCE_US(x) (((x) & 0x1) << 28) argument
46 #define G_00000D_FORCE_US(x) (((x) >> 28) & 0x1) argument
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| /drivers/net/ethernet/chelsio/cxgb/ |
| D | regs.h | 46 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) argument
50 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) argument
54 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) argument
58 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) argument
62 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) argument
66 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) argument
71 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) argument
72 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) argument
75 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) argument
79 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) argument
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| D | fpga_defs.h | 55 #define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV) argument
56 #define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV) argument
60 #define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT) argument
61 #define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT) argument
66 #define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL) argument
70 #define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE) argument
74 #define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE) argument
78 #define V_MI0_BUSY(x) ((x) << S_MI0_BUSY) argument
82 #define V_MI0_MDIO(x) ((x) << S_MI0_MDIO) argument
89 #define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR) argument
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| /drivers/net/ethernet/chelsio/cxgb3/ |
| D | sge_defs.h | 10 #define V_EC_CREDITS(x) ((x) << S_EC_CREDITS) argument
11 #define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS) argument
14 #define V_EC_GTS(x) ((x) << S_EC_GTS) argument
19 #define V_EC_INDEX(x) ((x) << S_EC_INDEX) argument
20 #define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX) argument
24 #define V_EC_SIZE(x) ((x) << S_EC_SIZE) argument
25 #define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE) argument
29 #define V_EC_BASE_LO(x) ((x) << S_EC_BASE_LO) argument
30 #define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO) argument
34 #define V_EC_BASE_HI(x) ((x) << S_EC_BASE_HI) argument
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| D | regs.h | 4 #define V_CONGMODE(x) ((x) << S_CONGMODE) argument
8 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) argument
12 #define V_FATLPERREN(x) ((x) << S_FATLPERREN) argument
16 #define V_DROPPKT(x) ((x) << S_DROPPKT) argument
20 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) argument
25 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) argument
29 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) argument
32 #define V_FLMODE(x) ((x) << S_FLMODE) argument
37 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) argument
40 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) argument
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| /drivers/infiniband/hw/cxgb3/ |
| D | tcb.h | 38 #define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) argument
43 #define V_TCB_TIMER(x) ((x) << S_TCB_TIMER) argument
48 #define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER) argument
53 #define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG) argument
58 #define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) argument
63 #define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) argument
68 #define V_TCB_TOS(x) ((x) << S_TCB_TOS) argument
73 #define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) argument
78 #define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) argument
83 #define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) argument
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| /drivers/video/exynos/ |
| D | exynos_mipi_dsi_regs.h | 48 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) argument
57 #define DSIM_LPDR_TOUT_SHIFT(x) ((x) << 0) argument
58 #define DSIM_BTA_TOUT_SHIFT(x) ((x) << 16) argument
61 #define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << 19) argument
62 #define DSIM_BYTE_CLKEN_SHIFT(x) ((x) << 24) argument
63 #define DSIM_BYTE_CLK_SRC_SHIFT(x) ((x) << 25) argument
64 #define DSIM_PLL_BYPASS_SHIFT(x) ((x) << 27) argument
65 #define DSIM_ESC_CLKEN_SHIFT(x) ((x) << 28) argument
66 #define DSIM_TX_REQUEST_HSCLK_SHIFT(x) ((x) << 31) argument
69 #define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0) argument
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| /drivers/scsi/qla4xxx/ |
| D | ql4_dbg.h | 20 #define DEBUG(x) do {x;} while (0); argument
22 #define DEBUG(x) do {} while (0); argument
26 #define DEBUG2(x) do {if(ql4xextended_error_logging == 2) x;} while (0); argument
27 #define DEBUG2_3(x) do {x;} while (0); argument
29 #define DEBUG2(x) do {} while (0); argument
33 #define DEBUG3(x) do {if(ql4xextended_error_logging == 3) x;} while (0); argument
35 #define DEBUG3(x) do {} while (0); argument
37 #define DEBUG2_3(x) do {} while (0); argument
41 #define DEBUG4(x) do {x;} while (0); argument
43 #define DEBUG4(x) do {} while (0); argument
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| /drivers/staging/tidspbridge/dynload/ |
| D | params.h | 130 #define TADDR_TO_HOST(x) (x) argument
132 #define HOST_TO_TADDR(x) (x) argument
134 #define TADDR_TO_HOST(x) ((x) >> (LOG_BITS_PER_AU-LOG_TARGET_AU_BITS)) argument
135 #define HOST_TO_TADDR(x) ((x) << (LOG_BITS_PER_AU-LOG_TARGET_AU_BITS)) argument
137 #define TADDR_TO_HOST(x) ((x) << (LOG_TARGET_AU_BITS-LOG_BITS_PER_AU)) argument
138 #define HOST_TO_TADDR(x) ((x) >> (LOG_TARGET_AU_BITS-LOG_BITS_PER_AU)) argument
143 #define TDATA_TO_HOST(x) (x) argument
145 #define HOST_TO_TDATA(x) (x) argument
147 #define HOST_TO_TDATA_ROUND(x) (x) argument
149 #define BYTE_TO_HOST_TDATA_ROUND(x) BYTE_TO_HOST_ROUND(x) argument
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| /drivers/edac/ |
| D | mce_amd.h | 8 #define EC(x) ((x) & 0xffff) argument
9 #define XEC(x, mask) (((x) >> 16) & mask) argument
11 #define LOW_SYNDROME(x) (((x) >> 15) & 0xff) argument
12 #define HIGH_SYNDROME(x) (((x) >> 24) & 0xff) argument
14 #define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010) argument
15 #define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100) argument
16 #define BUS_ERROR(x) (((x) & 0xF800) == 0x0800) argument
17 #define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400) argument
19 #define TT(x) (((x) >> 2) & 0x3) argument
20 #define TT_MSG(x) tt_msgs[TT(x)] argument
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| /drivers/net/ethernet/intel/ixgbevf/ |
| D | regs.h | 42 #define IXGBE_VTEITR(x) (0x00820 + (4 * (x))) argument
43 #define IXGBE_VTIVAR(x) (0x00120 + (4 * (x))) argument
45 #define IXGBE_VTRSCINT(x) (0x00180 + (4 * (x))) argument
46 #define IXGBE_VFRDBAL(x) (0x01000 + (0x40 * (x))) argument
47 #define IXGBE_VFRDBAH(x) (0x01004 + (0x40 * (x))) argument
48 #define IXGBE_VFRDLEN(x) (0x01008 + (0x40 * (x))) argument
49 #define IXGBE_VFRDH(x) (0x01010 + (0x40 * (x))) argument
50 #define IXGBE_VFRDT(x) (0x01018 + (0x40 * (x))) argument
51 #define IXGBE_VFRXDCTL(x) (0x01028 + (0x40 * (x))) argument
52 #define IXGBE_VFSRRCTL(x) (0x01014 + (0x40 * (x))) argument
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| /drivers/net/ethernet/ibm/emac/ |
| D | debug.h | 44 # define emac_dbg_register(x) do { } while(0) argument
45 # define emac_dbg_unregister(x) do { } while(0) argument
46 # define mal_dbg_register(x) do { } while(0) argument
47 # define mal_dbg_unregister(x) do { } while(0) argument
60 # define DBG(d,f,x...) EMAC_DBG(d, emac, f, ##x) argument
61 # define MAL_DBG(d,f,x...) EMAC_DBG(d, mal, f, ##x) argument
62 # define ZMII_DBG(d,f,x...) EMAC_DBG(d, zmii, f, ##x) argument
63 # define RGMII_DBG(d,f,x...) EMAC_DBG(d, rgmii, f, ##x) argument
66 # define DBG(f,x...) ((void)0) argument
67 # define MAL_DBG(d,f,x...) ((void)0) argument
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| /drivers/infiniband/hw/cxgb4/ |
| D | t4fw_ri_api.h | 167 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) argument
168 #define G_FW_RI_TPTE_VALID(x) \ argument
174 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) argument
175 #define G_FW_RI_TPTE_STAGKEY(x) \ argument
180 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) argument
181 #define G_FW_RI_TPTE_STAGSTATE(x) \ argument
187 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) argument
188 #define G_FW_RI_TPTE_STAGTYPE(x) \ argument
193 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) argument
194 #define G_FW_RI_TPTE_PDID(x) \ argument
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