1Linux IOMMU Support 2=================== 3 4The architecture spec can be obtained from the below location. 5 6http://www.intel.com/technology/virtualization/ 7 8This guide gives a quick cheat sheet for some basic understanding. 9 10Some Keywords 11 12DMAR - DMA remapping 13DRHD - DMA Engine Reporting Structure 14RMRR - Reserved memory Region Reporting Structure 15ZLR - Zero length reads from PCI devices 16IOVA - IO Virtual address. 17 18Basic stuff 19----------- 20 21ACPI enumerates and lists the different DMA engines in the platform, and 22device scope relationships between PCI devices and which DMA engine controls 23them. 24 25What is RMRR? 26------------- 27 28There are some devices the BIOS controls, for e.g USB devices to perform 29PS2 emulation. The regions of memory used for these devices are marked 30reserved in the e820 map. When we turn on DMA translation, DMA to those 31regions will fail. Hence BIOS uses RMRR to specify these regions along with 32devices that need to access these regions. OS is expected to setup 33unity mappings for these regions for these devices to access these regions. 34 35How is IOVA generated? 36--------------------- 37 38Well behaved drivers call pci_map_*() calls before sending command to device 39that needs to perform DMA. Once DMA is completed and mapping is no longer 40required, device performs a pci_unmap_*() calls to unmap the region. 41 42The Intel IOMMU driver allocates a virtual address per domain. Each PCIE 43device has its own domain (hence protection). Devices under p2p bridges 44share the virtual address with all devices under the p2p bridge due to 45transaction id aliasing for p2p bridges. 46 47IOVA generation is pretty generic. We used the same technique as vmalloc() 48but these are not global address spaces, but separate for each domain. 49Different DMA engines may support different number of domains. 50 51We also allocate guard pages with each mapping, so we can attempt to catch 52any overflow that might happen. 53 54 55Graphics Problems? 56------------------ 57If you encounter issues with graphics devices, you can try adding 58option intel_iommu=igfx_off to turn off the integrated graphics engine. 59If this fixes anything, please ensure you file a bug reporting the problem. 60 61Some exceptions to IOVA 62----------------------- 63Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff). 64The same is true for peer to peer transactions. Hence we reserve the 65address from PCI MMIO ranges so they are not allocated for IOVA addresses. 66 67 68Fault reporting 69--------------- 70When errors are reported, the DMA engine signals via an interrupt. The fault 71reason and device that caused it with fault reason is printed on console. 72 73See below for sample. 74 75 76Boot Message Sample 77------------------- 78 79Something like this gets printed indicating presence of DMAR tables 80in ACPI. 81 82ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0 83 84When DMAR is being processed and initialized by ACPI, prints DMAR locations 85and any RMRR's processed. 86 87ACPI DMAR:Host address width 36 88ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000 89ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000 90ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000 91ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff 92ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff 93 94When DMAR is enabled for use, you will notice.. 95 96PCI-DMA: Using DMAR IOMMU 97 98Fault reporting 99--------------- 100 101DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000 102DMAR:[fault reason 05] PTE Write access is not set 103DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000 104DMAR:[fault reason 05] PTE Write access is not set 105 106TBD 107---- 108 109- For compatibility testing, could use unity map domain for all devices, just 110 provide a 1-1 for all useful memory under a single domain for all devices. 111- API for paravirt ops for abstracting functionality for VMM folks. 112