1/* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12/include/ "skeleton.dtsi" 13 14/ { 15 interrupt-parent = <&icoll>; 16 17 aliases { 18 gpio0 = &gpio0; 19 gpio1 = &gpio1; 20 gpio2 = &gpio2; 21 gpio3 = &gpio3; 22 gpio4 = &gpio4; 23 saif0 = &saif0; 24 saif1 = &saif1; 25 serial0 = &auart0; 26 serial1 = &auart1; 27 serial2 = &auart2; 28 serial3 = &auart3; 29 serial4 = &auart4; 30 ethernet0 = &mac0; 31 ethernet1 = &mac1; 32 }; 33 34 cpus { 35 cpu@0 { 36 compatible = "arm,arm926ejs"; 37 }; 38 }; 39 40 apb@80000000 { 41 compatible = "simple-bus"; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 reg = <0x80000000 0x80000>; 45 ranges; 46 47 apbh@80000000 { 48 compatible = "simple-bus"; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 reg = <0x80000000 0x3c900>; 52 ranges; 53 54 icoll: interrupt-controller@80000000 { 55 compatible = "fsl,imx28-icoll", "fsl,icoll"; 56 interrupt-controller; 57 #interrupt-cells = <1>; 58 reg = <0x80000000 0x2000>; 59 }; 60 61 hsadc@80002000 { 62 reg = <0x80002000 0x2000>; 63 interrupts = <13 87>; 64 dmas = <&dma_apbh 12>; 65 dma-names = "rx"; 66 status = "disabled"; 67 }; 68 69 dma_apbh: dma-apbh@80004000 { 70 compatible = "fsl,imx28-dma-apbh"; 71 reg = <0x80004000 0x2000>; 72 interrupts = <82 83 84 85 73 88 88 88 88 74 88 88 88 88 75 87 86 0 0>; 76 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", 77 "gpmi0", "gmpi1", "gpmi2", "gmpi3", 78 "gpmi4", "gmpi5", "gpmi6", "gmpi7", 79 "hsadc", "lcdif", "empty", "empty"; 80 #dma-cells = <1>; 81 dma-channels = <16>; 82 clocks = <&clks 25>; 83 }; 84 85 perfmon@80006000 { 86 reg = <0x80006000 0x800>; 87 interrupts = <27>; 88 status = "disabled"; 89 }; 90 91 gpmi-nand@8000c000 { 92 compatible = "fsl,imx28-gpmi-nand"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; 96 reg-names = "gpmi-nand", "bch"; 97 interrupts = <88>, <41>; 98 interrupt-names = "gpmi-dma", "bch"; 99 clocks = <&clks 50>; 100 clock-names = "gpmi_io"; 101 dmas = <&dma_apbh 4>; 102 dma-names = "rx-tx"; 103 fsl,gpmi-dma-channel = <4>; 104 status = "disabled"; 105 }; 106 107 ssp0: ssp@80010000 { 108 #address-cells = <1>; 109 #size-cells = <0>; 110 reg = <0x80010000 0x2000>; 111 interrupts = <96 82>; 112 clocks = <&clks 46>; 113 dmas = <&dma_apbh 0>; 114 dma-names = "rx-tx"; 115 fsl,ssp-dma-channel = <0>; 116 status = "disabled"; 117 }; 118 119 ssp1: ssp@80012000 { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 reg = <0x80012000 0x2000>; 123 interrupts = <97 83>; 124 clocks = <&clks 47>; 125 dmas = <&dma_apbh 1>; 126 dma-names = "rx-tx"; 127 fsl,ssp-dma-channel = <1>; 128 status = "disabled"; 129 }; 130 131 ssp2: ssp@80014000 { 132 #address-cells = <1>; 133 #size-cells = <0>; 134 reg = <0x80014000 0x2000>; 135 interrupts = <98 84>; 136 clocks = <&clks 48>; 137 dmas = <&dma_apbh 2>; 138 dma-names = "rx-tx"; 139 fsl,ssp-dma-channel = <2>; 140 status = "disabled"; 141 }; 142 143 ssp3: ssp@80016000 { 144 #address-cells = <1>; 145 #size-cells = <0>; 146 reg = <0x80016000 0x2000>; 147 interrupts = <99 85>; 148 clocks = <&clks 49>; 149 dmas = <&dma_apbh 3>; 150 dma-names = "rx-tx"; 151 fsl,ssp-dma-channel = <3>; 152 status = "disabled"; 153 }; 154 155 pinctrl@80018000 { 156 #address-cells = <1>; 157 #size-cells = <0>; 158 compatible = "fsl,imx28-pinctrl", "simple-bus"; 159 reg = <0x80018000 0x2000>; 160 161 gpio0: gpio@0 { 162 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; 163 interrupts = <127>; 164 gpio-controller; 165 #gpio-cells = <2>; 166 interrupt-controller; 167 #interrupt-cells = <2>; 168 }; 169 170 gpio1: gpio@1 { 171 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; 172 interrupts = <126>; 173 gpio-controller; 174 #gpio-cells = <2>; 175 interrupt-controller; 176 #interrupt-cells = <2>; 177 }; 178 179 gpio2: gpio@2 { 180 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; 181 interrupts = <125>; 182 gpio-controller; 183 #gpio-cells = <2>; 184 interrupt-controller; 185 #interrupt-cells = <2>; 186 }; 187 188 gpio3: gpio@3 { 189 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; 190 interrupts = <124>; 191 gpio-controller; 192 #gpio-cells = <2>; 193 interrupt-controller; 194 #interrupt-cells = <2>; 195 }; 196 197 gpio4: gpio@4 { 198 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; 199 interrupts = <123>; 200 gpio-controller; 201 #gpio-cells = <2>; 202 interrupt-controller; 203 #interrupt-cells = <2>; 204 }; 205 206 duart_pins_a: duart@0 { 207 reg = <0>; 208 fsl,pinmux-ids = < 209 0x3102 /* MX28_PAD_PWM0__DUART_RX */ 210 0x3112 /* MX28_PAD_PWM1__DUART_TX */ 211 >; 212 fsl,drive-strength = <0>; 213 fsl,voltage = <1>; 214 fsl,pull-up = <0>; 215 }; 216 217 duart_pins_b: duart@1 { 218 reg = <1>; 219 fsl,pinmux-ids = < 220 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ 221 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ 222 >; 223 fsl,drive-strength = <0>; 224 fsl,voltage = <1>; 225 fsl,pull-up = <0>; 226 }; 227 228 duart_4pins_a: duart-4pins@0 { 229 reg = <0>; 230 fsl,pinmux-ids = < 231 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ 232 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ 233 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */ 234 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */ 235 >; 236 fsl,drive-strength = <0>; 237 fsl,voltage = <1>; 238 fsl,pull-up = <0>; 239 }; 240 241 gpmi_pins_a: gpmi-nand@0 { 242 reg = <0>; 243 fsl,pinmux-ids = < 244 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ 245 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ 246 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ 247 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ 248 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ 249 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ 250 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ 251 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ 252 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ 253 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ 254 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ 255 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ 256 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ 257 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ 258 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ 259 >; 260 fsl,drive-strength = <0>; 261 fsl,voltage = <1>; 262 fsl,pull-up = <0>; 263 }; 264 265 gpmi_status_cfg: gpmi-status-cfg { 266 fsl,pinmux-ids = < 267 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ 268 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ 269 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ 270 >; 271 fsl,drive-strength = <2>; 272 }; 273 274 auart0_pins_a: auart0@0 { 275 reg = <0>; 276 fsl,pinmux-ids = < 277 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ 278 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ 279 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ 280 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ 281 >; 282 fsl,drive-strength = <0>; 283 fsl,voltage = <1>; 284 fsl,pull-up = <0>; 285 }; 286 287 auart0_2pins_a: auart0-2pins@0 { 288 reg = <0>; 289 fsl,pinmux-ids = < 290 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ 291 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ 292 >; 293 fsl,drive-strength = <0>; 294 fsl,voltage = <1>; 295 fsl,pull-up = <0>; 296 }; 297 298 auart1_pins_a: auart1@0 { 299 reg = <0>; 300 fsl,pinmux-ids = < 301 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ 302 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ 303 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */ 304 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */ 305 >; 306 fsl,drive-strength = <0>; 307 fsl,voltage = <1>; 308 fsl,pull-up = <0>; 309 }; 310 311 auart1_2pins_a: auart1-2pins@0 { 312 reg = <0>; 313 fsl,pinmux-ids = < 314 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ 315 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ 316 >; 317 fsl,drive-strength = <0>; 318 fsl,voltage = <1>; 319 fsl,pull-up = <0>; 320 }; 321 322 auart2_2pins_a: auart2-2pins@0 { 323 reg = <0>; 324 fsl,pinmux-ids = < 325 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */ 326 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */ 327 >; 328 fsl,drive-strength = <0>; 329 fsl,voltage = <1>; 330 fsl,pull-up = <0>; 331 }; 332 333 auart3_pins_a: auart3@0 { 334 reg = <0>; 335 fsl,pinmux-ids = < 336 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ 337 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ 338 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ 339 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ 340 >; 341 fsl,drive-strength = <0>; 342 fsl,voltage = <1>; 343 fsl,pull-up = <0>; 344 }; 345 346 auart3_2pins_a: auart3-2pins@0 { 347 reg = <0>; 348 fsl,pinmux-ids = < 349 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */ 350 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */ 351 >; 352 fsl,drive-strength = <0>; 353 fsl,voltage = <1>; 354 fsl,pull-up = <0>; 355 }; 356 357 mac0_pins_a: mac0@0 { 358 reg = <0>; 359 fsl,pinmux-ids = < 360 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ 361 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ 362 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ 363 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ 364 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ 365 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ 366 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ 367 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ 368 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ 369 >; 370 fsl,drive-strength = <1>; 371 fsl,voltage = <1>; 372 fsl,pull-up = <1>; 373 }; 374 375 mac1_pins_a: mac1@0 { 376 reg = <0>; 377 fsl,pinmux-ids = < 378 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ 379 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ 380 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ 381 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ 382 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ 383 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ 384 >; 385 fsl,drive-strength = <1>; 386 fsl,voltage = <1>; 387 fsl,pull-up = <1>; 388 }; 389 390 mmc0_8bit_pins_a: mmc0-8bit@0 { 391 reg = <0>; 392 fsl,pinmux-ids = < 393 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ 394 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ 395 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ 396 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ 397 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ 398 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ 399 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ 400 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ 401 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ 402 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ 403 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ 404 >; 405 fsl,drive-strength = <1>; 406 fsl,voltage = <1>; 407 fsl,pull-up = <1>; 408 }; 409 410 mmc0_4bit_pins_a: mmc0-4bit@0 { 411 reg = <0>; 412 fsl,pinmux-ids = < 413 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ 414 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ 415 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ 416 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ 417 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ 418 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ 419 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ 420 >; 421 fsl,drive-strength = <1>; 422 fsl,voltage = <1>; 423 fsl,pull-up = <1>; 424 }; 425 426 mmc0_cd_cfg: mmc0-cd-cfg { 427 fsl,pinmux-ids = < 428 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ 429 >; 430 fsl,pull-up = <0>; 431 }; 432 433 mmc0_sck_cfg: mmc0-sck-cfg { 434 fsl,pinmux-ids = < 435 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ 436 >; 437 fsl,drive-strength = <2>; 438 fsl,pull-up = <0>; 439 }; 440 441 i2c0_pins_a: i2c0@0 { 442 reg = <0>; 443 fsl,pinmux-ids = < 444 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ 445 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ 446 >; 447 fsl,drive-strength = <1>; 448 fsl,voltage = <1>; 449 fsl,pull-up = <1>; 450 }; 451 452 i2c0_pins_b: i2c0@1 { 453 reg = <1>; 454 fsl,pinmux-ids = < 455 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ 456 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ 457 >; 458 fsl,drive-strength = <1>; 459 fsl,voltage = <1>; 460 fsl,pull-up = <1>; 461 }; 462 463 i2c1_pins_a: i2c1@0 { 464 reg = <0>; 465 fsl,pinmux-ids = < 466 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ 467 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ 468 >; 469 fsl,drive-strength = <1>; 470 fsl,voltage = <1>; 471 fsl,pull-up = <1>; 472 }; 473 474 saif0_pins_a: saif0@0 { 475 reg = <0>; 476 fsl,pinmux-ids = < 477 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ 478 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ 479 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ 480 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ 481 >; 482 fsl,drive-strength = <2>; 483 fsl,voltage = <1>; 484 fsl,pull-up = <1>; 485 }; 486 487 saif1_pins_a: saif1@0 { 488 reg = <0>; 489 fsl,pinmux-ids = < 490 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ 491 >; 492 fsl,drive-strength = <2>; 493 fsl,voltage = <1>; 494 fsl,pull-up = <1>; 495 }; 496 497 pwm0_pins_a: pwm0@0 { 498 reg = <0>; 499 fsl,pinmux-ids = < 500 0x3100 /* MX28_PAD_PWM0__PWM_0 */ 501 >; 502 fsl,drive-strength = <0>; 503 fsl,voltage = <1>; 504 fsl,pull-up = <0>; 505 }; 506 507 pwm2_pins_a: pwm2@0 { 508 reg = <0>; 509 fsl,pinmux-ids = < 510 0x3120 /* MX28_PAD_PWM2__PWM_2 */ 511 >; 512 fsl,drive-strength = <0>; 513 fsl,voltage = <1>; 514 fsl,pull-up = <0>; 515 }; 516 517 pwm3_pins_a: pwm3@0 { 518 reg = <0>; 519 fsl,pinmux-ids = < 520 0x31c0 /* MX28_PAD_PWM3__PWM_3 */ 521 >; 522 fsl,drive-strength = <0>; 523 fsl,voltage = <1>; 524 fsl,pull-up = <0>; 525 }; 526 527 pwm3_pins_b: pwm3@1 { 528 reg = <1>; 529 fsl,pinmux-ids = < 530 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */ 531 >; 532 fsl,drive-strength = <0>; 533 fsl,voltage = <1>; 534 fsl,pull-up = <0>; 535 }; 536 537 pwm4_pins_a: pwm4@0 { 538 reg = <0>; 539 fsl,pinmux-ids = < 540 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ 541 >; 542 fsl,drive-strength = <0>; 543 fsl,voltage = <1>; 544 fsl,pull-up = <0>; 545 }; 546 547 lcdif_24bit_pins_a: lcdif-24bit@0 { 548 reg = <0>; 549 fsl,pinmux-ids = < 550 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ 551 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ 552 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ 553 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ 554 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ 555 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ 556 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ 557 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ 558 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ 559 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ 560 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ 561 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ 562 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ 563 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ 564 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ 565 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ 566 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ 567 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ 568 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ 569 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ 570 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ 571 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ 572 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ 573 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ 574 >; 575 fsl,drive-strength = <0>; 576 fsl,voltage = <1>; 577 fsl,pull-up = <0>; 578 }; 579 580 lcdif_16bit_pins_a: lcdif-16bit@0 { 581 reg = <0>; 582 fsl,pinmux-ids = < 583 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ 584 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ 585 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ 586 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ 587 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ 588 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ 589 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ 590 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ 591 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ 592 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ 593 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ 594 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ 595 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ 596 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ 597 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ 598 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ 599 >; 600 fsl,drive-strength = <0>; 601 fsl,voltage = <1>; 602 fsl,pull-up = <0>; 603 }; 604 605 can0_pins_a: can0@0 { 606 reg = <0>; 607 fsl,pinmux-ids = < 608 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ 609 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ 610 >; 611 fsl,drive-strength = <0>; 612 fsl,voltage = <1>; 613 fsl,pull-up = <0>; 614 }; 615 616 can1_pins_a: can1@0 { 617 reg = <0>; 618 fsl,pinmux-ids = < 619 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ 620 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ 621 >; 622 fsl,drive-strength = <0>; 623 fsl,voltage = <1>; 624 fsl,pull-up = <0>; 625 }; 626 627 spi2_pins_a: spi2@0 { 628 reg = <0>; 629 fsl,pinmux-ids = < 630 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ 631 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ 632 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ 633 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ 634 >; 635 fsl,drive-strength = <1>; 636 fsl,voltage = <1>; 637 fsl,pull-up = <1>; 638 }; 639 640 usbphy0_pins_a: usbphy0@0 { 641 reg = <0>; 642 fsl,pinmux-ids = < 643 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ 644 >; 645 fsl,drive-strength = <2>; 646 fsl,voltage = <1>; 647 fsl,pull-up = <0>; 648 }; 649 650 usbphy0_pins_b: usbphy0@1 { 651 reg = <1>; 652 fsl,pinmux-ids = < 653 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ 654 >; 655 fsl,drive-strength = <2>; 656 fsl,voltage = <1>; 657 fsl,pull-up = <0>; 658 }; 659 660 usbphy1_pins_a: usbphy1@0 { 661 reg = <0>; 662 fsl,pinmux-ids = < 663 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ 664 >; 665 fsl,drive-strength = <2>; 666 fsl,voltage = <1>; 667 fsl,pull-up = <0>; 668 }; 669 }; 670 671 digctl@8001c000 { 672 compatible = "fsl,imx28-digctl"; 673 reg = <0x8001c000 0x2000>; 674 interrupts = <89>; 675 status = "disabled"; 676 }; 677 678 etm@80022000 { 679 reg = <0x80022000 0x2000>; 680 status = "disabled"; 681 }; 682 683 dma_apbx: dma-apbx@80024000 { 684 compatible = "fsl,imx28-dma-apbx"; 685 reg = <0x80024000 0x2000>; 686 interrupts = <78 79 66 0 687 80 81 68 69 688 70 71 72 73 689 74 75 76 77>; 690 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", 691 "saif0", "saif1", "i2c0", "i2c1", 692 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", 693 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; 694 #dma-cells = <1>; 695 dma-channels = <16>; 696 clocks = <&clks 26>; 697 }; 698 699 dcp@80028000 { 700 reg = <0x80028000 0x2000>; 701 interrupts = <52 53 54>; 702 status = "disabled"; 703 }; 704 705 pxp@8002a000 { 706 reg = <0x8002a000 0x2000>; 707 interrupts = <39>; 708 status = "disabled"; 709 }; 710 711 ocotp@8002c000 { 712 compatible = "fsl,ocotp"; 713 reg = <0x8002c000 0x2000>; 714 status = "disabled"; 715 }; 716 717 axi-ahb@8002e000 { 718 reg = <0x8002e000 0x2000>; 719 status = "disabled"; 720 }; 721 722 lcdif@80030000 { 723 compatible = "fsl,imx28-lcdif"; 724 reg = <0x80030000 0x2000>; 725 interrupts = <38 86>; 726 clocks = <&clks 55>; 727 dmas = <&dma_apbh 13>; 728 dma-names = "rx"; 729 status = "disabled"; 730 }; 731 732 can0: can@80032000 { 733 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; 734 reg = <0x80032000 0x2000>; 735 interrupts = <8>; 736 clocks = <&clks 58>, <&clks 58>; 737 clock-names = "ipg", "per"; 738 status = "disabled"; 739 }; 740 741 can1: can@80034000 { 742 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; 743 reg = <0x80034000 0x2000>; 744 interrupts = <9>; 745 clocks = <&clks 59>, <&clks 59>; 746 clock-names = "ipg", "per"; 747 status = "disabled"; 748 }; 749 750 simdbg@8003c000 { 751 reg = <0x8003c000 0x200>; 752 status = "disabled"; 753 }; 754 755 simgpmisel@8003c200 { 756 reg = <0x8003c200 0x100>; 757 status = "disabled"; 758 }; 759 760 simsspsel@8003c300 { 761 reg = <0x8003c300 0x100>; 762 status = "disabled"; 763 }; 764 765 simmemsel@8003c400 { 766 reg = <0x8003c400 0x100>; 767 status = "disabled"; 768 }; 769 770 gpiomon@8003c500 { 771 reg = <0x8003c500 0x100>; 772 status = "disabled"; 773 }; 774 775 simenet@8003c700 { 776 reg = <0x8003c700 0x100>; 777 status = "disabled"; 778 }; 779 780 armjtag@8003c800 { 781 reg = <0x8003c800 0x100>; 782 status = "disabled"; 783 }; 784 }; 785 786 apbx@80040000 { 787 compatible = "simple-bus"; 788 #address-cells = <1>; 789 #size-cells = <1>; 790 reg = <0x80040000 0x40000>; 791 ranges; 792 793 clks: clkctrl@80040000 { 794 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; 795 reg = <0x80040000 0x2000>; 796 #clock-cells = <1>; 797 }; 798 799 saif0: saif@80042000 { 800 compatible = "fsl,imx28-saif"; 801 reg = <0x80042000 0x2000>; 802 interrupts = <59 80>; 803 clocks = <&clks 53>; 804 dmas = <&dma_apbx 4>; 805 dma-names = "rx-tx"; 806 fsl,saif-dma-channel = <4>; 807 status = "disabled"; 808 }; 809 810 power@80044000 { 811 reg = <0x80044000 0x2000>; 812 status = "disabled"; 813 }; 814 815 saif1: saif@80046000 { 816 compatible = "fsl,imx28-saif"; 817 reg = <0x80046000 0x2000>; 818 interrupts = <58 81>; 819 clocks = <&clks 54>; 820 dmas = <&dma_apbx 5>; 821 dma-names = "rx-tx"; 822 fsl,saif-dma-channel = <5>; 823 status = "disabled"; 824 }; 825 826 lradc@80050000 { 827 compatible = "fsl,imx28-lradc"; 828 reg = <0x80050000 0x2000>; 829 interrupts = <10 14 15 16 17 18 19 830 20 21 22 23 24 25>; 831 status = "disabled"; 832 }; 833 834 spdif@80054000 { 835 reg = <0x80054000 0x2000>; 836 interrupts = <45 66>; 837 dmas = <&dma_apbx 2>; 838 dma-names = "tx"; 839 status = "disabled"; 840 }; 841 842 rtc@80056000 { 843 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; 844 reg = <0x80056000 0x2000>; 845 interrupts = <29>; 846 }; 847 848 i2c0: i2c@80058000 { 849 #address-cells = <1>; 850 #size-cells = <0>; 851 compatible = "fsl,imx28-i2c"; 852 reg = <0x80058000 0x2000>; 853 interrupts = <111 68>; 854 clock-frequency = <100000>; 855 dmas = <&dma_apbx 6>; 856 dma-names = "rx-tx"; 857 fsl,i2c-dma-channel = <6>; 858 status = "disabled"; 859 }; 860 861 i2c1: i2c@8005a000 { 862 #address-cells = <1>; 863 #size-cells = <0>; 864 compatible = "fsl,imx28-i2c"; 865 reg = <0x8005a000 0x2000>; 866 interrupts = <110 69>; 867 clock-frequency = <100000>; 868 dmas = <&dma_apbx 7>; 869 dma-names = "rx-tx"; 870 fsl,i2c-dma-channel = <7>; 871 status = "disabled"; 872 }; 873 874 pwm: pwm@80064000 { 875 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; 876 reg = <0x80064000 0x2000>; 877 clocks = <&clks 44>; 878 #pwm-cells = <2>; 879 fsl,pwm-number = <8>; 880 status = "disabled"; 881 }; 882 883 timrot@80068000 { 884 compatible = "fsl,imx28-timrot", "fsl,timrot"; 885 reg = <0x80068000 0x2000>; 886 interrupts = <48 49 50 51>; 887 clocks = <&clks 26>; 888 }; 889 890 auart0: serial@8006a000 { 891 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 892 reg = <0x8006a000 0x2000>; 893 interrupts = <112 70 71>; 894 dmas = <&dma_apbx 8>, <&dma_apbx 9>; 895 dma-names = "rx", "tx"; 896 fsl,auart-dma-channel = <8 9>; 897 clocks = <&clks 45>; 898 status = "disabled"; 899 }; 900 901 auart1: serial@8006c000 { 902 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 903 reg = <0x8006c000 0x2000>; 904 interrupts = <113 72 73>; 905 dmas = <&dma_apbx 10>, <&dma_apbx 11>; 906 dma-names = "rx", "tx"; 907 clocks = <&clks 45>; 908 status = "disabled"; 909 }; 910 911 auart2: serial@8006e000 { 912 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 913 reg = <0x8006e000 0x2000>; 914 interrupts = <114 74 75>; 915 dmas = <&dma_apbx 12>, <&dma_apbx 13>; 916 dma-names = "rx", "tx"; 917 clocks = <&clks 45>; 918 status = "disabled"; 919 }; 920 921 auart3: serial@80070000 { 922 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 923 reg = <0x80070000 0x2000>; 924 interrupts = <115 76 77>; 925 dmas = <&dma_apbx 14>, <&dma_apbx 15>; 926 dma-names = "rx", "tx"; 927 clocks = <&clks 45>; 928 status = "disabled"; 929 }; 930 931 auart4: serial@80072000 { 932 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 933 reg = <0x80072000 0x2000>; 934 interrupts = <116 78 79>; 935 dmas = <&dma_apbx 0>, <&dma_apbx 1>; 936 dma-names = "rx", "tx"; 937 clocks = <&clks 45>; 938 status = "disabled"; 939 }; 940 941 duart: serial@80074000 { 942 compatible = "arm,pl011", "arm,primecell"; 943 reg = <0x80074000 0x1000>; 944 interrupts = <47>; 945 clocks = <&clks 45>, <&clks 26>; 946 clock-names = "uart", "apb_pclk"; 947 status = "disabled"; 948 }; 949 950 usbphy0: usbphy@8007c000 { 951 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; 952 reg = <0x8007c000 0x2000>; 953 clocks = <&clks 62>; 954 status = "disabled"; 955 }; 956 957 usbphy1: usbphy@8007e000 { 958 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; 959 reg = <0x8007e000 0x2000>; 960 clocks = <&clks 63>; 961 status = "disabled"; 962 }; 963 }; 964 }; 965 966 ahb@80080000 { 967 compatible = "simple-bus"; 968 #address-cells = <1>; 969 #size-cells = <1>; 970 reg = <0x80080000 0x80000>; 971 ranges; 972 973 usb0: usb@80080000 { 974 compatible = "fsl,imx28-usb", "fsl,imx27-usb"; 975 reg = <0x80080000 0x10000>; 976 interrupts = <93>; 977 clocks = <&clks 60>; 978 fsl,usbphy = <&usbphy0>; 979 status = "disabled"; 980 }; 981 982 usb1: usb@80090000 { 983 compatible = "fsl,imx28-usb", "fsl,imx27-usb"; 984 reg = <0x80090000 0x10000>; 985 interrupts = <92>; 986 clocks = <&clks 61>; 987 fsl,usbphy = <&usbphy1>; 988 status = "disabled"; 989 }; 990 991 dflpt@800c0000 { 992 reg = <0x800c0000 0x10000>; 993 status = "disabled"; 994 }; 995 996 mac0: ethernet@800f0000 { 997 compatible = "fsl,imx28-fec"; 998 reg = <0x800f0000 0x4000>; 999 interrupts = <101>; 1000 clocks = <&clks 57>, <&clks 57>, <&clks 64>; 1001 clock-names = "ipg", "ahb", "enet_out"; 1002 status = "disabled"; 1003 }; 1004 1005 mac1: ethernet@800f4000 { 1006 compatible = "fsl,imx28-fec"; 1007 reg = <0x800f4000 0x4000>; 1008 interrupts = <102>; 1009 clocks = <&clks 57>, <&clks 57>; 1010 clock-names = "ipg", "ahb"; 1011 status = "disabled"; 1012 }; 1013 1014 switch@800f8000 { 1015 reg = <0x800f8000 0x8000>; 1016 status = "disabled"; 1017 }; 1018 1019 }; 1020}; 1021